maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[X86] Generalize X86PadShortFunction to work with TargetSchedModel 

Pre-commit for D45486, don't rely on itinerary scheduler model to determine latencies for padding, use the generic TargetSchedModel::computeInstrLatency call.

Also, replace hard coded (atom specific) 2*uop creation per padding cycle with a version based on the scheduler model's issue width.

Differential Revision: https://reviews.llvm.org/D45486

llvm-svn: 329834
This commit is contained in:
Simon Pilgrim 2018-04-11 18:05:17 +00:00
parent b7a747e6a3
commit 7f321d8c24
1 changed files with 12 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
llvm/lib/Target/X86/X86PadShortFunction.cpp
View File

@ -21,7 +21,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/IR/Function.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
@ -49,7 +49,7 @@ namespace {
struct PadShortFunc : public MachineFunctionPass {
static char ID;
PadShortFunc() : MachineFunctionPass(ID)
, Threshold(4), STI(nullptr), TII(nullptr) {}
, Threshold(4) {}
bool runOnMachineFunction(MachineFunction &MF) override;
@ -82,8 +82,7 @@ namespace {
// VisitedBBs - Cache of previously visited BBs.
DenseMap<MachineBasicBlock*, VisitedBBInfo> VisitedBBs;
const X86Subtarget *STI;
const TargetInstrInfo *TII;
TargetSchedModel TSM;
};
char PadShortFunc::ID = 0;
@ -99,15 +98,13 @@ bool PadShortFunc::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
if (MF.getFunction().optForSize()) {
return false;
}
STI = &MF.getSubtarget<X86Subtarget>();
if (!STI->padShortFunctions())
if (MF.getFunction().optForSize())
return false;
TII = STI->getInstrInfo();
if (!MF.getSubtarget<X86Subtarget>().padShortFunctions())
return false;
TSM.init(&MF.getSubtarget());
// Search through basic blocks and mark the ones that have early returns
ReturnBBs.clear();
@ -195,7 +192,7 @@ bool PadShortFunc::cyclesUntilReturn(MachineBasicBlock *MBB,
return true;
}
CyclesToEnd += TII->getInstrLatency(STI->getInstrItineraryData(), MI);
CyclesToEnd += TSM.computeInstrLatency(&MI);
}
VisitedBBs[MBB] = VisitedBBInfo(false, CyclesToEnd);
@ -209,9 +206,8 @@ void PadShortFunc::addPadding(MachineBasicBlock *MBB,
MachineBasicBlock::iterator &MBBI,
unsigned int NOOPsToAdd) {
DebugLoc DL = MBBI->getDebugLoc();
unsigned IssueWidth = TSM.getIssueWidth();
while (NOOPsToAdd-- > 0) {
BuildMI(*MBB, MBBI, DL, TII->get(X86::NOOP));
BuildMI(*MBB, MBBI, DL, TII->get(X86::NOOP));
}
for (unsigned i = 0, e = IssueWidth * NOOPsToAdd; i != e; ++i)
BuildMI(*MBB, MBBI, DL, TSM.getInstrInfo()->get(X86::NOOP));
}