[GlobalISel] Move method definition to the proper file. NFC.

llvm-svn: 298221
This commit is contained in:
Ahmed Bougacha 2017-03-19 16:12:48 +00:00
parent 531e275aa8
commit 7f2d17331c
2 changed files with 21 additions and 19 deletions

View File

@ -177,22 +177,3 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
// FIXME: Should we accurately track changes?
return true;
}
bool InstructionSelector::isOperandImmEqual(
const MachineOperand &MO, int64_t Value,
const MachineRegisterInfo &MRI) const {
// TODO: We should also test isImm() and isCImm() too but this isn't required
// until a DAGCombine equivalent is implemented.
if (MO.isReg()) {
MachineInstr *Def = MRI.getVRegDef(MO.getReg());
if (Def->getOpcode() != TargetOpcode::G_CONSTANT)
return false;
assert(Def->getOperand(1).isCImm() &&
"G_CONSTANT values must be constants");
const ConstantInt &Imm = *Def->getOperand(1).getCImm();
return Imm.getBitWidth() <= 64 && Imm.getSExtValue() == Value;
}
return false;
}

View File

@ -14,6 +14,8 @@
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
@ -65,3 +67,22 @@ bool InstructionSelector::constrainSelectedInstRegOperands(
}
return true;
}
bool InstructionSelector::isOperandImmEqual(
const MachineOperand &MO, int64_t Value,
const MachineRegisterInfo &MRI) const {
// TODO: We should also test isImm() and isCImm() too but this isn't required
// until a DAGCombine equivalent is implemented.
if (MO.isReg()) {
MachineInstr *Def = MRI.getVRegDef(MO.getReg());
if (Def->getOpcode() != TargetOpcode::G_CONSTANT)
return false;
assert(Def->getOperand(1).isCImm() &&
"G_CONSTANT values must be constants");
const ConstantInt &Imm = *Def->getOperand(1).getCImm();
return Imm.getBitWidth() <= 64 && Imm.getSExtValue() == Value;
}
return false;
}