forked from OSchip/llvm-project
[GlobalISel] Move method definition to the proper file. NFC.
llvm-svn: 298221
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@ -177,22 +177,3 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
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// FIXME: Should we accurately track changes?
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return true;
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}
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bool InstructionSelector::isOperandImmEqual(
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const MachineOperand &MO, int64_t Value,
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const MachineRegisterInfo &MRI) const {
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// TODO: We should also test isImm() and isCImm() too but this isn't required
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// until a DAGCombine equivalent is implemented.
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if (MO.isReg()) {
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MachineInstr *Def = MRI.getVRegDef(MO.getReg());
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if (Def->getOpcode() != TargetOpcode::G_CONSTANT)
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return false;
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assert(Def->getOperand(1).isCImm() &&
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"G_CONSTANT values must be constants");
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const ConstantInt &Imm = *Def->getOperand(1).getCImm();
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return Imm.getBitWidth() <= 64 && Imm.getSExtValue() == Value;
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}
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return false;
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}
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@ -14,6 +14,8 @@
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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@ -65,3 +67,22 @@ bool InstructionSelector::constrainSelectedInstRegOperands(
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}
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return true;
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}
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bool InstructionSelector::isOperandImmEqual(
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const MachineOperand &MO, int64_t Value,
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const MachineRegisterInfo &MRI) const {
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// TODO: We should also test isImm() and isCImm() too but this isn't required
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// until a DAGCombine equivalent is implemented.
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if (MO.isReg()) {
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MachineInstr *Def = MRI.getVRegDef(MO.getReg());
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if (Def->getOpcode() != TargetOpcode::G_CONSTANT)
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return false;
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assert(Def->getOperand(1).isCImm() &&
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"G_CONSTANT values must be constants");
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const ConstantInt &Imm = *Def->getOperand(1).getCImm();
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return Imm.getBitWidth() <= 64 && Imm.getSExtValue() == Value;
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}
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return false;
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}
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