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[SimplifyCFG] FoldTwoEntryPHINode(): bailout on inverted logical and/or (PR51149) 

The logical (select) form of and/or will now be a source of problems.
We don't really account for it's inverted form, yet it exists,
and presumably we should treat it just like non-inverted form:
https://alive2.llvm.org/ce/z/BU9AXk

https://bugs.llvm.org/show_bug.cgi?id=51149 reports a reportedly-serious
perf regression that will hopefully be mitigated by this.
This commit is contained in:
Roman Lebedev 2021-07-22 22:11:46 +03:00
parent 952dc2e561
commit 7ef6f01909
No known key found for this signature in database
GPG Key ID: 083C3EBB4A1689E0
2 changed files with 16 additions and 5 deletions
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9
llvm/lib/Transforms/Utils/SimplifyCFG.cpp
View File

@ -2771,12 +2771,15 @@ static bool FoldTwoEntryPHINode(PHINode *PN, const TargetTransformInfo &TTI,
};
// Don't fold i1 branches on PHIs which contain binary operators or
// select form of or/ands, unless one of the incoming values is an 'not' and
// another one is freely invertible.
// (possibly inverted) select form of or/ands, unless one of
// the incoming values is an 'not' and another one is freely invertible.
// These can often be turned into switches and other things.
auto IsBinOpOrAnd = [](Value *V) {
return match(
V, m_CombineOr(m_BinOp(), m_CombineOr(m_LogicalAnd(), m_LogicalOr())));
V, m_CombineOr(
m_BinOp(),
m_CombineOr(m_Select(m_Value(), m_ImmConstant(), m_Value()),
m_Select(m_Value(), m_Value(), m_ImmConstant()))));
};
if (PN->getType()->isIntegerTy(1) &&
(IsBinOpOrAnd(PN->getIncomingValue(0)) ||

12
llvm/test/Transforms/SimplifyCFG/two-entry-phi-node.ll
View File

@ -200,10 +200,14 @@ define i1 @t6_nor_logical2(i8 %v0, i8 %v1, i8 %v2, i1 %v3) {
; CHECK-LABEL: @t6_nor_logical2(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0
; CHECK-NEXT: br i1 [[C0]], label [[PRED0:%.*]], label [[END:%.*]]
; CHECK: pred0:
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1:%.*]], 0
; CHECK-NEXT: [[C2:%.*]] = icmp ne i8 [[V2:%.*]], 0
; CHECK-NEXT: [[COMPUTED:%.*]] = select i1 [[C1]], i1 false, i1 [[C2]]
; CHECK-NEXT: [[R:%.*]] = select i1 [[C0]], i1 [[COMPUTED]], i1 [[V3:%.*]]
; CHECK-NEXT: br label [[END]]
; CHECK: end:
; CHECK-NEXT: [[R:%.*]] = phi i1 [ [[COMPUTED]], [[PRED0]] ], [ [[V3:%.*]], [[ENTRY:%.*]] ]
; CHECK-NEXT: ret i1 [[R]]
;
entry:
@ -290,10 +294,14 @@ define i1 @t9_nand_logical2(i8 %v0, i8 %v1, i8 %v2, i1 %v3) {
; CHECK-LABEL: @t9_nand_logical2(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0
; CHECK-NEXT: br i1 [[C0]], label [[PRED0:%.*]], label [[END:%.*]]
; CHECK: pred0:
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1:%.*]], 0
; CHECK-NEXT: [[C2:%.*]] = icmp ne i8 [[V2:%.*]], 0
; CHECK-NEXT: [[COMPUTED:%.*]] = select i1 [[C1]], i1 [[C2]], i1 true
; CHECK-NEXT: [[R:%.*]] = select i1 [[C0]], i1 [[COMPUTED]], i1 [[V3:%.*]]
; CHECK-NEXT: br label [[END]]
; CHECK: end:
; CHECK-NEXT: [[R:%.*]] = phi i1 [ [[COMPUTED]], [[PRED0]] ], [ [[V3:%.*]], [[ENTRY:%.*]] ]
; CHECK-NEXT: ret i1 [[R]]
;
entry: