forked from OSchip/llvm-project
[X86] Split immediate shifts tests. NFCI.
A future patch will combine logical shifts more aggressively. llvm-svn: 350396
This commit is contained in:
Simon Pilgrim
parent
7902405c42
commit
7ee2285625
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@ -1,52 +1,93 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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;RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=knl | FileCheck %s --check-prefix=CHECK --check-prefix=KNL
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;RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s --check-prefix=CHECK --check-prefix=SKX
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;RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=knl | FileCheck %s --check-prefixes=CHECK,KNL
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;RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s --check-prefixes=CHECK,SKX
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define <16 x i32> @shift_16_i32(<16 x i32> %a) {
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; CHECK-LABEL: shift_16_i32:
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define <16 x i32> @ashr_16_i32(<16 x i32> %a) {
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; CHECK-LABEL: ashr_16_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsrld $1, %zmm0, %zmm0
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; CHECK-NEXT: vpslld $12, %zmm0, %zmm0
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; CHECK-NEXT: vpsrad $12, %zmm0, %zmm0
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; CHECK-NEXT: retq
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%b = lshr <16 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%c = shl <16 x i32> %b, <i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12>
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%d = ashr <16 x i32> %c, <i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12>
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ret <16 x i32> %d;
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%b = ashr <16 x i32> %a, <i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12>
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ret <16 x i32> %b
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}
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define <8 x i64> @shift_8_i64(<8 x i64> %a) {
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; CHECK-LABEL: shift_8_i64:
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define <16 x i32> @lshr_16_i32(<16 x i32> %a) {
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; CHECK-LABEL: lshr_16_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsrld $1, %zmm0, %zmm0
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; CHECK-NEXT: retq
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%b = lshr <16 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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ret <16 x i32> %b
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}
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define <16 x i32> @shl_16_i32(<16 x i32> %a) {
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; CHECK-LABEL: shl_16_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpslld $12, %zmm0, %zmm0
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; CHECK-NEXT: retq
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%b = shl <16 x i32> %a, <i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12>
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ret <16 x i32> %b
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}
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define <8 x i64> @ashr_8_i64(<8 x i64> %a) {
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; CHECK-LABEL: ashr_8_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsrlq $1, %zmm0, %zmm0
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; CHECK-NEXT: vpsllq $12, %zmm0, %zmm0
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; CHECK-NEXT: vpsraq $12, %zmm0, %zmm0
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; CHECK-NEXT: retq
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%b = lshr <8 x i64> %a, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>
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%c = shl <8 x i64> %b, <i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12>
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%d = ashr <8 x i64> %c, <i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12>
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ret <8 x i64> %d;
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%b = ashr <8 x i64> %a, <i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12>
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ret <8 x i64> %b
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}
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define <4 x i64> @shift_4_i64(<4 x i64> %a) {
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; KNL-LABEL: shift_4_i64:
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define <8 x i64> @lshr_8_i64(<8 x i64> %a) {
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; CHECK-LABEL: lshr_8_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsrlq $1, %zmm0, %zmm0
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; CHECK-NEXT: retq
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%b = lshr <8 x i64> %a, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>
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ret <8 x i64> %b
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}
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define <8 x i64> @shl_8_i64(<8 x i64> %a) {
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; CHECK-LABEL: shl_8_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsllq $12, %zmm0, %zmm0
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; CHECK-NEXT: retq
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%b = shl <8 x i64> %a, <i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12>
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ret <8 x i64> %b
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}
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define <4 x i64> @ashr_4_i64(<4 x i64> %a) {
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; KNL-LABEL: ashr_4_i64:
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; KNL: # %bb.0:
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; KNL-NEXT: vpsrlq $1, %ymm0, %ymm0
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; KNL-NEXT: vpsllq $12, %ymm0, %ymm0
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; KNL-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
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; KNL-NEXT: vpsraq $12, %zmm0, %zmm0
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; KNL-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
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; KNL-NEXT: retq
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;
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; SKX-LABEL: shift_4_i64:
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; SKX-LABEL: ashr_4_i64:
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; SKX: # %bb.0:
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; SKX-NEXT: vpsrlq $1, %ymm0, %ymm0
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; SKX-NEXT: vpsllq $12, %ymm0, %ymm0
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; SKX-NEXT: vpsraq $12, %ymm0, %ymm0
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; SKX-NEXT: retq
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%b = ashr <4 x i64> %a, <i64 12, i64 12, i64 12, i64 12>
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ret <4 x i64> %b
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}
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define <4 x i64> @lshr_4_i64(<4 x i64> %a) {
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; CHECK-LABEL: lshr_4_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsrlq $1, %ymm0, %ymm0
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; CHECK-NEXT: retq
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%b = lshr <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
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%c = shl <4 x i64> %b, <i64 12, i64 12, i64 12, i64 12>
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%d = ashr <4 x i64> %c, <i64 12, i64 12, i64 12, i64 12>
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ret <4 x i64> %d;
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ret <4 x i64> %b
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}
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define <4 x i64> @shl_4_i64(<4 x i64> %a) {
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; CHECK-LABEL: shl_4_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsllq $12, %ymm0, %ymm0
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; CHECK-NEXT: retq
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%b = shl <4 x i64> %a, <i64 12, i64 12, i64 12, i64 12>
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ret <4 x i64> %b
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}
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define <8 x i64> @variable_shl4(<8 x i64> %x, <8 x i64> %y) {
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