forked from OSchip/llvm-project
[RISCV][RFC] add inst support of zbkb
This commit add instructions supports of `zbkb` which defined in scalar cryptography extension version v1.0.0 (has been ratified already). Most of the zbkb directives reuse parts of the zbp and zbb directives, so this patch just modified some of the inst aliases and predicates. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D117640
This commit is contained in:
Wu Xinlong
parent
82af95029e
commit
7ee1c162cc
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@ -55,6 +55,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
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{"zbb", RISCVExtensionVersion{1, 0}},
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{"zbc", RISCVExtensionVersion{1, 0}},
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{"zbs", RISCVExtensionVersion{1, 0}},
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{"zbkb", RISCVExtensionVersion{1, 0}},
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};
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static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
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@ -143,6 +143,26 @@ def HasStdExtZbbOrZbp
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"'Zbb' (Base 'B' Instructions) or "
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"'Zbp' (Permutation 'B' Instructions)">;
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def FeatureStdExtZbkb
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: SubtargetFeature<"zbkb", "HasStdExtZbkb", "true",
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"'Zbkb' (Bitmanip instructions for Cryptography)">;
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def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
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AssemblerPredicate<(all_of FeatureStdExtZbkb),
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"'Zbkb' (Bitmanip instructions for Cryptography)">;
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def HasStdExtZbpOrZbkb
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: Predicate<"Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkb()">,
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AssemblerPredicate<(any_of FeatureStdExtZbp, FeatureStdExtZbkb),
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"'Zbp' (Permutation 'B' Instructions) or "
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"'Zbkb' (Bitmanip instructions for Cryptography)">;
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def HasStdExtZbbOrZbpOrZbkb
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: Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkb()">,
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AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbp, FeatureStdExtZbkb),
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"'Zbb' (Base 'B' Instructions) or "
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"'Zbp' (Permutation 'B' Instructions) or "
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"'Zbkb' (Bitmanip instructions for Cryptography)">;
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def FeatureNoRVCHints
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: SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
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"Disable RVC Hint Instructions.">;
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@ -313,14 +313,14 @@ class RVBTernaryImm5<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode,
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtZbbOrZbp] in {
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let Predicates = [HasStdExtZbbOrZbpOrZbkb] in {
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def ANDN : ALU_rr<0b0100000, 0b111, "andn">,
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Sched<[WriteIALU, ReadIALU, ReadIALU]>;
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def ORN : ALU_rr<0b0100000, 0b110, "orn">,
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Sched<[WriteIALU, ReadIALU, ReadIALU]>;
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def XNOR : ALU_rr<0b0100000, 0b100, "xnor">,
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Sched<[WriteIALU, ReadIALU, ReadIALU]>;
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} // Predicates = [HasStdExtZbbOrZbp]
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} // Predicates = [HasStdExtZbbOrZbpOrZbkb]
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let Predicates = [HasStdExtZba] in {
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def SH1ADD : ALU_rr<0b0010000, 0b010, "sh1add">,
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@ -331,12 +331,12 @@ def SH3ADD : ALU_rr<0b0010000, 0b110, "sh3add">,
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Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
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} // Predicates = [HasStdExtZba]
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let Predicates = [HasStdExtZbbOrZbp] in {
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let Predicates = [HasStdExtZbbOrZbpOrZbkb] in {
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def ROL : ALU_rr<0b0110000, 0b001, "rol">,
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Sched<[WriteRotateReg, ReadRotateReg, ReadRotateReg]>;
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def ROR : ALU_rr<0b0110000, 0b101, "ror">,
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Sched<[WriteRotateReg, ReadRotateReg, ReadRotateReg]>;
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} // Predicates = [HasStdExtZbbOrZbp]
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} // Predicates = [HasStdExtZbbOrZbpOrZbkb]
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let Predicates = [HasStdExtZbs] in {
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def BCLR : ALU_rr<0b0100100, 0b001, "bclr">,
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@ -360,7 +360,7 @@ def XPERMB : ALU_rr<0b0010100, 0b100, "xperm.b">, Sched<[]>;
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def XPERMH : ALU_rr<0b0010100, 0b110, "xperm.h">, Sched<[]>;
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} // Predicates = [HasStdExtZbp]
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let Predicates = [HasStdExtZbbOrZbp] in
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let Predicates = [HasStdExtZbbOrZbpOrZbkb] in
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def RORI : RVBShift_ri<0b01100, 0b101, OPC_OP_IMM, "rori">,
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Sched<[WriteRotateImm, ReadRotateImm]>;
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@ -471,11 +471,13 @@ def BDECOMPRESS : ALU_rr<0b0100100, 0b110, "bdecompress">, Sched<[]>;
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def BCOMPRESS : ALU_rr<0b0000100, 0b110, "bcompress">, Sched<[]>;
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} // Predicates = [HasStdExtZbe]
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let Predicates = [HasStdExtZbp] in {
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let Predicates = [HasStdExtZbpOrZbkb] in {
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def PACK : ALU_rr<0b0000100, 0b100, "pack">, Sched<[]>;
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def PACKU : ALU_rr<0b0100100, 0b100, "packu">, Sched<[]>;
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def PACKH : ALU_rr<0b0000100, 0b111, "packh">, Sched<[]>;
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} // Predicates = [HasStdExtZbp]
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} // Predicates = [HasStdExtZbpOrZbkb]
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let Predicates = [HasStdExtZbp] in
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def PACKU : ALU_rr<0b0100100, 0b100, "packu">, Sched<[]>;
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let Predicates = [HasStdExtZbm, IsRV64] in {
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def BMATOR : ALU_rr<0b0000100, 0b011, "bmator">, Sched<[]>;
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@ -504,7 +506,7 @@ def SH3ADDUW : ALUW_rr<0b0010000, 0b110, "sh3add.uw">,
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Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
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} // Predicates = [HasStdExtZbb, IsRV64]
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let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
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let Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64] in {
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def ROLW : ALUW_rr<0b0110000, 0b001, "rolw">,
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Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>;
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def RORW : ALUW_rr<0b0110000, 0b101, "rorw">,
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@ -520,7 +522,7 @@ let Predicates = [HasStdExtZbp, IsRV64] in {
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def XPERMW : ALU_rr<0b0010100, 0b000, "xperm.w">, Sched<[]>;
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} // Predicates = [HasStdExtZbp, IsRV64]
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let Predicates = [HasStdExtZbbOrZbp, IsRV64] in
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let Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64] in
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def RORIW : RVBShiftW_ri<0b0110000, 0b101, OPC_OP_IMM_32, "roriw">,
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Sched<[WriteRotateImm32, ReadRotateImm32]>;
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@ -559,10 +561,11 @@ def BDECOMPRESSW : ALUW_rr<0b0100100, 0b110, "bdecompressw">, Sched<[]>;
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def BCOMPRESSW : ALUW_rr<0b0000100, 0b110, "bcompressw">, Sched<[]>;
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} // Predicates = [HasStdExtZbe, IsRV64]
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let Predicates = [HasStdExtZbp, IsRV64] in {
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let Predicates = [HasStdExtZbpOrZbkb, IsRV64] in
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def PACKW : ALUW_rr<0b0000100, 0b100, "packw">, Sched<[]>;
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let Predicates = [HasStdExtZbp, IsRV64] in
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def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">, Sched<[]>;
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} // Predicates = [HasStdExtZbp, IsRV64]
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let Predicates = [HasStdExtZbf, IsRV64] in
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def BFPW : ALUW_rr<0b0100100, 0b111, "bfpw">,
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@ -593,21 +596,21 @@ def ZEXTH_RV64 : RVInstR<0b0000100, 0b100, OPC_OP_32, (outs GPR:$rd),
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// causes diagnostics to suggest that Zbp rather than Zbb is required for rev8
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// or gorci. Since Zbb is closer to being finalized than Zbp this will be
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// misleading to users.
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let Predicates = [HasStdExtZbbOrZbp, IsRV32] in {
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let Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV32] in {
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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def REV8_RV32 : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
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"rev8", "$rd, $rs1">, Sched<[WriteREV8, ReadREV8]> {
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let imm12 = { 0b01101, 0b0011000 };
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}
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} // Predicates = [HasStdExtZbbOrZbp, IsRV32]
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} // Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV32]
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let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
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let Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64] in {
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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def REV8_RV64 : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
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"rev8", "$rd, $rs1">, Sched<[WriteREV8, ReadREV8]> {
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let imm12 = { 0b01101, 0b0111000 };
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}
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} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
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} // Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64]
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let Predicates = [HasStdExtZbbOrZbp] in {
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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@ -617,6 +620,15 @@ def ORCB : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
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}
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} // Predicates = [HasStdExtZbbOrZbp]
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let Predicates = [HasStdExtZbpOrZbkb] in
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def BREV8 : RVBUnary<0b0110100, 0b00111, 0b101, OPC_OP_IMM, "brev8">;
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let Predicates = [HasStdExtZbpOrZbkb, IsRV32] in {
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def ZIP_RV32 : RVBUnary<0b0000100, 0b01111, 0b001, OPC_OP_IMM, "zip">;
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def UNZIP_RV32 : RVBUnary<0b0000100, 0b01111, 0b101, OPC_OP_IMM, "unzip">;
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} // Predicates = [HasStdExtZbkb, IsRV32]
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//===----------------------------------------------------------------------===//
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// Pseudo Instructions
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//===----------------------------------------------------------------------===//
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@ -631,11 +643,11 @@ def : InstAlias<"rev2.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00010)>;
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def : InstAlias<"rev.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00011)>;
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def : InstAlias<"rev4.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00100)>;
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def : InstAlias<"rev2.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00110)>;
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def : InstAlias<"rev.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00111)>;
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def : InstAlias<"rev8.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01000)>;
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def : InstAlias<"rev4.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01100)>;
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def : InstAlias<"rev2.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01110)>;
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def : InstAlias<"rev.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01111)>;
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def : InstAlias<"rev.b $rd, $rs", (BREV8 GPR:$rd, GPR:$rs)>;
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def : InstAlias<"zip.n $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0001)>;
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def : InstAlias<"unzip.n $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0001)>;
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@ -675,8 +687,6 @@ def : InstAlias<"zip4 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1100)>;
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def : InstAlias<"unzip4 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1100)>;
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def : InstAlias<"zip2 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1110)>;
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def : InstAlias<"unzip2 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1110)>;
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def : InstAlias<"zip $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1111)>;
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def : InstAlias<"unzip $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1111)>;
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def : InstAlias<"orc16 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b10000)>;
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def : InstAlias<"orc8 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11000)>;
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@ -17,7 +17,7 @@ def RocketModel : SchedMachineModel {
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let LoadLatency = 3;
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let MispredictPenalty = 3;
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let CompleteModel = false;
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let UnsupportedFeatures = [HasVInstructions, HasVInstructionsI64];
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let UnsupportedFeatures = [HasStdExtZbkb, HasVInstructions, HasVInstructionsI64];
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}
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//===----------------------------------------------------------------------===//
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@ -15,7 +15,7 @@ def SiFive7Model : SchedMachineModel {
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let LoadLatency = 3;
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let MispredictPenalty = 3;
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let CompleteModel = 0;
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let UnsupportedFeatures = [HasVInstructions];
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let UnsupportedFeatures = [HasStdExtZbkb, HasVInstructions];
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}
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// The SiFive7 microarchitecture has two pipelines: A and B.
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@ -83,6 +83,7 @@ private:
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bool HasStdExtZve64d = false;
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bool HasStdExtZfhmin = false;
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bool HasStdExtZfh = false;
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bool HasStdExtZbkb = false;
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bool HasRV64 = false;
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bool IsRV32E = false;
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bool EnableLinkerRelax = false;
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@ -156,6 +157,7 @@ public:
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bool hasStdExtZvl() const { return ZvlLen != ExtZvl::NotSet; }
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bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
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bool hasStdExtZfh() const { return HasStdExtZfh; }
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bool hasStdExtZbkb() const { return HasStdExtZbkb; }
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bool is64Bit() const { return HasRV64; }
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bool isRV32E() const { return IsRV32E; }
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bool enableLinkerRelax() const { return EnableLinkerRelax; }
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@ -19,6 +19,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-v %s -o - | FileCheck --check-prefix=RV32V %s
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; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zfh,+experimental-v,+f %s -o - | FileCheck --check-prefix=RV32COMBINED %s
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; RUN: llc -mtriple=riscv32 -mattr=+zbkb %s -o - | FileCheck --check-prefix=RV32ZBKB %s
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; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
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; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
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; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
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@ -38,6 +39,7 @@
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-v %s -o - | FileCheck --check-prefix=RV64V %s
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; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zfh,+experimental-v,+f %s -o - | FileCheck --check-prefix=RV64COMBINED %s
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; RUN: llc -mtriple=riscv64 -mattr=+zbkb %s -o - | FileCheck --check-prefix=RV64ZBKB %s
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; RV32M: .attribute 5, "rv32i2p0_m2p0"
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@ -59,6 +61,7 @@
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; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
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; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
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; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
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; RV32ZBKB: .attribute 5, "rv32i2p0_zbkb1p0"
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; RV64M: .attribute 5, "rv64i2p0_m2p0"
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; RV64A: .attribute 5, "rv64i2p0_a2p0"
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@ -79,6 +82,7 @@
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; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
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; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
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; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
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; RV64ZBKB: .attribute 5, "rv64i2p0_zbkb1p0"
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define i32 @addi(i32 %a) {
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%1 = add i32 %a, 1
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@ -1491,7 +1491,7 @@ define i32 @grev7_i32(i32 %a) nounwind {
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;
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; RV32ZBP-LABEL: grev7_i32:
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; RV32ZBP: # %bb.0:
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; RV32ZBP-NEXT: rev.b a0, a0
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; RV32ZBP-NEXT: grevi a0, a0, 7
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; RV32ZBP-NEXT: ret
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%and1 = shl i32 %a, 1
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%shl1 = and i32 %and1, -1431655766
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@ -1560,8 +1560,8 @@ define i64 @grev7_i64(i64 %a) nounwind {
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;
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; RV32ZBP-LABEL: grev7_i64:
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; RV32ZBP: # %bb.0:
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; RV32ZBP-NEXT: rev.b a0, a0
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; RV32ZBP-NEXT: rev.b a1, a1
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; RV32ZBP-NEXT: grevi a0, a0, 7
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; RV32ZBP-NEXT: grevi a1, a1, 7
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; RV32ZBP-NEXT: ret
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%and1 = shl i64 %a, 1
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%shl1 = and i64 %and1, -6148914691236517206
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@ -2175,7 +2175,7 @@ define zeroext i8 @bitreverse_i8(i8 zeroext %a) nounwind {
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|||
;
|
||||
; RV32ZBP-LABEL: bitreverse_i8:
|
||||
; RV32ZBP: # %bb.0:
|
||||
; RV32ZBP-NEXT: rev.b a0, a0
|
||||
; RV32ZBP-NEXT: grevi a0, a0, 7
|
||||
; RV32ZBP-NEXT: ret
|
||||
%1 = tail call i8 @llvm.bitreverse.i8(i8 %a)
|
||||
ret i8 %1
|
||||
|
|
@ -2450,7 +2450,7 @@ define i32 @bitreverse_bswap_i32(i32 %a) {
|
|||
;
|
||||
; RV32ZBP-LABEL: bitreverse_bswap_i32:
|
||||
; RV32ZBP: # %bb.0:
|
||||
; RV32ZBP-NEXT: rev.b a0, a0
|
||||
; RV32ZBP-NEXT: grevi a0, a0, 7
|
||||
; RV32ZBP-NEXT: ret
|
||||
%1 = call i32 @llvm.bitreverse.i32(i32 %a)
|
||||
%2 = call i32 @llvm.bswap.i32(i32 %1)
|
||||
|
|
@ -2539,8 +2539,8 @@ define i64 @bitreverse_bswap_i64(i64 %a) {
|
|||
;
|
||||
; RV32ZBP-LABEL: bitreverse_bswap_i64:
|
||||
; RV32ZBP: # %bb.0:
|
||||
; RV32ZBP-NEXT: rev.b a0, a0
|
||||
; RV32ZBP-NEXT: rev.b a1, a1
|
||||
; RV32ZBP-NEXT: grevi a0, a0, 7
|
||||
; RV32ZBP-NEXT: grevi a1, a1, 7
|
||||
; RV32ZBP-NEXT: ret
|
||||
%1 = call i64 @llvm.bitreverse.i64(i64 %a)
|
||||
%2 = call i64 @llvm.bswap.i64(i64 %1)
|
||||
|
|
|
|||
|
|
@ -1438,7 +1438,7 @@ define i64 @grev7_i64(i64 %a) nounwind {
|
|||
;
|
||||
; RV64ZBP-LABEL: grev7_i64:
|
||||
; RV64ZBP: # %bb.0:
|
||||
; RV64ZBP-NEXT: rev.b a0, a0
|
||||
; RV64ZBP-NEXT: grevi a0, a0, 7
|
||||
; RV64ZBP-NEXT: ret
|
||||
%and1 = shl i64 %a, 1
|
||||
%shl1 = and i64 %and1, -6148914691236517206
|
||||
|
|
@ -2481,7 +2481,7 @@ define i64 @bitreverse_bswap_i64(i64 %a) {
|
|||
;
|
||||
; RV64ZBP-LABEL: bitreverse_bswap_i64:
|
||||
; RV64ZBP: # %bb.0:
|
||||
; RV64ZBP-NEXT: rev.b a0, a0
|
||||
; RV64ZBP-NEXT: grevi a0, a0, 7
|
||||
; RV64ZBP-NEXT: ret
|
||||
%1 = call i64 @llvm.bitreverse.i64(i64 %a)
|
||||
%2 = call i64 @llvm.bswap.i64(i64 %1)
|
||||
|
|
|
|||
|
|
@ -127,3 +127,6 @@
|
|||
|
||||
.attribute arch, "rv32ifd_zve64d0p10"
|
||||
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl32b0p10_zvl64b0p10"
|
||||
|
||||
.attribute arch, "rv32i_zbkb1p0"
|
||||
# CHECK: attribute 5, "rv32i2p0_zbkb1p0"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,16 @@
|
|||
# RUN: llvm-mc %s -triple=riscv32 -mattr=+zbkb -show-encoding \
|
||||
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
|
||||
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zbkb < %s \
|
||||
# RUN: | llvm-objdump --mattr=+zbkb -d -r - \
|
||||
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
|
||||
|
||||
# CHECK-ASM-AND-OBJ: rev8 t0, t1
|
||||
# CHECK-ASM: encoding: [0x93,0x52,0x83,0x69]
|
||||
rev8 t0, t1
|
||||
|
||||
# CHECK-ASM-AND-OBJ: zip t0, t1
|
||||
# CHECK-ASM: encoding: [0x93,0x12,0xf3,0x08]
|
||||
zip t0, t1
|
||||
# CHECK-S-OBJ-NOALIAS: unzip t0, t1
|
||||
# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x08]
|
||||
unzip t0, t1
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
# RUN: llvm-mc %s -triple=riscv32 -mattr=+zbkb -show-encoding \
|
||||
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
|
||||
# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbkb -show-encoding \
|
||||
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
|
||||
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zbkb < %s \
|
||||
# RUN: | llvm-objdump --mattr=+zbkb -d -r - \
|
||||
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
|
||||
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbkb < %s \
|
||||
# RUN: | llvm-objdump --mattr=+zbkb -d -r - \
|
||||
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
|
||||
|
||||
# CHECK-ASM-AND-OBJ: ror t0, t1, t2
|
||||
# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x60]
|
||||
ror t0, t1, t2
|
||||
# CHECK-ASM-AND-OBJ: rol t0, t1, t2
|
||||
# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x60]
|
||||
rol t0, t1, t2
|
||||
# CHECK-ASM-AND-OBJ: rori t0, t1, 31
|
||||
# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x61]
|
||||
rori t0, t1, 31
|
||||
# CHECK-ASM-AND-OBJ: rori t0, t1, 0
|
||||
# CHECK-ASM: encoding: [0x93,0x52,0x03,0x60]
|
||||
rori t0, t1, 0
|
||||
|
||||
# CHECK-ASM-AND-OBJ: andn t0, t1, t2
|
||||
# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x40]
|
||||
andn t0, t1, t2
|
||||
# CHECK-ASM-AND-OBJ: orn t0, t1, t2
|
||||
# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x40]
|
||||
orn t0, t1, t2
|
||||
# CHECK-ASM-AND-OBJ: xnor t0, t1, t2
|
||||
# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x40]
|
||||
xnor t0, t1, t2
|
||||
|
||||
# CHECK-ASM: pack t0, t1, zero
|
||||
# CHECK-OBJ: zext.h t0, t1
|
||||
# CHECK-ASM: encoding: [0xb3,0x42,0x03,0x08]
|
||||
pack t0, t1, x0
|
||||
# CHECK-ASM-AND-OBJ: packh t0, t1, t2
|
||||
# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x08]
|
||||
packh t0, t1, t2
|
||||
|
||||
# CHECK-ASM-AND-OBJ: brev8 t0, t1
|
||||
# CHECK-ASM: encoding: [0x93,0x52,0x73,0x68]
|
||||
brev8 t0, t1
|
||||
|
|
@ -39,7 +39,7 @@ rev4.b x5, x6
|
|||
# CHECK-S-OBJ: rev2.b t0, t1
|
||||
rev2.b x5, x6
|
||||
|
||||
# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 7
|
||||
# CHECK-S-OBJ-NOALIAS: brev8 t0, t1
|
||||
# CHECK-S-OBJ: rev.b t0, t1
|
||||
rev.b x5, x6
|
||||
|
||||
|
|
@ -151,14 +151,6 @@ zip2 x5, x6
|
|||
# CHECK-S-OBJ: unzip2 t0, t1
|
||||
unzip2 x5, x6
|
||||
|
||||
# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 15
|
||||
# CHECK-S-OBJ: zip t0, t1
|
||||
zip x5, x6
|
||||
|
||||
# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 15
|
||||
# CHECK-S-OBJ: unzip t0, t1
|
||||
unzip x5, x6
|
||||
|
||||
# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 1
|
||||
# CHECK-S-OBJ: orc.p t0, t1
|
||||
orc.p x5, x6
|
||||
|
|
|
|||
|
|
@ -13,3 +13,9 @@ pack t0, t1, x0
|
|||
# CHECK-OBJ: rev8 t0, t1
|
||||
# CHECK-ASM: encoding: [0x93,0x52,0x83,0x69]
|
||||
grevi t0, t1, 24
|
||||
# CHECK-ASM-AND-OBJ: zip t0, t1
|
||||
# CHECK-ASM: encoding: [0x93,0x12,0xf3,0x08]
|
||||
zip x5, x6
|
||||
# CHECK-ASM-AND-OBJ: unzip t0, t1
|
||||
# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x08]
|
||||
unzip x5, x6
|
||||
|
|
|
|||
|
|
@ -54,5 +54,5 @@ xperm.n t0, t1, t2
|
|||
# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x28]
|
||||
xperm.b t0, t1, t2
|
||||
# CHECK-ASM-AND-OBJ: xperm.h t0, t1, t2
|
||||
# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x28
|
||||
# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x28]
|
||||
xperm.h t0, t1, t2
|
||||
|
|
|
|||
|
|
@ -0,0 +1,20 @@
|
|||
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbkb < %s \
|
||||
# RUN: | llvm-objdump --mattr=+zbkb -d -r - \
|
||||
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
|
||||
|
||||
# CHECK-ASM-AND-OBJ: rorw t0, t1, t2
|
||||
# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x60]
|
||||
rorw t0, t1, t2
|
||||
# CHECK-ASM-AND-OBJ: rolw t0, t1, t2
|
||||
# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x60]
|
||||
rolw t0, t1, t2
|
||||
# CHECK-ASM-AND-OBJ: roriw t0, t1, 31
|
||||
# CHECK-ASM: encoding: [0x9b,0x52,0xf3,0x61]
|
||||
roriw t0, t1, 31
|
||||
# CHECK-ASM-AND-OBJ: roriw t0, t1, 0
|
||||
# CHECK-ASM: encoding: [0x9b,0x52,0x03,0x60]
|
||||
roriw t0, t1, 0
|
||||
|
||||
# CHECK-ASM-AND-OBJ: packw t0, t1, t2
|
||||
# CHECK-ASM: encoding: [0xbb,0x42,0x73,0x08]
|
||||
packw t0, t1, t2
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbkb -show-encoding \
|
||||
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
|
||||
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbkb < %s \
|
||||
# RUN: | llvm-objdump --mattr=+zbkb -d -r - \
|
||||
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
|
||||
|
||||
# CHECK-ASM-AND-OBJ: rev8 t0, t1
|
||||
# CHECK-ASM: encoding: [0x93,0x52,0x83,0x6b]
|
||||
rev8 t0, t1
|
||||
|
|
@ -39,7 +39,7 @@ rev4.b x5, x6
|
|||
# CHECK-S-OBJ: rev2.b t0, t1
|
||||
rev2.b x5, x6
|
||||
|
||||
# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 7
|
||||
# CHECK-S-OBJ-NOALIAS: brev8 t0, t1
|
||||
# CHECK-S-OBJ: rev.b t0, t1
|
||||
rev.b x5, x6
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue