forked from OSchip/llvm-project
McARM: Always keep an offset expression, if used (instead of assuming == 0 if used but not present), and simplify logic.
Also, clean up various non-sensicalisms in isMemModeRegThumb() and isMemModeImmThumb(). llvm-svn: 123738
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@ -234,9 +234,6 @@ public:
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Mem.Writeback || Mem.Negative)
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Mem.Writeback || Mem.Negative)
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return false;
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return false;
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// If there is an offset expression, make sure it's valid.
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if (!Mem.Offset) return true;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
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if (!CE) return false;
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if (!CE) return false;
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@ -245,16 +242,14 @@ public:
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return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
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return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
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}
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}
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bool isMemModeRegThumb() const {
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bool isMemModeRegThumb() const {
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if (!isMemory() || (!Mem.OffsetIsReg && !Mem.Offset) || Mem.Writeback)
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if (!isMemory() || !Mem.OffsetIsReg || Mem.Writeback)
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return false;
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return false;
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return !Mem.Offset || !isa<MCConstantExpr>(Mem.Offset);
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return true;
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}
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}
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bool isMemModeImmThumb() const {
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bool isMemModeImmThumb() const {
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if (!isMemory() || (!Mem.OffsetIsReg && !Mem.Offset) || Mem.Writeback)
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if (!isMemory() || Mem.OffsetIsReg || Mem.Writeback)
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return false;
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return false;
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if (!Mem.Offset) return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
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if (!CE) return false;
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if (!CE) return false;
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@ -319,7 +314,6 @@ public:
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// FIXME: #-0 is encoded differently than #0. Does the parser preserve
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// FIXME: #-0 is encoded differently than #0. Does the parser preserve
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// the difference?
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// the difference?
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if (Mem.Offset) {
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
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assert(CE && "Non-constant mode 5 offset operand!");
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assert(CE && "Non-constant mode 5 offset operand!");
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@ -332,9 +326,6 @@ public:
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else
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else
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Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
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Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
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-Offset)));
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-Offset)));
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} else {
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Inst.addOperand(MCOperand::CreateImm(0));
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}
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}
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}
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void addMemModeRegThumbOperands(MCInst &Inst, unsigned N) const {
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void addMemModeRegThumbOperands(MCInst &Inst, unsigned N) const {
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@ -424,6 +415,8 @@ public:
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"OffsetRegNum must imply OffsetIsReg!");
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"OffsetRegNum must imply OffsetIsReg!");
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assert((!OffsetRegShifted || OffsetIsReg) &&
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assert((!OffsetRegShifted || OffsetIsReg) &&
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"OffsetRegShifted must imply OffsetIsReg!");
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"OffsetRegShifted must imply OffsetIsReg!");
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assert((Offset || OffsetIsReg) &&
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"Offset must exists unless register offset is used!");
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assert((!ShiftAmount || (OffsetIsReg && OffsetRegShifted)) &&
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assert((!ShiftAmount || (OffsetIsReg && OffsetRegShifted)) &&
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"Cannot have shift amount without shifted register offset!");
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"Cannot have shift amount without shifted register offset!");
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assert((!Offset || !OffsetIsReg) &&
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assert((!Offset || !OffsetIsReg) &&
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@ -755,6 +748,12 @@ ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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Parser.Lex(); // Eat exclaim token
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Parser.Lex(); // Eat exclaim token
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}
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}
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// Force Offset to exist if used.
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if (!OffsetIsReg) {
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if (!Offset)
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Offset = MCConstantExpr::Create(0, getContext());
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}
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Operands.push_back(ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset,
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Operands.push_back(ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset,
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OffsetRegNum, OffsetRegShifted,
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OffsetRegNum, OffsetRegShifted,
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ShiftType, ShiftAmount, Preindexed,
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ShiftType, ShiftAmount, Preindexed,
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@ -797,6 +796,12 @@ ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return true;
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return true;
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}
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}
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// Force Offset to exist if used.
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if (!OffsetIsReg) {
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if (!Offset)
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Offset = MCConstantExpr::Create(0, getContext());
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}
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Operands.push_back(ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset,
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Operands.push_back(ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset,
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OffsetRegNum, OffsetRegShifted,
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OffsetRegNum, OffsetRegShifted,
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ShiftType, ShiftAmount, Preindexed,
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ShiftType, ShiftAmount, Preindexed,
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