forked from OSchip/llvm-project
[AArch64][AsmParser] NFC: Parser.Lex() -> Lex()
Reviewed By: tmatheson Differential Revision: https://reviews.llvm.org/D107146
This commit is contained in:
Cullen Rhodes
parent
307b1fddd4
commit
7ed0120d84
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@ -2672,7 +2672,6 @@ unsigned AArch64AsmParser::matchRegisterNameAlias(StringRef Name,
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/// the register is added to the operand list.
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OperandMatchResultTy
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AArch64AsmParser::tryParseScalarRegister(unsigned &RegNum) {
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MCAsmParser &Parser = getParser();
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const AsmToken &Tok = getTok();
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if (Tok.isNot(AsmToken::Identifier))
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return MatchOperand_NoMatch;
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@ -2683,14 +2682,13 @@ AArch64AsmParser::tryParseScalarRegister(unsigned &RegNum) {
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return MatchOperand_NoMatch;
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RegNum = Reg;
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Parser.Lex(); // Eat identifier token.
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Lex(); // Eat identifier token.
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return MatchOperand_Success;
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}
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/// tryParseSysCROperand - Try to parse a system instruction CR operand name.
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OperandMatchResultTy
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AArch64AsmParser::tryParseSysCROperand(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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SMLoc S = getLoc();
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if (getTok().isNot(AsmToken::Identifier)) {
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@ -2711,7 +2709,7 @@ AArch64AsmParser::tryParseSysCROperand(OperandVector &Operands) {
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return MatchOperand_ParseFail;
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}
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Parser.Lex(); // Eat identifier token.
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Lex(); // Eat identifier token.
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Operands.push_back(
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AArch64Operand::CreateSysCR(CRNum, S, getLoc(), getContext()));
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return MatchOperand_Success;
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@ -2721,7 +2719,6 @@ AArch64AsmParser::tryParseSysCROperand(OperandVector &Operands) {
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template <bool IsSVEPrefetch>
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OperandMatchResultTy
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AArch64AsmParser::tryParsePrefetch(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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SMLoc S = getLoc();
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const AsmToken &Tok = getTok();
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@ -2783,14 +2780,13 @@ AArch64AsmParser::tryParsePrefetch(OperandVector &Operands) {
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Operands.push_back(AArch64Operand::CreatePrefetch(
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*PRFM, Tok.getString(), S, getContext()));
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Parser.Lex(); // Eat identifier token.
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Lex(); // Eat identifier token.
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return MatchOperand_Success;
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}
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/// tryParsePSBHint - Try to parse a PSB operand, mapped to Hint command
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OperandMatchResultTy
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AArch64AsmParser::tryParsePSBHint(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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SMLoc S = getLoc();
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const AsmToken &Tok = getTok();
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if (Tok.isNot(AsmToken::Identifier)) {
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@ -2806,14 +2802,13 @@ AArch64AsmParser::tryParsePSBHint(OperandVector &Operands) {
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Operands.push_back(AArch64Operand::CreatePSBHint(
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PSB->Encoding, Tok.getString(), S, getContext()));
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Parser.Lex(); // Eat identifier token.
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Lex(); // Eat identifier token.
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return MatchOperand_Success;
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}
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/// tryParseBTIHint - Try to parse a BTI operand, mapped to Hint command
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OperandMatchResultTy
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AArch64AsmParser::tryParseBTIHint(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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SMLoc S = getLoc();
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const AsmToken &Tok = getTok();
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if (Tok.isNot(AsmToken::Identifier)) {
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@ -2829,7 +2824,7 @@ AArch64AsmParser::tryParseBTIHint(OperandVector &Operands) {
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Operands.push_back(AArch64Operand::CreateBTIHint(
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BTI->Encoding, Tok.getString(), S, getContext()));
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Parser.Lex(); // Eat identifier token.
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Lex(); // Eat identifier token.
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return MatchOperand_Success;
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}
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@ -2837,12 +2832,11 @@ AArch64AsmParser::tryParseBTIHint(OperandVector &Operands) {
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/// instruction.
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OperandMatchResultTy
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AArch64AsmParser::tryParseAdrpLabel(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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SMLoc S = getLoc();
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const MCExpr *Expr = nullptr;
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if (getTok().is(AsmToken::Hash)) {
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Parser.Lex(); // Eat hash token.
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Lex(); // Eat hash token.
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}
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if (parseSymbolicImmVal(Expr))
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@ -2898,7 +2892,7 @@ AArch64AsmParser::tryParseAdrLabel(OperandVector &Operands) {
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return MatchOperand_NoMatch;
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if (getTok().is(AsmToken::Hash))
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getParser().Lex(); // Eat hash token.
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Lex(); // Eat hash token.
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if (parseSymbolicImmVal(Expr))
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return MatchOperand_ParseFail;
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@ -2927,7 +2921,6 @@ AArch64AsmParser::tryParseAdrLabel(OperandVector &Operands) {
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template<bool AddFPZeroAsLiteral>
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OperandMatchResultTy
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AArch64AsmParser::tryParseFPImm(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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SMLoc S = getLoc();
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bool Hash = parseOptionalToken(AsmToken::Hash);
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@ -2974,7 +2967,7 @@ AArch64AsmParser::tryParseFPImm(OperandVector &Operands) {
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RealVal, *StatusOrErr == APFloat::opOK, S, getContext()));
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}
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Parser.Lex(); // Eat the token.
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Lex(); // Eat the token.
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return MatchOperand_Success;
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}
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@ -2983,11 +2976,10 @@ AArch64AsmParser::tryParseFPImm(OperandVector &Operands) {
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/// a shift suffix, for example '#1, lsl #12'.
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OperandMatchResultTy
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AArch64AsmParser::tryParseImmWithOptionalShift(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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SMLoc S = getLoc();
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if (getTok().is(AsmToken::Hash))
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Parser.Lex(); // Eat '#'
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Lex(); // Eat '#'
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else if (getTok().isNot(AsmToken::Integer))
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// Operand should start from # or should be integer, emit error otherwise.
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return MatchOperand_NoMatch;
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@ -3002,7 +2994,7 @@ AArch64AsmParser::tryParseImmWithOptionalShift(OperandVector &Operands) {
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}
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// Eat ','
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Parser.Lex();
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Lex();
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// The optional operand must be "lsl #N" where N is non-negative.
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if (!getTok().is(AsmToken::Identifier) ||
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@ -3012,7 +3004,7 @@ AArch64AsmParser::tryParseImmWithOptionalShift(OperandVector &Operands) {
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}
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// Eat 'lsl'
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Parser.Lex();
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Lex();
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parseOptionalToken(AsmToken::Hash);
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@ -3027,7 +3019,7 @@ AArch64AsmParser::tryParseImmWithOptionalShift(OperandVector &Operands) {
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Error(getLoc(), "positive shift amount required");
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return MatchOperand_ParseFail;
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}
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Parser.Lex(); // Eat the number
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Lex(); // Eat the number
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// Just in case the optional lsl #0 is used for immediates other than zero.
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if (ShiftAmount == 0 && Imm != nullptr) {
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@ -3085,7 +3077,6 @@ AArch64CC::CondCode AArch64AsmParser::parseCondCodeString(StringRef Cond) {
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/// parseCondCode - Parse a Condition Code operand.
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bool AArch64AsmParser::parseCondCode(OperandVector &Operands,
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bool invertCondCode) {
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MCAsmParser &Parser = getParser();
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SMLoc S = getLoc();
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const AsmToken &Tok = getTok();
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assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
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@ -3094,7 +3085,7 @@ bool AArch64AsmParser::parseCondCode(OperandVector &Operands,
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AArch64CC::CondCode CC = parseCondCodeString(Cond);
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if (CC == AArch64CC::Invalid)
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return TokError("invalid condition code");
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Parser.Lex(); // Eat identifier token.
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Lex(); // Eat identifier token.
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if (invertCondCode) {
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if (CC == AArch64CC::AL || CC == AArch64CC::NV)
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@ -3109,7 +3100,6 @@ bool AArch64AsmParser::parseCondCode(OperandVector &Operands,
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OperandMatchResultTy
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AArch64AsmParser::tryParseSVCR(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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const AsmToken &Tok = getTok();
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SMLoc S = getLoc();
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@ -3125,20 +3115,19 @@ AArch64AsmParser::tryParseSVCR(OperandVector &Operands) {
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Operands.push_back(
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AArch64Operand::CreateSVCR(PStateImm, Tok.getString(), S, getContext()));
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Parser.Lex(); // Eat identifier token.
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Lex(); // Eat identifier token.
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return MatchOperand_Success;
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}
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OperandMatchResultTy
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AArch64AsmParser::tryParseMatrixRegister(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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const AsmToken &Tok = getTok();
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SMLoc S = getLoc();
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StringRef Name = Tok.getString();
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if (Name.equals_insensitive("za")) {
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Parser.Lex(); // eat "za"
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Lex(); // eat "za"
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Operands.push_back(AArch64Operand::CreateMatrixRegister(
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AArch64::ZA, /*ElementWidth=*/0, MatrixKind::Array, S, getLoc(),
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getContext()));
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@ -3176,7 +3165,7 @@ AArch64AsmParser::tryParseMatrixRegister(OperandVector &Operands) {
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}
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unsigned ElementWidth = KindRes->second;
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Parser.Lex();
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Lex();
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Operands.push_back(AArch64Operand::CreateMatrixRegister(
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Reg, ElementWidth, Kind, S, getLoc(), getContext()));
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@ -3194,7 +3183,6 @@ AArch64AsmParser::tryParseMatrixRegister(OperandVector &Operands) {
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/// them if present.
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OperandMatchResultTy
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AArch64AsmParser::tryParseOptionalShiftExtend(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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const AsmToken &Tok = getTok();
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std::string LowerID = Tok.getString().lower();
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AArch64_AM::ShiftExtendType ShOp =
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@ -3218,7 +3206,7 @@ AArch64AsmParser::tryParseOptionalShiftExtend(OperandVector &Operands) {
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return MatchOperand_NoMatch;
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SMLoc S = Tok.getLoc();
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Parser.Lex();
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Lex();
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bool Hash = parseOptionalToken(AsmToken::Hash);
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@ -3363,7 +3351,6 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
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Mnemonic = Name;
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Operands.push_back(AArch64Operand::CreateToken("sys", NameLoc, getContext()));
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MCAsmParser &Parser = getParser();
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const AsmToken &Tok = getTok();
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StringRef Op = Tok.getString();
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SMLoc S = Tok.getLoc();
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@ -3427,7 +3414,7 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
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createSysAlias(PRCTX->Encoding << 3 | PRCTX_Op2 , Operands, S);
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}
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Parser.Lex(); // Eat operand.
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Lex(); // Eat operand.
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bool ExpectRegister = (Op.lower().find("all") == StringRef::npos);
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bool HasRegister = false;
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@ -3518,14 +3505,13 @@ AArch64AsmParser::tryParseBarrierOperand(OperandVector &Operands) {
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Operands.push_back(AArch64Operand::CreateBarrier(
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DB ? DB->Encoding : TSB->Encoding, Tok.getString(), getLoc(),
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getContext(), false /*hasnXSModifier*/));
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Parser.Lex(); // Consume the option
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Lex(); // Consume the option
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return MatchOperand_Success;
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}
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OperandMatchResultTy
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AArch64AsmParser::tryParseBarriernXSOperand(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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const AsmToken &Tok = getTok();
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assert(Mnemonic == "dsb" && "Instruction does not accept nXS operands");
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@ -3573,14 +3559,13 @@ AArch64AsmParser::tryParseBarriernXSOperand(OperandVector &Operands) {
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Operands.push_back(
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AArch64Operand::CreateBarrier(DB->Encoding, Tok.getString(), getLoc(),
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getContext(), true /*hasnXSModifier*/));
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Parser.Lex(); // Consume the option
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Lex(); // Consume the option
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return MatchOperand_Success;
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}
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OperandMatchResultTy
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AArch64AsmParser::tryParseSysReg(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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const AsmToken &Tok = getTok();
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if (Tok.isNot(AsmToken::Identifier))
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@ -3605,7 +3590,7 @@ AArch64AsmParser::tryParseSysReg(OperandVector &Operands) {
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Operands.push_back(
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AArch64Operand::CreateSysReg(Tok.getString(), getLoc(), MRSReg, MSRReg,
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PStateImm, getContext()));
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Parser.Lex(); // Eat identifier
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Lex(); // Eat identifier
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return MatchOperand_Success;
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}
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@ -3673,7 +3658,6 @@ AArch64AsmParser::tryParseVectorIndex(OperandVector &Operands) {
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OperandMatchResultTy
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AArch64AsmParser::tryParseVectorRegister(unsigned &Reg, StringRef &Kind,
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RegKind MatchKind) {
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MCAsmParser &Parser = getParser();
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const AsmToken &Tok = getTok();
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if (Tok.isNot(AsmToken::Identifier))
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@ -3694,7 +3678,7 @@ AArch64AsmParser::tryParseVectorRegister(unsigned &Reg, StringRef &Kind,
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return MatchOperand_ParseFail;
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}
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}
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Parser.Lex(); // Eat the register token.
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Lex(); // Eat the register token.
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Reg = RegNum;
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return MatchOperand_Success;
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@ -3731,7 +3715,6 @@ AArch64AsmParser::tryParseSVEPredicateVector(OperandVector &Operands) {
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}
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// Not all predicates are followed by a '/m' or '/z'.
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MCAsmParser &Parser = getParser();
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if (getTok().isNot(AsmToken::Slash))
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return MatchOperand_Success;
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@ -3744,7 +3727,7 @@ AArch64AsmParser::tryParseSVEPredicateVector(OperandVector &Operands) {
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// Add a literal slash as operand
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Operands.push_back(AArch64Operand::CreateToken("/", getLoc(), getContext()));
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Parser.Lex(); // Eat the slash.
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Lex(); // Eat the slash.
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// Zeroing or merging?
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auto Pred = getTok().getString().lower();
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@ -3757,7 +3740,7 @@ AArch64AsmParser::tryParseSVEPredicateVector(OperandVector &Operands) {
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const char *ZM = Pred == "z" ? "z" : "m";
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Operands.push_back(AArch64Operand::CreateToken(ZM, getLoc(), getContext()));
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Parser.Lex(); // Eat zero/merge token.
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Lex(); // Eat zero/merge token.
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return MatchOperand_Success;
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}
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@ -3775,7 +3758,6 @@ bool AArch64AsmParser::parseRegister(OperandVector &Operands) {
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}
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bool AArch64AsmParser::parseSymbolicImmVal(const MCExpr *&ImmVal) {
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MCAsmParser &Parser = getParser();
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bool HasELFModifier = false;
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AArch64MCExpr::VariantKind RefKind;
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@ -3838,7 +3820,7 @@ bool AArch64AsmParser::parseSymbolicImmVal(const MCExpr *&ImmVal) {
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if (RefKind == AArch64MCExpr::VK_INVALID)
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return TokError("expect relocation specifier in operand after ':'");
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Parser.Lex(); // Eat identifier
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Lex(); // Eat identifier
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if (parseToken(AsmToken::Colon, "expect ':' after relocation specifier"))
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return true;
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@ -3999,7 +3981,7 @@ AArch64AsmParser::tryParseVectorList(OperandVector &Operands,
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SMLoc S = getLoc();
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auto LCurly = getTok();
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Parser.Lex(); // Eat left bracket token.
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Lex(); // Eat left bracket token.
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StringRef Kind;
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unsigned FirstReg;
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@ -4150,7 +4132,7 @@ AArch64AsmParser::tryParseGPROperand(OperandVector &Operands) {
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}
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// Eat the comma
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getParser().Lex();
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Lex();
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// Match the shift
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SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> ExtOpnd;
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@ -4182,17 +4164,17 @@ bool AArch64AsmParser::parseOptionalMulOperand(OperandVector &Operands) {
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Operands.push_back(
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AArch64Operand::CreateToken("mul", getLoc(), getContext()));
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Parser.Lex(); // Eat the "mul"
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Lex(); // Eat the "mul"
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if (NextIsVL) {
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Operands.push_back(
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AArch64Operand::CreateToken("vl", getLoc(), getContext()));
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Parser.Lex(); // Eat the "vl"
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Lex(); // Eat the "vl"
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return false;
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}
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if (NextIsHash) {
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Parser.Lex(); // Eat the #
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Lex(); // Eat the #
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SMLoc S = getLoc();
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// Parse immediate operand.
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@ -4210,7 +4192,6 @@ bool AArch64AsmParser::parseOptionalMulOperand(OperandVector &Operands) {
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}
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bool AArch64AsmParser::parseKeywordOperand(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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auto Tok = getTok();
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if (Tok.isNot(AsmToken::Identifier))
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return true;
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@ -4223,7 +4204,7 @@ bool AArch64AsmParser::parseKeywordOperand(OperandVector &Operands) {
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Operands.push_back(
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AArch64Operand::CreateToken(Keyword, Tok.getLoc(), getContext()));
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Parser.Lex();
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Lex();
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return false;
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}
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@ -4262,7 +4243,7 @@ bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
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case AsmToken::LBrac: {
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||||
Operands.push_back(
|
||||
AArch64Operand::CreateToken("[", getLoc(), getContext()));
|
||||
Parser.Lex(); // Eat '['
|
||||
Lex(); // Eat '['
|
||||
|
||||
// There's no comma after a '[', so we can parse the next operand
|
||||
// immediately.
|
||||
|
|
@ -4274,7 +4255,7 @@ bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
|
|||
|
||||
Operands.push_back(
|
||||
AArch64Operand::CreateToken("{", getLoc(), getContext()));
|
||||
Parser.Lex(); // Eat '{'
|
||||
Lex(); // Eat '{'
|
||||
|
||||
// There's no comma after a '{', so we can parse the next operand
|
||||
// immediately.
|
||||
|
|
@ -4335,7 +4316,7 @@ bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
|
|||
// We need to consume this token only when we have a Real, otherwise
|
||||
// we let parseSymbolicImmVal take care of it
|
||||
if (Parser.getLexer().peekTok().is(AsmToken::Real))
|
||||
Parser.Lex();
|
||||
Lex();
|
||||
}
|
||||
|
||||
// The only Real that should come through here is a literal #0.0 for
|
||||
|
|
@ -4351,7 +4332,7 @@ bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
|
|||
return TokError("unexpected floating point literal");
|
||||
else if (IntVal != 0 || isNegative)
|
||||
return TokError("expected floating-point constant #0.0");
|
||||
Parser.Lex(); // Eat the token.
|
||||
Lex(); // Eat the token.
|
||||
|
||||
Operands.push_back(AArch64Operand::CreateToken("#0", S, getContext()));
|
||||
Operands.push_back(AArch64Operand::CreateToken(".0", S, getContext()));
|
||||
|
|
@ -4370,7 +4351,7 @@ bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
|
|||
SMLoc Loc = getLoc();
|
||||
if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
|
||||
return TokError("unexpected token in operand");
|
||||
Parser.Lex(); // Eat '='
|
||||
Lex(); // Eat '='
|
||||
const MCExpr *SubExprVal;
|
||||
if (getParser().parseExpression(SubExprVal))
|
||||
return true;
|
||||
|
|
@ -4432,7 +4413,7 @@ bool AArch64AsmParser::parseComma() {
|
|||
if (check(getTok().isNot(AsmToken::Comma), getLoc(), "expected comma"))
|
||||
return true;
|
||||
// Eat the comma
|
||||
getParser().Lex();
|
||||
Lex();
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -6261,8 +6242,7 @@ bool AArch64AsmParser::parseDirectiveLtorg(SMLoc L) {
|
|||
/// parseDirectiveReq
|
||||
/// ::= name .req registername
|
||||
bool AArch64AsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
|
||||
MCAsmParser &Parser = getParser();
|
||||
Parser.Lex(); // Eat the '.req' token.
|
||||
Lex(); // Eat the '.req' token.
|
||||
SMLoc SRegLoc = getLoc();
|
||||
RegKind RegisterKind = RegKind::Scalar;
|
||||
unsigned RegNum;
|
||||
|
|
@ -6325,11 +6305,10 @@ bool AArch64AsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
|
|||
/// parseDirectiveUneq
|
||||
/// ::= .unreq registername
|
||||
bool AArch64AsmParser::parseDirectiveUnreq(SMLoc L) {
|
||||
MCAsmParser &Parser = getParser();
|
||||
if (getTok().isNot(AsmToken::Identifier))
|
||||
return TokError("unexpected input in .unreq directive.");
|
||||
RegisterReqs.erase(getTok().getIdentifier().lower());
|
||||
Parser.Lex(); // Eat the identifier.
|
||||
Lex(); // Eat the identifier.
|
||||
return parseToken(AsmToken::EndOfStatement);
|
||||
}
|
||||
|
||||
|
|
@ -6353,8 +6332,6 @@ bool AArch64AsmParser::parseDirectiveCFIBKeyFrame() {
|
|||
/// parseDirectiveVariantPCS
|
||||
/// ::= .variant_pcs symbolname
|
||||
bool AArch64AsmParser::parseDirectiveVariantPCS(SMLoc L) {
|
||||
MCAsmParser &Parser = getParser();
|
||||
|
||||
const AsmToken &Tok = getTok();
|
||||
if (Tok.isNot(AsmToken::Identifier))
|
||||
return TokError("expected symbol name");
|
||||
|
|
@ -6365,7 +6342,7 @@ bool AArch64AsmParser::parseDirectiveVariantPCS(SMLoc L) {
|
|||
if (!Sym)
|
||||
return TokError("unknown symbol");
|
||||
|
||||
Parser.Lex(); // Eat the symbol
|
||||
Lex(); // Eat the symbol
|
||||
|
||||
if (parseEOL())
|
||||
return true;
|
||||
|
|
@ -6774,7 +6751,7 @@ AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
|
|||
return MatchOperand_ParseFail;
|
||||
}
|
||||
// Eat the comma
|
||||
getParser().Lex();
|
||||
Lex();
|
||||
|
||||
SMLoc E = getLoc();
|
||||
unsigned SecondReg;
|
||||
|
|
@ -6840,7 +6817,7 @@ AArch64AsmParser::tryParseSVEDataVector(OperandVector &Operands) {
|
|||
}
|
||||
|
||||
// Eat the comma
|
||||
getParser().Lex();
|
||||
Lex();
|
||||
|
||||
// Match the shift
|
||||
SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> ExtOpnd;
|
||||
|
|
@ -6870,7 +6847,7 @@ AArch64AsmParser::tryParseSVEPattern(OperandVector &Operands) {
|
|||
|
||||
int64_t Pattern;
|
||||
if (IsHash) {
|
||||
Parser.Lex(); // Eat hash
|
||||
Lex(); // Eat hash
|
||||
|
||||
// Parse the immediate operand.
|
||||
const MCExpr *ImmVal;
|
||||
|
|
@ -6889,7 +6866,7 @@ AArch64AsmParser::tryParseSVEPattern(OperandVector &Operands) {
|
|||
if (!Pat)
|
||||
return MatchOperand_NoMatch;
|
||||
|
||||
Parser.Lex();
|
||||
Lex();
|
||||
Pattern = Pat->Encoding;
|
||||
assert(Pattern >= 0 && Pattern < 32);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue