forked from OSchip/llvm-project
[Lanai] fix lowering wide returns
This implements LanaiTargetLowering::CanLowerReturn, thereby ensuring all return values conform to the RetCC and get sret-demoted as necessary. A regression test is also added that exercises this functionality. Reviewed By: jpienaar Differential Revision: https://reviews.llvm.org/D107086
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@ -530,6 +530,15 @@ SDValue LanaiTargetLowering::LowerCCCArguments(
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return Chain;
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}
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bool LanaiTargetLowering::CanLowerReturn(
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CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
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return CCInfo.CheckReturn(Outs, RetCC_Lanai32);
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}
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SDValue
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LanaiTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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bool IsVarArg,
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@ -90,6 +90,11 @@ public:
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SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const override;
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Register getRegisterByName(const char *RegName, LLT VT,
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const MachineFunction &MF) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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@ -0,0 +1,13 @@
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; RUN: llc -march=lanai < %s | FileCheck %s
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; Tests that lowering wide registers (128 bits or more) works on Lanai.
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; The emitted assembly is not checked, we just do a smoketest.
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target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
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target triple = "lanai"
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; CHECK-LABEL: add128:
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define i128 @add128(i128 %x, i128 %y) {
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%a = add i128 %x, %y
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ret i128 %a
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}
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