forked from OSchip/llvm-project
parent
5da1825ebc
commit
7ecc277ef9
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//===- HexagonDepArch.h ---------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//
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//
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// The LLVM Compiler Infrastructure
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// The LLVM Compiler Infrastructure
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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#ifndef HEXAGON_DEP_ARCH_H
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#ifndef HEXAGON_DEP_ARCH_H
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#define HEXAGON_DEP_ARCH_H
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#define HEXAGON_DEP_ARCH_H
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namespace llvm {
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namespace llvm {
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namespace Hexagon {
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namespace Hexagon {
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enum class ArchEnum { NoArch,Generic,V5,V55,V60,V62,V65 };
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enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65 };
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} // namespace Hexagon
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} // namespace Hexagon
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} // namespace llvm;
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} // namespace llvm;
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#endif // HEXAGON_DEP_ARCH_H
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#endif // HEXAGON_DEP_ARCH_H
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//===- HexagonDepMappings.td ----------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//
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//
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// The LLVM Compiler Infrastructure
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// The LLVM Compiler Infrastructure
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//
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//
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// Automatically generated file, please consult code owner before editing.
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// Automatically generated file, please consult code owner before editing.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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def A2_negAlias : InstAlias<"$Rd32 = neg($Rs32)", (A2_subri IntRegs:$Rd32, 0, IntRegs:$Rs32)>;
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def A2_negAlias : InstAlias<"$Rd32 = neg($Rs32)", (A2_subri IntRegs:$Rd32, 0, IntRegs:$Rs32)>;
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def A2_notAlias : InstAlias<"$Rd32 = not($Rs32)", (A2_subri IntRegs:$Rd32, -1, IntRegs:$Rs32)>;
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def A2_notAlias : InstAlias<"$Rd32 = not($Rs32)", (A2_subri IntRegs:$Rd32, -1, IntRegs:$Rs32)>;
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def A2_tfrfAlias : InstAlias<"if (!$Pu4) $Rd32 = $Rs32", (A2_paddif IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
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def A2_tfrfAlias : InstAlias<"if (!$Pu4) $Rd32 = $Rs32", (A2_paddif IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
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