forked from OSchip/llvm-project
[AArch64][GlobalISel] Legalize 32-bit + narrow G_SMULO + G_UMULO
SDAG lowers 32-bit and 64-bit G_SMULO + G_UMULO. We were missing the 32-bit case. For other sizes, make the 0th type a power of 2 and clamp it to either 32 bits or 64 bits. Right now, this will allow us to handle narrow types (e.g. s4, s24, etc.). The LegalizerHelper doesn't support narrowing G_SMULO or G_UMULO right now. I think we want clamping behaviour either way, so we might as well include it now to be explicit. Differential Revision: https://reviews.llvm.org/D108240
This commit is contained in:
Jessica Paquette
parent
16caf6321c
commit
7e91c59844
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@ -169,7 +169,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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getActionDefinitionsBuilder({G_SREM, G_UREM, G_SDIVREM, G_UDIVREM})
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.lowerFor({s1, s8, s16, s32, s64});
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getActionDefinitionsBuilder({G_SMULO, G_UMULO}).lowerFor({{s64, s1}});
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getActionDefinitionsBuilder({G_SMULO, G_UMULO})
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.widenScalarToNextPow2(0, /*Min = */ 32)
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.clampScalar(0, s32, s64)
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.lowerIf(typeIs(1, s1));
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getActionDefinitionsBuilder({G_SMULH, G_UMULH}).legalFor({s32, s64});
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@ -136,6 +136,19 @@ entry:
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ret void
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}
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %4:_(s128), %5:_(s1) = G_UMULO %0:_, %6:_ (in function: umul_s128)
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; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for umul_s128
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; FALLBACK-WITH-REPORT-OUT-LABEL: umul_s128
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declare {i128, i1} @llvm.umul.with.overflow.i128(i128, i128) nounwind readnone
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define zeroext i1 @umul_s128(i128 %v1, i128* %res) {
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entry:
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%t = call {i128, i1} @llvm.umul.with.overflow.i128(i128 %v1, i128 2)
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%val = extractvalue {i128, i1} %t, 0
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%obit = extractvalue {i128, i1} %t, 1
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store i128 %val, i128* %res
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ret i1 %obit
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}
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attributes #1 = { "target-features"="+sve" }
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attributes #2 = { "target-features"="+ls64" }
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@ -65,6 +65,93 @@ body: |
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%4:_(s32) = G_ANYEXT %3(s1)
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$w0 = COPY %4(s32)
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...
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---
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name: test_smul_overflow_s32
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body: |
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bb.0:
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; CHECK-LABEL: name: test_smul_overflow_s32
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; CHECK: %lhs:_(s32) = COPY $w0
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; CHECK: %rhs:_(s32) = COPY $w1
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; CHECK: [[SMULH:%[0-9]+]]:_(s32) = G_SMULH %lhs, %rhs
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; CHECK: %mul:_(s32) = G_MUL %lhs, %rhs
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
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; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR %mul, [[C]](s64)
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; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SMULH]](s32), [[ASHR]]
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; CHECK: $w0 = COPY %mul(s32)
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; CHECK: %ext_overflow:_(s32) = COPY [[ICMP]](s32)
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; CHECK: $w0 = COPY %ext_overflow(s32)
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; CHECK: RET_ReallyLR implicit $w0
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%lhs:_(s32) = COPY $w0
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%rhs:_(s32) = COPY $w1
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%mul:_(s32), %overflow:_(s1) = G_SMULO %lhs, %rhs
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$w0 = COPY %mul(s32)
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%ext_overflow:_(s32) = G_ANYEXT %overflow(s1)
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$w0 = COPY %ext_overflow(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: test_umul_overflow_s32
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body: |
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bb.0:
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; CHECK-LABEL: name: test_umul_overflow_s32
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; CHECK: %lhs:_(s32) = COPY $w0
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; CHECK: %rhs:_(s32) = COPY $w1
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; CHECK: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH %lhs, %rhs
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: %mul:_(s32) = G_MUL %lhs, %rhs
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; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]]
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; CHECK: $w0 = COPY %mul(s32)
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; CHECK: %ext_overflow:_(s32) = COPY [[ICMP]](s32)
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; CHECK: $w0 = COPY %ext_overflow(s32)
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; CHECK: RET_ReallyLR implicit $w0
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%lhs:_(s32) = COPY $w0
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%rhs:_(s32) = COPY $w1
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%mul:_(s32), %overflow:_(s1) = G_UMULO %lhs, %rhs
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$w0 = COPY %mul(s32)
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%ext_overflow:_(s32) = G_ANYEXT %overflow(s1)
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$w0 = COPY %ext_overflow(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: test_umul_overflow_s24
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body: |
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bb.0:
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; CHECK-LABEL: name: test_umul_overflow_s24
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; CHECK: %lhs_wide:_(s32) = COPY $w0
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; CHECK: %rhs_wide:_(s32) = COPY $w1
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %lhs_wide(s32)
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %rhs_wide(s32)
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; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; CHECK: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[AND1]]
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
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; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C1]]
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; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
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; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[MUL]](s32), [[AND2]]
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
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; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
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; CHECK: %ext_mul:_(s32) = COPY [[MUL]](s32)
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; CHECK: $w0 = COPY %ext_mul(s32)
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; CHECK: %ext_overflow:_(s32) = COPY [[OR]](s32)
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; CHECK: $w0 = COPY %ext_overflow(s32)
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; CHECK: RET_ReallyLR implicit $w0
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%lhs_wide:_(s32) = COPY $w0
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%rhs_wide:_(s32) = COPY $w1
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%lhs:_(s24) = G_TRUNC %lhs_wide
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%rhs:_(s24) = G_TRUNC %rhs_wide
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%mul:_(s24), %overflow:_(s1) = G_UMULO %lhs, %rhs
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%ext_mul:_(s32) = G_ANYEXT %mul
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$w0 = COPY %ext_mul(s32)
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%ext_overflow:_(s32) = G_ANYEXT %overflow(s1)
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$w0 = COPY %ext_overflow(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: vector_mul_scalarize
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@ -341,11 +341,11 @@
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# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
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# DEBUG-NEXT: G_UMULO (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
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# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
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# DEBUG-NEXT: .. the first uncovered type index: 2, OK
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# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
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# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: G_SMULO (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
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# DEBUG-NEXT: .. the first uncovered type index: 2, OK
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# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
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# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: G_UMULH (opcode {{[0-9]+}}): 1 type index, 0 imm indices
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# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
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# DEBUG-NEXT: .. the first uncovered type index: 1, OK
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