PowerPC: Don't lower SELECT_CC to PPCISD::FSEL on SPE

SPE doesn't have a fsel instruction, so don't try to lower to it.

This fixes a "Cannot select: tN: f64 = PPCISD::FSEL tX, tY, tZ" error.

Reviewed By: #powerpc, lkail
Differential Revision: https://reviews.llvm.org/D77773
This commit is contained in:
Justin Hibbits 2020-04-08 21:29:40 -05:00
parent 914dbf4808
commit 7e9153e940
2 changed files with 33 additions and 2 deletions

View File

@ -7797,9 +7797,9 @@ SDValue PPCTargetLowering::LowerTRUNCATEVector(SDValue Op,
/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
/// possible.
SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
// Not FP? Not a fsel.
// Not FP, or using SPE? Not a fsel.
if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
!Op.getOperand(2).getValueType().isFloatingPoint())
!Op.getOperand(2).getValueType().isFloatingPoint() || Subtarget.hasSPE())
return Op;
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();

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@ -0,0 +1,31 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
; RUN: -mattr=+spe | FileCheck %s
define void @no_fsel(i32 %e) #0 {
; CHECK-LABEL: no_fsel:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li 4, .LCPI0_0@l
; CHECK-NEXT: lis 5, .LCPI0_0@ha
; CHECK-NEXT: evlddx 4, 5, 4
; CHECK-NEXT: efdcfui 3, 3
; CHECK-NEXT: efdmul 5, 3, 3
; CHECK-NEXT: efdcmpeq 0, 5, 4
; CHECK-NEXT: ble 0, .LBB0_2
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: evor 3, 4, 4
; CHECK-NEXT: .LBB0_2: # %entry
; CHECK-NEXT: efdctsiz 3, 3
; CHECK-NEXT: sth 3, 0(3)
; CHECK-NEXT: blr
entry:
%conv = uitofp i32 %e to double
%mul = fmul double %conv, %conv
%tobool = fcmp une double %mul, 0.000000e+00
%cond = select i1 %tobool, double %conv, double 0.000000e+00
%conv3 = fptosi double %cond to i16
store i16 %conv3, i16* undef
ret void
}
attributes #0 = { "no-infs-fp-math"="true" "no-nans-fp-math"="true" }