forked from OSchip/llvm-project
PowerPC: Don't lower SELECT_CC to PPCISD::FSEL on SPE
SPE doesn't have a fsel instruction, so don't try to lower to it. This fixes a "Cannot select: tN: f64 = PPCISD::FSEL tX, tY, tZ" error. Reviewed By: #powerpc, lkail Differential Revision: https://reviews.llvm.org/D77773
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@ -7797,9 +7797,9 @@ SDValue PPCTargetLowering::LowerTRUNCATEVector(SDValue Op,
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/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
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/// possible.
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SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
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// Not FP? Not a fsel.
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// Not FP, or using SPE? Not a fsel.
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if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
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!Op.getOperand(2).getValueType().isFloatingPoint())
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!Op.getOperand(2).getValueType().isFloatingPoint() || Subtarget.hasSPE())
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return Op;
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
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@ -0,0 +1,31 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
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; RUN: -mattr=+spe | FileCheck %s
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define void @no_fsel(i32 %e) #0 {
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; CHECK-LABEL: no_fsel:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 4, .LCPI0_0@l
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; CHECK-NEXT: lis 5, .LCPI0_0@ha
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; CHECK-NEXT: evlddx 4, 5, 4
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; CHECK-NEXT: efdcfui 3, 3
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; CHECK-NEXT: efdmul 5, 3, 3
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; CHECK-NEXT: efdcmpeq 0, 5, 4
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; CHECK-NEXT: ble 0, .LBB0_2
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: evor 3, 4, 4
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; CHECK-NEXT: .LBB0_2: # %entry
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; CHECK-NEXT: efdctsiz 3, 3
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; CHECK-NEXT: sth 3, 0(3)
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; CHECK-NEXT: blr
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entry:
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%conv = uitofp i32 %e to double
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%mul = fmul double %conv, %conv
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%tobool = fcmp une double %mul, 0.000000e+00
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%cond = select i1 %tobool, double %conv, double 0.000000e+00
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%conv3 = fptosi double %cond to i16
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store i16 %conv3, i16* undef
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ret void
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}
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attributes #0 = { "no-infs-fp-math"="true" "no-nans-fp-math"="true" }
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