diff --git a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
index 2002f0938663..43dcfdca6bce 100644
--- a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -560,7 +560,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
   assert( LN->getAddressingMode() == ISD::UNINDEXED
           && "we should get only UNINDEXED adresses");
   // clean aligned loads can be selected as-is
-  if (InVT.getSizeInBits() == 128 && alignment == 16)
+  if (InVT.getSizeInBits() == 128 && (alignment%16) == 0)
     return SDValue();
 
   // Get pointerinfos to the memory chunk(s) that contain the data to load
@@ -573,7 +573,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
   SDValue basePtr = LN->getBasePtr();
   SDValue rotate;
 
-  if (alignment == 16) {
+  if ((alignment%16) == 0) {
     ConstantSDNode *CN;
 
     // Special cases for a known aligned load to simplify the base pointer
@@ -777,7 +777,7 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
   assert( SN->getAddressingMode() == ISD::UNINDEXED
           && "we should get only UNINDEXED adresses");
   // clean aligned loads can be selected as-is
-  if (StVT.getSizeInBits() == 128 && alignment == 16)
+  if (StVT.getSizeInBits() == 128 && (alignment%16) == 0)
     return SDValue();
 
   SDValue alignLoadVec;
@@ -785,7 +785,7 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
   SDValue the_chain = SN->getChain();
   SDValue insertEltOffs;
 
-  if (alignment == 16) {
+  if ((alignment%16) == 0) {
     ConstantSDNode *CN;
     // Special cases for a known aligned load to simplify the base pointer
     // and insertion byte:
diff --git a/llvm/test/CodeGen/CellSPU/stores.ll b/llvm/test/CodeGen/CellSPU/stores.ll
index efc915ca2691..7e0bf06b4e45 100644
--- a/llvm/test/CodeGen/CellSPU/stores.ll
+++ b/llvm/test/CodeGen/CellSPU/stores.ll
@@ -162,3 +162,12 @@ define void @store_misaligned( i32 %val, i32* %ptr) {
 	store i32 %val, i32*%ptr, align 2
 	ret void
 }
+
+define void @store_v8( <8 x float> %val, <8 x float>* %ptr )
+{
+;CHECK: stq
+;CHECK: stq
+;CHECK: bi $lr
+	store <8 x float> %val, <8 x float>* %ptr
+	ret void
+}