forked from OSchip/llvm-project
parent
6a124a84dc
commit
7e4d9969cb
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@ -1437,6 +1437,14 @@ def: SetCC_R16<setult, SltuCCRxRy16>;
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def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
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def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
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(AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
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// hi/lo relocs
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def : Mips16Pat<(MipsHi tglobaltlsaddr:$in),
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(SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>;
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// wrapper_pic
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class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
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Mips16Pat<(MipsWrapper RC:$gp, node:$in),
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@ -1445,5 +1453,3 @@ class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
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def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>;
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def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
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(AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
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@ -0,0 +1,15 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=PIC16
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@f.i = internal thread_local unnamed_addr global i32 1, align 4
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define i8* @f(i8* nocapture %a) nounwind {
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entry:
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%0 = load i32* @f.i, align 4
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%inc = add nsw i32 %0, 1
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store i32 %inc, i32* @f.i, align 4
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%1 = inttoptr i32 %inc to i8*
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; PIC16: addiu ${{[0-9]+}}, %tlsldm(f.i)
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ret i8* %1
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}
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