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[CodeGen] Fix warnings in getVectorTypeBreakdown 

Added NextPowerOf2() routine to TypeSize and rewritten the code
in getVectorTypeBreakdown to avoid warnings being generated.

Differential Revision: https://reviews.llvm.org/D81578
This commit is contained in:
David Sherwood 2020-06-11 07:47:23 +01:00
parent 6d18c2067e
commit 7e30ef77f6
2 changed files with 10 additions and 6 deletions
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4
llvm/include/llvm/Support/TypeSize.h
View File

@ -229,6 +229,10 @@ public:
TypeSize operator/(int64_t RHS) const {
return { MinSize / RHS, IsScalable };
}
TypeSize NextPowerOf2() const {
return TypeSize(llvm::NextPowerOf2(MinSize), IsScalable);
}
};
/// Returns a TypeSize with a known minimum size that is the next integer

10
llvm/lib/CodeGen/TargetLoweringBase.cpp
View File

@ -1474,14 +1474,14 @@ unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT
MVT DestVT = getRegisterType(Context, NewVT);
RegisterVT = DestVT;
unsigned NewVTSize = NewVT.getSizeInBits();
if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16.
TypeSize NewVTSize = NewVT.getSizeInBits();
// Convert sizes such as i33 to i64.
if (!isPowerOf2_32(NewVTSize))
NewVTSize = NextPowerOf2(NewVTSize);
if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
if (!isPowerOf2_32(NewVTSize.getKnownMinSize()))
NewVTSize = NewVTSize.NextPowerOf2();
return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
}
// Otherwise, promotion or legal types use the same number of registers as
// the vector decimated to the appropriate level.