forked from OSchip/llvm-project
[CodeGen] Fix warnings in getVectorTypeBreakdown
Added NextPowerOf2() routine to TypeSize and rewritten the code in getVectorTypeBreakdown to avoid warnings being generated. Differential Revision: https://reviews.llvm.org/D81578
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@ -229,6 +229,10 @@ public:
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TypeSize operator/(int64_t RHS) const {
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TypeSize operator/(int64_t RHS) const {
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return { MinSize / RHS, IsScalable };
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return { MinSize / RHS, IsScalable };
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}
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}
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TypeSize NextPowerOf2() const {
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return TypeSize(llvm::NextPowerOf2(MinSize), IsScalable);
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}
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};
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};
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/// Returns a TypeSize with a known minimum size that is the next integer
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/// Returns a TypeSize with a known minimum size that is the next integer
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@ -1474,14 +1474,14 @@ unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT
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MVT DestVT = getRegisterType(Context, NewVT);
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MVT DestVT = getRegisterType(Context, NewVT);
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RegisterVT = DestVT;
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RegisterVT = DestVT;
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unsigned NewVTSize = NewVT.getSizeInBits();
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if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16.
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TypeSize NewVTSize = NewVT.getSizeInBits();
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// Convert sizes such as i33 to i64.
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// Convert sizes such as i33 to i64.
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if (!isPowerOf2_32(NewVTSize))
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if (!isPowerOf2_32(NewVTSize.getKnownMinSize()))
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NewVTSize = NextPowerOf2(NewVTSize);
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NewVTSize = NewVTSize.NextPowerOf2();
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if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
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return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
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return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
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}
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// Otherwise, promotion or legal types use the same number of registers as
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// Otherwise, promotion or legal types use the same number of registers as
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// the vector decimated to the appropriate level.
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// the vector decimated to the appropriate level.
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