From 7e30404c3b6c3610a0d704e8433a3a3134ce982a Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Fri, 5 Nov 2021 13:28:35 -0400 Subject: [PATCH] [DAGCombiner] add fold for vselect based on mask of signbit, part 2 This is the 'or' sibling for the fold added with: D113212 https://alive2.llvm.org/ce/z/tgnp7K Note that neither of these transforms is poison-safe, but it does not seem to matter at this level. We have had the scalar version of D113212 for a long time, so this is just making optimizer behavior consistent. We do not have the scalar version of *this* fold, however, so that is another follow-up. --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 13 ++- .../test/CodeGen/AArch64/vselect-constants.ll | 16 +-- .../CodeGen/Thumb2/mve-vselect-constants.ll | 15 +-- llvm/test/CodeGen/X86/vselect-zero.ll | 106 +++++++----------- 4 files changed, 67 insertions(+), 83 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 14fc62dca3fe..07a2ac8db511 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -9549,7 +9549,7 @@ static SDValue foldVSelectToSignBitSplatMask(SDNode *N, SelectionDAG &DAG) { SDValue N1 = N->getOperand(1); SDValue N2 = N->getOperand(2); EVT VT = N->getValueType(0); - if (N0.getOpcode() != ISD::SETCC || !N0.hasOneUse() || !isNullOrNullSplat(N2)) + if (N0.getOpcode() != ISD::SETCC || !N0.hasOneUse()) return SDValue(); SDValue Cond0 = N0.getOperand(0); @@ -9559,13 +9559,22 @@ static SDValue foldVSelectToSignBitSplatMask(SDNode *N, SelectionDAG &DAG) { return SDValue(); // (Cond0 s< 0) ? N1 : 0 --> (Cond0 s>> BW-1) & N1 - if (CC == ISD::SETLT && isNullOrNullSplat(Cond1)) { + if (CC == ISD::SETLT && isNullOrNullSplat(Cond1) && isNullOrNullSplat(N2)) { SDLoc DL(N); SDValue ShiftAmt = DAG.getConstant(VT.getScalarSizeInBits() - 1, DL, VT); SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); return DAG.getNode(ISD::AND, DL, VT, Sra, N1); } + // (Cond0 s< 0) ? -1 : N2 --> (Cond0 s>> BW-1) | N2 + if (CC == ISD::SETLT && isNullOrNullSplat(Cond1) && + isAllOnesOrAllOnesSplat(N1)) { + SDLoc DL(N); + SDValue ShiftAmt = DAG.getConstant(VT.getScalarSizeInBits() - 1, DL, VT); + SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); + return DAG.getNode(ISD::OR, DL, VT, Sra, N2); + } + return SDValue(); } diff --git a/llvm/test/CodeGen/AArch64/vselect-constants.ll b/llvm/test/CodeGen/AArch64/vselect-constants.ll index f655a0dca23c..b206c88c5cb8 100644 --- a/llvm/test/CodeGen/AArch64/vselect-constants.ll +++ b/llvm/test/CodeGen/AArch64/vselect-constants.ll @@ -240,8 +240,8 @@ define <2 x i64> @signbit_mask_v2i64(<2 x i64> %a, <2 x i64> %b) { define <16 x i8> @signbit_setmask_v16i8(<16 x i8> %a, <16 x i8> %b) { ; CHECK-LABEL: signbit_setmask_v16i8: ; CHECK: // %bb.0: -; CHECK-NEXT: cmlt v0.16b, v0.16b, #0 -; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b +; CHECK-NEXT: sshr v0.16b, v0.16b, #7 +; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: ret %cond = icmp slt <16 x i8> %a, zeroinitializer %r = select <16 x i1> %cond, <16 x i8> , <16 x i8> %b @@ -251,8 +251,8 @@ define <16 x i8> @signbit_setmask_v16i8(<16 x i8> %a, <16 x i8> %b) { define <8 x i16> @signbit_setmask_v8i16(<8 x i16> %a, <8 x i16> %b) { ; CHECK-LABEL: signbit_setmask_v8i16: ; CHECK: // %bb.0: -; CHECK-NEXT: cmlt v0.8h, v0.8h, #0 -; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b +; CHECK-NEXT: sshr v0.8h, v0.8h, #15 +; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: ret %cond = icmp slt <8 x i16> %a, zeroinitializer %r = select <8 x i1> %cond, <8 x i16> , <8 x i16> %b @@ -262,8 +262,8 @@ define <8 x i16> @signbit_setmask_v8i16(<8 x i16> %a, <8 x i16> %b) { define <4 x i32> @signbit_setmask_v4i32(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: signbit_setmask_v4i32: ; CHECK: // %bb.0: -; CHECK-NEXT: cmlt v0.4s, v0.4s, #0 -; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b +; CHECK-NEXT: sshr v0.4s, v0.4s, #31 +; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: ret %cond = icmp slt <4 x i32> %a, zeroinitializer %r = select <4 x i1> %cond, <4 x i32> , <4 x i32> %b @@ -273,8 +273,8 @@ define <4 x i32> @signbit_setmask_v4i32(<4 x i32> %a, <4 x i32> %b) { define <2 x i64> @signbit_setmask_v2i64(<2 x i64> %a, <2 x i64> %b) { ; CHECK-LABEL: signbit_setmask_v2i64: ; CHECK: // %bb.0: -; CHECK-NEXT: cmlt v0.2d, v0.2d, #0 -; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b +; CHECK-NEXT: sshr v0.2d, v0.2d, #63 +; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: ret %cond = icmp slt <2 x i64> %a, zeroinitializer %r = select <2 x i1> %cond, <2 x i64> , <2 x i64> %b diff --git a/llvm/test/CodeGen/Thumb2/mve-vselect-constants.ll b/llvm/test/CodeGen/Thumb2/mve-vselect-constants.ll index 1c89c55173db..534a6b1b7295 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vselect-constants.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vselect-constants.ll @@ -186,9 +186,8 @@ define arm_aapcs_vfpcc <2 x i64> @signbit_mask_v2i64(<2 x i64> %a, <2 x i64> %b) define arm_aapcs_vfpcc <16 x i8> @signbit_setmask_v16i8(<16 x i8> %a, <16 x i8> %b) { ; CHECK-LABEL: signbit_setmask_v16i8: ; CHECK: @ %bb.0: -; CHECK-NEXT: vmov.i8 q2, #0xff -; CHECK-NEXT: vcmp.s8 lt, q0, zr -; CHECK-NEXT: vpsel q0, q2, q1 +; CHECK-NEXT: vshr.s8 q0, q0, #7 +; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: bx lr %cond = icmp slt <16 x i8> %a, zeroinitializer %r = select <16 x i1> %cond, <16 x i8> , <16 x i8> %b @@ -198,9 +197,8 @@ define arm_aapcs_vfpcc <16 x i8> @signbit_setmask_v16i8(<16 x i8> %a, <16 x i8> define arm_aapcs_vfpcc <8 x i16> @signbit_setmask_v8i16(<8 x i16> %a, <8 x i16> %b) { ; CHECK-LABEL: signbit_setmask_v8i16: ; CHECK: @ %bb.0: -; CHECK-NEXT: vmov.i8 q2, #0xff -; CHECK-NEXT: vcmp.s16 lt, q0, zr -; CHECK-NEXT: vpsel q0, q2, q1 +; CHECK-NEXT: vshr.s16 q0, q0, #15 +; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: bx lr %cond = icmp slt <8 x i16> %a, zeroinitializer %r = select <8 x i1> %cond, <8 x i16> , <8 x i16> %b @@ -210,9 +208,8 @@ define arm_aapcs_vfpcc <8 x i16> @signbit_setmask_v8i16(<8 x i16> %a, <8 x i16> define arm_aapcs_vfpcc <4 x i32> @signbit_setmask_v4i32(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: signbit_setmask_v4i32: ; CHECK: @ %bb.0: -; CHECK-NEXT: vmov.i8 q2, #0xff -; CHECK-NEXT: vcmp.s32 lt, q0, zr -; CHECK-NEXT: vpsel q0, q2, q1 +; CHECK-NEXT: vshr.s32 q0, q0, #31 +; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: bx lr %cond = icmp slt <4 x i32> %a, zeroinitializer %r = select <4 x i1> %cond, <4 x i32> , <4 x i32> %b diff --git a/llvm/test/CodeGen/X86/vselect-zero.ll b/llvm/test/CodeGen/X86/vselect-zero.ll index 4bcc57e4d433..e090ee3999e9 100644 --- a/llvm/test/CodeGen/X86/vselect-zero.ll +++ b/llvm/test/CodeGen/X86/vselect-zero.ll @@ -407,16 +407,13 @@ define <16 x i8> @signbit_setmask_v16i8(<16 x i8> %a, <16 x i8> %b) { define <8 x i16> @signbit_setmask_v8i16(<8 x i16> %a, <8 x i16> %b) { ; SSE-LABEL: signbit_setmask_v8i16: ; SSE: # %bb.0: -; SSE-NEXT: pxor %xmm2, %xmm2 -; SSE-NEXT: pcmpgtw %xmm0, %xmm2 -; SSE-NEXT: por %xmm1, %xmm2 -; SSE-NEXT: movdqa %xmm2, %xmm0 +; SSE-NEXT: psraw $15, %xmm0 +; SSE-NEXT: por %xmm1, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: signbit_setmask_v8i16: ; AVX: # %bb.0: -; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 -; AVX-NEXT: vpcmpgtw %xmm0, %xmm2, %xmm0 +; AVX-NEXT: vpsraw $15, %xmm0, %xmm0 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq %cond = icmp slt <8 x i16> %a, zeroinitializer @@ -427,16 +424,13 @@ define <8 x i16> @signbit_setmask_v8i16(<8 x i16> %a, <8 x i16> %b) { define <4 x i32> @signbit_setmask_v4i32(<4 x i32> %a, <4 x i32> %b) { ; SSE-LABEL: signbit_setmask_v4i32: ; SSE: # %bb.0: -; SSE-NEXT: pxor %xmm2, %xmm2 -; SSE-NEXT: pcmpgtd %xmm0, %xmm2 -; SSE-NEXT: por %xmm1, %xmm2 -; SSE-NEXT: movdqa %xmm2, %xmm0 +; SSE-NEXT: psrad $31, %xmm0 +; SSE-NEXT: por %xmm1, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: signbit_setmask_v4i32: ; AVX: # %bb.0: -; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 -; AVX-NEXT: vpcmpgtd %xmm0, %xmm2, %xmm0 +; AVX-NEXT: vpsrad $31, %xmm0, %xmm0 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq %cond = icmp slt <4 x i32> %a, zeroinitializer @@ -447,9 +441,8 @@ define <4 x i32> @signbit_setmask_v4i32(<4 x i32> %a, <4 x i32> %b) { define <2 x i64> @signbit_setmask_v2i64(<2 x i64> %a, <2 x i64> %b) { ; SSE2-LABEL: signbit_setmask_v2i64: ; SSE2: # %bb.0: -; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] -; SSE2-NEXT: pxor %xmm0, %xmm0 -; SSE2-NEXT: pcmpgtd %xmm2, %xmm0 +; SSE2-NEXT: psrad $31, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: retq ; @@ -477,12 +470,12 @@ define <32 x i8> @signbit_setmask_v32i8(<32 x i8> %a, <32 x i8> %b) { ; SSE: # %bb.0: ; SSE-NEXT: pxor %xmm4, %xmm4 ; SSE-NEXT: pxor %xmm5, %xmm5 -; SSE-NEXT: pcmpgtb %xmm1, %xmm5 -; SSE-NEXT: pcmpgtb %xmm0, %xmm4 -; SSE-NEXT: por %xmm2, %xmm4 -; SSE-NEXT: por %xmm3, %xmm5 -; SSE-NEXT: movdqa %xmm4, %xmm0 -; SSE-NEXT: movdqa %xmm5, %xmm1 +; SSE-NEXT: pcmpgtb %xmm0, %xmm5 +; SSE-NEXT: por %xmm2, %xmm5 +; SSE-NEXT: pcmpgtb %xmm1, %xmm4 +; SSE-NEXT: por %xmm3, %xmm4 +; SSE-NEXT: movdqa %xmm5, %xmm0 +; SSE-NEXT: movdqa %xmm4, %xmm1 ; SSE-NEXT: retq ; ; AVX1-LABEL: signbit_setmask_v32i8: @@ -509,30 +502,24 @@ define <32 x i8> @signbit_setmask_v32i8(<32 x i8> %a, <32 x i8> %b) { define <16 x i16> @signbit_setmask_v16i16(<16 x i16> %a, <16 x i16> %b) { ; SSE-LABEL: signbit_setmask_v16i16: ; SSE: # %bb.0: -; SSE-NEXT: pxor %xmm4, %xmm4 -; SSE-NEXT: pxor %xmm5, %xmm5 -; SSE-NEXT: pcmpgtw %xmm1, %xmm5 -; SSE-NEXT: pcmpgtw %xmm0, %xmm4 -; SSE-NEXT: por %xmm2, %xmm4 -; SSE-NEXT: por %xmm3, %xmm5 -; SSE-NEXT: movdqa %xmm4, %xmm0 -; SSE-NEXT: movdqa %xmm5, %xmm1 +; SSE-NEXT: psraw $15, %xmm0 +; SSE-NEXT: por %xmm2, %xmm0 +; SSE-NEXT: psraw $15, %xmm1 +; SSE-NEXT: por %xmm3, %xmm1 ; SSE-NEXT: retq ; ; AVX1-LABEL: signbit_setmask_v16i16: ; AVX1: # %bb.0: -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 -; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 -; AVX1-NEXT: vpcmpgtw %xmm2, %xmm3, %xmm2 -; AVX1-NEXT: vpcmpgtw %xmm0, %xmm3, %xmm0 -; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: vpsraw $15, %xmm0, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 +; AVX1-NEXT: vpsraw $15, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0 ; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: retq ; ; AVX2-LABEL: signbit_setmask_v16i16: ; AVX2: # %bb.0: -; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 -; AVX2-NEXT: vpcmpgtw %ymm0, %ymm2, %ymm0 +; AVX2-NEXT: vpsraw $15, %ymm0, %ymm0 ; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq %cond = icmp slt <16 x i16> %a, zeroinitializer @@ -543,30 +530,24 @@ define <16 x i16> @signbit_setmask_v16i16(<16 x i16> %a, <16 x i16> %b) { define <8 x i32> @signbit_setmask_v8i32(<8 x i32> %a, <8 x i32> %b) { ; SSE-LABEL: signbit_setmask_v8i32: ; SSE: # %bb.0: -; SSE-NEXT: pxor %xmm4, %xmm4 -; SSE-NEXT: pxor %xmm5, %xmm5 -; SSE-NEXT: pcmpgtd %xmm1, %xmm5 -; SSE-NEXT: pcmpgtd %xmm0, %xmm4 -; SSE-NEXT: por %xmm2, %xmm4 -; SSE-NEXT: por %xmm3, %xmm5 -; SSE-NEXT: movdqa %xmm4, %xmm0 -; SSE-NEXT: movdqa %xmm5, %xmm1 +; SSE-NEXT: psrad $31, %xmm0 +; SSE-NEXT: por %xmm2, %xmm0 +; SSE-NEXT: psrad $31, %xmm1 +; SSE-NEXT: por %xmm3, %xmm1 ; SSE-NEXT: retq ; ; AVX1-LABEL: signbit_setmask_v8i32: ; AVX1: # %bb.0: -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 -; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 -; AVX1-NEXT: vpcmpgtd %xmm2, %xmm3, %xmm2 -; AVX1-NEXT: vpcmpgtd %xmm0, %xmm3, %xmm0 -; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: vpsrad $31, %xmm0, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 +; AVX1-NEXT: vpsrad $31, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0 ; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: retq ; ; AVX2-LABEL: signbit_setmask_v8i32: ; AVX2: # %bb.0: -; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 -; AVX2-NEXT: vpcmpgtd %ymm0, %ymm2, %ymm0 +; AVX2-NEXT: vpsrad $31, %ymm0, %ymm0 ; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq %cond = icmp slt <8 x i32> %a, zeroinitializer @@ -577,27 +558,24 @@ define <8 x i32> @signbit_setmask_v8i32(<8 x i32> %a, <8 x i32> %b) { define <4 x i64> @signbit_setmask_v4i64(<4 x i64> %a, <4 x i64> %b) { ; SSE2-LABEL: signbit_setmask_v4i64: ; SSE2: # %bb.0: -; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm1[1,1,3,3] -; SSE2-NEXT: pxor %xmm4, %xmm4 -; SSE2-NEXT: pxor %xmm1, %xmm1 -; SSE2-NEXT: pcmpgtd %xmm5, %xmm1 +; SSE2-NEXT: psrad $31, %xmm0 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] -; SSE2-NEXT: pcmpgtd %xmm0, %xmm4 -; SSE2-NEXT: por %xmm2, %xmm4 +; SSE2-NEXT: por %xmm2, %xmm0 +; SSE2-NEXT: psrad $31, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSE2-NEXT: por %xmm3, %xmm1 -; SSE2-NEXT: movdqa %xmm4, %xmm0 ; SSE2-NEXT: retq ; ; SSE42-LABEL: signbit_setmask_v4i64: ; SSE42: # %bb.0: ; SSE42-NEXT: pxor %xmm4, %xmm4 ; SSE42-NEXT: pxor %xmm5, %xmm5 -; SSE42-NEXT: pcmpgtq %xmm1, %xmm5 -; SSE42-NEXT: pcmpgtq %xmm0, %xmm4 -; SSE42-NEXT: por %xmm2, %xmm4 -; SSE42-NEXT: por %xmm3, %xmm5 -; SSE42-NEXT: movdqa %xmm4, %xmm0 -; SSE42-NEXT: movdqa %xmm5, %xmm1 +; SSE42-NEXT: pcmpgtq %xmm0, %xmm5 +; SSE42-NEXT: por %xmm2, %xmm5 +; SSE42-NEXT: pcmpgtq %xmm1, %xmm4 +; SSE42-NEXT: por %xmm3, %xmm4 +; SSE42-NEXT: movdqa %xmm5, %xmm0 +; SSE42-NEXT: movdqa %xmm4, %xmm1 ; SSE42-NEXT: retq ; ; AVX1-LABEL: signbit_setmask_v4i64: