forked from OSchip/llvm-project
[X86] Make post-ra scheduling macrofusion-aware.
Subscribers: MatzeB, arsenm, jvesely, nhaehnle, hiraditya, javed.absar, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59688 llvm-svn: 357384
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@ -14,6 +14,7 @@
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#include "X86CallLowering.h"
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#include "X86LegalizerInfo.h"
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#include "X86MacroFusion.h"
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#include "X86RegisterBankInfo.h"
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#include "X86Subtarget.h"
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#include "MCTargetDesc/X86BaseInfo.h"
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@ -366,3 +367,8 @@ const RegisterBankInfo *X86Subtarget::getRegBankInfo() const {
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bool X86Subtarget::enableEarlyIfConversion() const {
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return hasCMov() && X86EarlyIfConv;
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}
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void X86Subtarget::getPostRAMutations(
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std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
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Mutations.push_back(createX86MacroFusionDAGMutation());
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}
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@ -843,6 +843,9 @@ public:
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bool enableEarlyIfConversion() const override;
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void getPostRAMutations(
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std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const;
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AntiDepBreakMode getAntiDepBreakMode() const override {
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return TargetSubtargetInfo::ANTIDEP_CRITICAL;
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}
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@ -45,8 +45,8 @@ define i32 @macrofuse_test_je(i32 %flags, i8* %p) nounwind {
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; BRANCHFUSION_POSTRA-LABEL: macrofuse_test_je:
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; BRANCHFUSION_POSTRA: # %bb.0: # %entry
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; BRANCHFUSION_POSTRA-NEXT: xorl %eax, %eax
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; BRANCHFUSION_POSTRA-NEXT: testl $512, %edi # imm = 0x200
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; BRANCHFUSION_POSTRA-NEXT: movb $1, (%rsi)
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; BRANCHFUSION_POSTRA-NEXT: testl $512, %edi # imm = 0x200
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; BRANCHFUSION_POSTRA-NEXT: je .LBB0_2
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; BRANCHFUSION_POSTRA-NEXT: # %bb.1: # %if.then
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; BRANCHFUSION_POSTRA-NEXT: movl $1, %eax
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@ -105,8 +105,8 @@ define i32 @macrofuse_cmp_je(i32 %flags, i8* %p) nounwind {
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;
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; BRANCHFUSION_POSTRA-LABEL: macrofuse_cmp_je:
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; BRANCHFUSION_POSTRA: # %bb.0: # %entry
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; BRANCHFUSION_POSTRA-NEXT: cmpl $512, %edi # imm = 0x200
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; BRANCHFUSION_POSTRA-NEXT: movb $1, (%rsi)
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; BRANCHFUSION_POSTRA-NEXT: cmpl $512, %edi # imm = 0x200
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; BRANCHFUSION_POSTRA-NEXT: je .LBB1_1
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; BRANCHFUSION_POSTRA-NEXT: # %bb.2: # %if.then
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; BRANCHFUSION_POSTRA-NEXT: movl $1, %eax
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