forked from OSchip/llvm-project
[ARM] Fix assembly and disassembly for VMRS/VMSR
This patch addresses two issues with assembly and disassembly for VMRS/VMSR:
1.currently VMRS/VMSR instructions accessing fpsid, mvfr{0-2} and fpexc, are
accepted for non ARMv8-A targets.
2. all VMRS/VMSR instructions accept writing/reading to PC and SP, when only
ARMv7-A and ARMv8-A should be allowed to write/read to SP and none to PC.
This patch addresses those issues and adds tests for these cases.
Differential Revision: https://reviews.llvm.org/D36306
llvm-svn: 310243
This commit is contained in:
Andre Vieira
parent
5d432ec929
commit
7dffb9bfa6
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@ -2160,28 +2160,32 @@ let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in
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def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
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"vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
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// Application level FPSCR -> GPR
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let hasSideEffects = 1, Uses = [FPSCR] in
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def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
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"vmrs", "\t$Rt, fpscr",
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[(set GPR:$Rt, (int_arm_get_fpscr))]>;
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let DecoderMethod = "DecodeForVMRSandVMSR" in {
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// Application level FPSCR -> GPR
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let hasSideEffects = 1, Uses = [FPSCR] in
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def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPRnopc:$Rt), (ins),
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"vmrs", "\t$Rt, fpscr",
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[(set GPRnopc:$Rt, (int_arm_get_fpscr))]>;
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// System level FPEXC, FPSID -> GPR
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let Uses = [FPSCR] in {
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def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
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"vmrs", "\t$Rt, fpexc", []>;
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def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
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"vmrs", "\t$Rt, fpsid", []>;
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def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins),
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"vmrs", "\t$Rt, mvfr0", []>;
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def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
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"vmrs", "\t$Rt, mvfr1", []>;
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def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPR:$Rt), (ins),
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"vmrs", "\t$Rt, mvfr2", []>, Requires<[HasFPARMv8]>;
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def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins),
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"vmrs", "\t$Rt, fpinst", []>;
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def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins),
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"vmrs", "\t$Rt, fpinst2", []>;
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// System level FPEXC, FPSID -> GPR
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let Uses = [FPSCR] in {
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let Predicates = [HasV8, HasVFP2] in {
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def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPRnopc:$Rt), (ins),
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"vmrs", "\t$Rt, fpexc", []>;
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def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPRnopc:$Rt), (ins),
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"vmrs", "\t$Rt, fpsid", []>;
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def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPRnopc:$Rt), (ins),
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"vmrs", "\t$Rt, mvfr0", []>;
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def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPRnopc:$Rt), (ins),
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"vmrs", "\t$Rt, mvfr1", []>;
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def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPRnopc:$Rt), (ins),
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"vmrs", "\t$Rt, mvfr2", []>;
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}
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def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPRnopc:$Rt), (ins),
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"vmrs", "\t$Rt, fpinst", []>;
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def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPRnopc:$Rt),
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(ins), "vmrs", "\t$Rt, fpinst2", []>;
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}
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}
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//===----------------------------------------------------------------------===//
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@ -2205,21 +2209,25 @@ class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
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let Inst{4} = 1;
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}
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let Defs = [FPSCR] in {
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// Application level GPR -> FPSCR
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def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
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"vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
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// System level GPR -> FPEXC
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def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src),
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"vmsr", "\tfpexc, $src", []>;
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// System level GPR -> FPSID
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def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src),
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"vmsr", "\tfpsid, $src", []>;
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def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPR:$src),
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let DecoderMethod = "DecodeForVMRSandVMSR" in {
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let Defs = [FPSCR] in {
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// Application level GPR -> FPSCR
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def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPRnopc:$src),
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"vmsr", "\tfpscr, $src",
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[(int_arm_set_fpscr GPRnopc:$src)]>;
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let Predicates = [HasV8, HasVFP2] in {
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// System level GPR -> FPEXC
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def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPRnopc:$src),
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"vmsr", "\tfpexc, $src", []>;
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// System level GPR -> FPSID
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def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPRnopc:$src),
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"vmsr", "\tfpsid, $src", []>;
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}
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def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPRnopc:$src),
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"vmsr", "\tfpinst, $src", []>;
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def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPR:$src),
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"vmsr", "\tfpinst2, $src", []>;
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def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPRnopc:$src),
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"vmsr", "\tfpinst2, $src", []>;
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}
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}
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//===----------------------------------------------------------------------===//
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@ -8746,6 +8746,11 @@ unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
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return Match_RequiresV8;
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}
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// Use of SP for VMRS/VMSR is only allowed in ARM mode.
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if ((Inst.getOpcode() == ARM::VMRS || Inst.getOpcode() == ARM::VMSR) &&
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Inst.getOperand(0).getReg() == ARM::SP && (isThumb() && !hasV8Ops()))
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return Match_InvalidOperand;
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for (unsigned I = 0; I < MCID.NumOperands; ++I)
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if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
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// rGPRRegClass excludes PC, and also excluded SP before ARMv8
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@ -398,6 +398,8 @@ static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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#include "ARMGenDisassemblerTables.inc"
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@ -5270,3 +5272,25 @@ static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
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return S;
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}
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static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
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uint64_t Address,
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const void *Decoder) {
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const FeatureBitset &featureBits =
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((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
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DecodeStatus S = MCDisassembler::Success;
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unsigned Rt = fieldFromInstruction(Val, 12, 4);
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if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
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if (Rt == 13 || Rt == 15)
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S = MCDisassembler::SoftFail;
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Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
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} else
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Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
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Inst.addOperand(MCOperand::createImm(ARMCC::AL));
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Inst.addOperand(MCOperand::createReg(0));
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return S;
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}
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@ -16,8 +16,6 @@
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.type fp,%function
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fp:
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vmrs r0, mvfr2
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@ CHECK-V7: error: instruction requires: FPARMv8
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vselgt.f32 s0, s0, s0
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@ CHECK-V7: error: instruction requires: FPARMv8
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@ -152,8 +150,6 @@ fp:
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.type nofp,%function
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nofp:
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vmrs r0, mvfr2
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@ CHECK: error: instruction requires: FPARMv8
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vselgt.f32 s0, s0, s0
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@ CHECK: error: instruction requires: FPARMv8
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@ -132,18 +132,10 @@
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vmrs APSR_nzcv, fpscr
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vmrs apsr_nzcv, fpscr
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fmstat
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vmrs r2, fpsid
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vmrs r3, FPSID
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vmrs r4, mvfr0
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vmrs r5, MVFR1
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@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
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@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
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@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
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@ CHECK: vmrs r2, fpsid @ encoding: [0x10,0x2a,0xf0,0xee]
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@ CHECK: vmrs r3, fpsid @ encoding: [0x10,0x3a,0xf0,0xee]
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@ CHECK: vmrs r4, mvfr0 @ encoding: [0x10,0x4a,0xf7,0xee]
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@ CHECK: vmrs r5, mvfr1 @ encoding: [0x10,0x5a,0xf6,0xee]
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@ CHECK: vnegne.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0x1e]
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vnegne.f64 d16, d16
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@ -165,10 +157,6 @@
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@ CHECK: vmrs r0, fpscr @ encoding: [0x10,0x0a,0xf1,0xee]
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vmrs r0, fpscr
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@ CHECK: vmrs r0, fpexc @ encoding: [0x10,0x0a,0xf8,0xee]
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vmrs r0, fpexc
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@ CHECK: vmrs r0, fpsid @ encoding: [0x10,0x0a,0xf0,0xee]
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vmrs r0, fpsid
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@ CHECK: vmrs r1, fpinst @ encoding: [0x10,0x1a,0xf9,0xee]
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vmrs r1, fpinst
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@ CHECK: vmrs r8, fpinst2 @ encoding: [0x10,0x8a,0xfa,0xee]
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@ -176,10 +164,6 @@
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@ CHECK: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
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vmsr fpscr, r0
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@ CHECK: vmsr fpexc, r0 @ encoding: [0x10,0x0a,0xe8,0xee]
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vmsr fpexc, r0
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@ CHECK: vmsr fpsid, r0 @ encoding: [0x10,0x0a,0xe0,0xee]
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vmsr fpsid, r0
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@ CHECK: vmsr fpinst, r3 @ encoding: [0x10,0x3a,0xe9,0xee]
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vmsr fpinst, r3
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@ CHECK: vmsr fpinst2, r4 @ encoding: [0x10,0x4a,0xea,0xee]
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@ -0,0 +1,180 @@
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// RUN: not llvm-mc -triple=armv7a-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
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// RUN: | FileCheck --check-prefix=CHECK-V7A-ARM %s
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// RUN: FileCheck --check-prefix=ERROR-V7A-ARM < %t %s
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// RUN: not llvm-mc -triple=thumbv7a-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
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// RUN: | FileCheck --check-prefix=CHECK-V7A-THUMB %s
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// RUN: FileCheck --check-prefix=ERROR-V7A-THUMB < %t %s
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// RUN: not llvm-mc -triple=thumbv7m-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
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// RUN: | FileCheck --check-prefix=CHECK-V7M %s
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// RUN: FileCheck --check-prefix=ERROR-V7M < %t %s
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// RUN: not llvm-mc -triple=armv8a-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
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// RUN: | FileCheck --check-prefix=CHECK-V8A-ARM %s
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// RUN: FileCheck --check-prefix=ERROR-V8A-ARM < %t %s
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// RUN: not llvm-mc -triple=thumbv8a-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
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// RUN: | FileCheck --check-prefix=CHECK-V8A-THUMB %s
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// RUN: FileCheck --check-prefix=ERROR-V8A-THUMB < %t %s
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// RUN: not llvm-mc -triple=thumbv8m.main-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
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// RUN: | FileCheck --check-prefix=CHECK-V8M %s
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// RUN: FileCheck --check-prefix=ERROR-V8M < %t %s
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// RUN: not llvm-mc -triple=thumbv7m-arm-none-eabi -show-encoding < %s 2>%t
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// RUN: FileCheck --check-prefix=ERROR-NOVFP < %t %s
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vmrs APSR_nzcv, fpscr
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vmrs apsr_nzcv, fpscr
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fmstat
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vmrs r10, fpscr
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vmrs r2, fpsid
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vmrs r3, FPSID
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vmrs r4, mvfr0
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vmrs r5, MVFR1
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vmrs r6, mvfr2
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vmrs sp, fpscr
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vmrs pc, fpscr
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// CHECK-V7A-ARM: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
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// CHECK-V7A-ARM: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
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// CHECK-V7A-ARM: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
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// CHECK-V7A-ARM: vmrs r10, fpscr @ encoding: [0x10,0xaa,0xf1,0xee]
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// ERROR-V7A-ARM: instruction requires: armv8
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// ERROR-V7A-ARM: instruction requires: armv8
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// ERROR-V7A-ARM: instruction requires: armv8
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// ERROR-V7A-ARM: instruction requires: armv8
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// ERROR-V7A-ARM: instruction requires: armv8
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// CHECK-V7A-ARM: vmrs sp, fpscr @ encoding: [0x10,0xda,0xf1,0xee]
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// ERROR-V7A-ARM: invalid operand for instruction
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// CHECK-V7A-THUMB: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
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// CHECK-V7A-THUMB: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
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// CHECK-V7A-THUMB: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
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// CHECK-V7A-THUMB: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
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// ERROR-V7A-THUMB: instruction requires: armv8
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// ERROR-V7A-THUMB: instruction requires: armv8
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// ERROR-V7A-THUMB: instruction requires: armv8
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// ERROR-V7A-THUMB: instruction requires: armv8
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// ERROR-V7A-THUMB: instruction requires: armv8
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// ERROR-V7A-THUMB: invalid operand for instruction
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// ERROR-V7A-THUMB: invalid operand for instruction
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// CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
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// CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
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// CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
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// CHECK-V7M: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
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// ERROR-V7M: instruction requires: armv8
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// ERROR-V7M: instruction requires: armv8
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// ERROR-V7M: instruction requires: armv8
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// ERROR-V7M: instruction requires: armv8
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// ERROR-V7M: instruction requires: armv8
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// ERROR-V7M: invalid operand for instruction
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// ERROR-V7M: invalid operand for instruction
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// CHECK-V8A-ARM: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
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// CHECK-V8A-ARM: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
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// CHECK-V8A-ARM: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
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// CHECK-V8A-ARM: vmrs r10, fpscr @ encoding: [0x10,0xaa,0xf1,0xee]
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// CHECK-V8A-ARM: vmrs r2, fpsid @ encoding: [0x10,0x2a,0xf0,0xee]
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// CHECK-V8A-ARM: vmrs r3, fpsid @ encoding: [0x10,0x3a,0xf0,0xee]
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// CHECK-V8A-ARM: vmrs r4, mvfr0 @ encoding: [0x10,0x4a,0xf7,0xee]
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// CHECK-V8A-ARM: vmrs r5, mvfr1 @ encoding: [0x10,0x5a,0xf6,0xee]
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// CHECK-V8A-ARM: vmrs r6, mvfr2 @ encoding: [0x10,0x6a,0xf5,0xee]
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// CHECK-V8A-ARM: vmrs sp, fpscr @ encoding: [0x10,0xda,0xf1,0xee]
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// ERROR-V8A-ARM: invalid operand for instruction
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// CHECK-V8A-THUMB: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
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// CHECK-V8A-THUMB: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
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// CHECK-V8A-THUMB: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
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// CHECK-V8A-THUMB: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
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// CHECK-V8A-THUMB: vmrs r2, fpsid @ encoding: [0xf0,0xee,0x10,0x2a]
|
||||
// CHECK-V8A-THUMB: vmrs r3, fpsid @ encoding: [0xf0,0xee,0x10,0x3a]
|
||||
// CHECK-V8A-THUMB: vmrs r4, mvfr0 @ encoding: [0xf7,0xee,0x10,0x4a]
|
||||
// CHECK-V8A-THUMB: vmrs r5, mvfr1 @ encoding: [0xf6,0xee,0x10,0x5a]
|
||||
// CHECK-V8A-THUMB: vmrs r6, mvfr2 @ encoding: [0xf5,0xee,0x10,0x6a]
|
||||
// CHECK-V8A-THUMB: vmrs sp, fpscr @ encoding: [0xf1,0xee,0x10,0xda]
|
||||
// ERROR-V8A-THUMB: invalid operand for instruction
|
||||
|
||||
// CHECK-V8M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
|
||||
// CHECK-V8M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
|
||||
// CHECK-V8M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
|
||||
// CHECK-V8M: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
|
||||
// ERROR-V8M: instruction requires: armv8
|
||||
// ERROR-V8M: instruction requires: armv8
|
||||
// ERROR-V8M: instruction requires: armv8
|
||||
// ERROR-V8M: instruction requires: armv8
|
||||
// ERROR-V8M: instruction requires: armv8
|
||||
// ERROR-V8M: invalid operand for instruction
|
||||
// ERROR-V8M: invalid operand for instruction
|
||||
|
||||
// ERROR-NOVFP: instruction requires: VFP2
|
||||
// ERROR-NOVFP: instruction requires: VFP2
|
||||
// ERROR-NOVFP: instruction requires: VFP2
|
||||
// ERROR-NOVFP: instruction requires: VFP2
|
||||
// ERROR-NOVFP: instruction requires: armv8
|
||||
// ERROR-NOVFP: instruction requires: armv8
|
||||
// ERROR-NOVFP: instruction requires: armv8
|
||||
// ERROR-NOVFP: instruction requires: armv8
|
||||
// ERROR-NOVFP: instruction requires: armv8
|
||||
// ERROR-NOVFP: instruction requires: VFP2
|
||||
// ERROR-NOVFP: invalid operand for instruction
|
||||
|
||||
vmsr fpscr, APSR_nzcv
|
||||
vmsr fpscr, r0
|
||||
vmsr fpexc, r1
|
||||
vmsr fpsid, r2
|
||||
vmsr fpscr, r10
|
||||
vmsr fpscr, sp
|
||||
vmsr fpscr, pc
|
||||
|
||||
// ERROR-V7A-ARM: invalid operand for instruction
|
||||
// CHECK-V7A-ARM: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
|
||||
// ERROR-V7A-ARM: instruction requires: armv8
|
||||
// ERROR-V7A-ARM: instruction requires: armv8
|
||||
// CHECK-V7A-ARM: vmsr fpscr, r10 @ encoding: [0x10,0xaa,0xe1,0xee]
|
||||
// CHECK-V7A-ARM: vmsr fpscr, sp @ encoding: [0x10,0xda,0xe1,0xee]
|
||||
// ERROR-V7A-ARM: invalid operand for instruction
|
||||
|
||||
// ERROR-V7A-THUMB: invalid operand for instruction
|
||||
// CHECK-V7A-THUMB: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
|
||||
// ERROR-V7A-THUMB: instruction requires: armv8
|
||||
// ERROR-V7A-THUMB: instruction requires: armv8
|
||||
// CHECK-V7A-THUMB: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
|
||||
// ERROR-V7A-THUMB: invalid operand for instruction
|
||||
// ERROR-V7A-THUMB: invalid operand for instruction
|
||||
|
||||
// ERROR-V7M: invalid operand for instruction
|
||||
// CHECK-V7M: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
|
||||
// ERROR-V7M: instruction requires: armv8
|
||||
// ERROR-V7M: instruction requires: armv8
|
||||
// CHECK-V7M: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
|
||||
// ERROR-V7M: invalid operand for instruction
|
||||
// ERROR-V7M: invalid operand for instruction
|
||||
|
||||
// ERROR-V8A-ARM: invalid operand for instruction
|
||||
// CHECK-V8A-ARM: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
|
||||
// CHECK-V8A-ARM: vmsr fpexc, r1 @ encoding: [0x10,0x1a,0xe8,0xee]
|
||||
// CHECK-V8A-ARM: vmsr fpsid, r2 @ encoding: [0x10,0x2a,0xe0,0xee]
|
||||
// CHECK-V8A-ARM: vmsr fpscr, r10 @ encoding: [0x10,0xaa,0xe1,0xee]
|
||||
// CHECK-V8A-ARM: vmsr fpscr, sp @ encoding: [0x10,0xda,0xe1,0xee]
|
||||
// ERROR-V8A-ARM: invalid operand for instruction
|
||||
|
||||
// ERROR-V8A-THUMB: invalid operand for instruction
|
||||
// CHECK-V8A-THUMB: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
|
||||
// CHECK-V8A-THUMB: vmsr fpexc, r1 @ encoding: [0xe8,0xee,0x10,0x1a]
|
||||
// CHECK-V8A-THUMB: vmsr fpsid, r2 @ encoding: [0xe0,0xee,0x10,0x2a]
|
||||
// CHECK-V8A-THUMB: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
|
||||
// CHECK-V8A-THUMB: vmsr fpscr, sp @ encoding: [0xe1,0xee,0x10,0xda]
|
||||
// ERROR-V8A-THUMB: invalid operand for instruction
|
||||
|
||||
// ERROR-V8M: invalid operand for instruction
|
||||
// CHECK-V8M: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
|
||||
// ERROR-V8M: instruction requires: armv8
|
||||
// ERROR-V8M: instruction requires: armv8
|
||||
// CHECK-V8M: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
|
||||
// ERROR-V8M: invalid operand for instruction
|
||||
// ERROR-V8M: invalid operand for instruction
|
||||
|
||||
// ERROR-NOVFP: invalid operand for instruction
|
||||
// ERROR-NOVFP: instruction requires: VFP2
|
||||
// ERROR-NOVFP: instruction requires: armv8
|
||||
// ERROR-NOVFP: instruction requires: armv8
|
||||
// ERROR-NOVFP: instruction requires: VFP2
|
||||
// ERROR-NOVFP: instruction requires: VFP2
|
||||
// ERROR-NOVFP: invalid operand for instruction
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
# RUN: not llvm-mc -disassemble -triple=armv7a-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
|
||||
# RUN: | FileCheck --check-prefix=CHECK-V7A %s
|
||||
# RUN: FileCheck --check-prefix=ERROR-V7A < %t %s
|
||||
# RUN: llvm-mc -disassemble -triple=armv8a-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
|
||||
# RUN: | FileCheck --check-prefix=CHECK-V8A %s
|
||||
# RUN: FileCheck --check-prefix=ERROR-V8A < %t %s
|
||||
|
||||
[0x10,0xfa,0xf1,0xee]
|
||||
[0x10,0xfa,0xf1,0xee]
|
||||
[0x10,0xfa,0xf1,0xee]
|
||||
[0x10,0xaa,0xf1,0xee]
|
||||
[0x10,0x2a,0xf0,0xee]
|
||||
[0x10,0x3a,0xf0,0xee]
|
||||
[0x10,0x4a,0xf7,0xee]
|
||||
[0x10,0x5a,0xf6,0xee]
|
||||
[0x10,0x6a,0xf5,0xee]
|
||||
[0x10,0xda,0xf1,0xee]
|
||||
|
||||
# CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
|
||||
# CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
|
||||
# CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
|
||||
# CHECK-V7A: vmrs r10, fpscr @ encoding: [0x10,0xaa,0xf1,0xee]
|
||||
# ERROR-V7A: invalid instruction encoding
|
||||
# ERROR-V7A: invalid instruction encoding
|
||||
# ERROR-V7A: invalid instruction encoding
|
||||
# ERROR-V7A: invalid instruction encoding
|
||||
# ERROR-V7A: invalid instruction encoding
|
||||
# CHECK-V7A: vmrs sp, fpscr @ encoding: [0x10,0xda,0xf1,0xee]
|
||||
|
||||
# CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
|
||||
# CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
|
||||
# CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
|
||||
# CHECK-V8A: vmrs r10, fpscr @ encoding: [0x10,0xaa,0xf1,0xee]
|
||||
# CHECK-V8A: vmrs r2, fpsid @ encoding: [0x10,0x2a,0xf0,0xee]
|
||||
# CHECK-V8A: vmrs r3, fpsid @ encoding: [0x10,0x3a,0xf0,0xee]
|
||||
# CHECK-V8A: vmrs r4, mvfr0 @ encoding: [0x10,0x4a,0xf7,0xee]
|
||||
# CHECK-V8A: vmrs r5, mvfr1 @ encoding: [0x10,0x5a,0xf6,0xee]
|
||||
# CHECK-V8A: vmrs r6, mvfr2 @ encoding: [0x10,0x6a,0xf5,0xee]
|
||||
# CHECK-V8A: vmrs sp, fpscr @ encoding: [0x10,0xda,0xf1,0xee]
|
||||
|
||||
[0x10,0xfa,0xe1,0xee]
|
||||
[0x10,0x0a,0xe1,0xee]
|
||||
[0x10,0x1a,0xe8,0xee]
|
||||
[0x10,0x2a,0xe0,0xee]
|
||||
[0x10,0xaa,0xe1,0xee]
|
||||
[0x10,0xda,0xe1,0xee]
|
||||
|
||||
# ERROR-V7A: potentially undefined instruction encoding
|
||||
# CHECK-V7A: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
|
||||
# ERROR-V7A: invalid instruction encoding
|
||||
# ERROR-V7A: invalid instruction encoding
|
||||
# CHECK-V7A: vmsr fpscr, r10 @ encoding: [0x10,0xaa,0xe1,0xee]
|
||||
# CHECK-V7A: vmsr fpscr, sp @ encoding: [0x10,0xda,0xe1,0xee]
|
||||
|
||||
# ERROR-V8A: potentially undefined instruction encoding
|
||||
# CHECK-V8A: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
|
||||
# CHECK-V8A: vmsr fpexc, r1 @ encoding: [0x10,0x1a,0xe8,0xee]
|
||||
# CHECK-V8A: vmsr fpsid, r2 @ encoding: [0x10,0x2a,0xe0,0xee]
|
||||
# CHECK-V8A: vmsr fpscr, r10 @ encoding: [0x10,0xaa,0xe1,0xee]
|
||||
# CHECK-V8A: vmsr fpscr, sp @ encoding: [0x10,0xda,0xe1,0xee]
|
||||
|
|
@ -118,10 +118,6 @@
|
|||
|
||||
0x10 0x0a 0xf1 0xee
|
||||
# CHECK: vmrs r0, fpscr
|
||||
0x10 0x0a 0xf8 0xee
|
||||
# CHECK: vmrs r0, fpexc
|
||||
0x10 0x0a 0xf0 0xee
|
||||
# CHECK: vmrs r0, fpsid
|
||||
0x10 0x1a 0xf9 0xee
|
||||
# CHECK: vmrs r1, fpinst
|
||||
0x10 0x8a 0xfa 0xee
|
||||
|
|
@ -129,10 +125,6 @@
|
|||
|
||||
0x10 0x0a 0xe1 0xee
|
||||
# CHECK: vmsr fpscr, r0
|
||||
0x10 0x0a 0xe8 0xee
|
||||
# CHECK: vmsr fpexc, r0
|
||||
0x10 0x0a 0xe0 0xee
|
||||
# CHECK: vmsr fpsid, r0
|
||||
0x10 0x3a 0xe9 0xee
|
||||
# CHECK: vmsr fpinst, r3
|
||||
0x10 0x4a 0xea 0xee
|
||||
|
|
|
|||
|
|
@ -0,0 +1,123 @@
|
|||
# RUN: not llvm-mc -disassemble -triple=thumbv7a-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
|
||||
# RUN: | FileCheck --check-prefix=CHECK-V7A %s
|
||||
# RUN: FileCheck --check-prefix=ERROR-V7A < %t %s
|
||||
# RUN: not llvm-mc -disassemble -triple=thumbv7m-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
|
||||
# RUN: | FileCheck --check-prefix=CHECK-V7M %s
|
||||
# RUN: FileCheck --check-prefix=ERROR-V7M < %t %s
|
||||
# RUN: llvm-mc -disassemble -triple=thumbv8a-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
|
||||
# RUN: | FileCheck --check-prefix=CHECK-V8A %s
|
||||
# RUN: FileCheck --check-prefix=ERROR-V8A < %t %s
|
||||
# RUN: not llvm-mc -disassemble -triple=thumbv8m.main-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
|
||||
# RUN: | FileCheck --check-prefix=CHECK-V8M %s
|
||||
# RUN: FileCheck --check-prefix=ERROR-V8M < %t %s
|
||||
# RUN: not llvm-mc -disassemble -triple=thumbv7m-arm-none-eabi -show-encoding < %s 2>%t
|
||||
# RUN: FileCheck --check-prefix=ERROR-NOVFP < %t %s
|
||||
|
||||
[0xf1,0xee,0x10,0xfa]
|
||||
[0xf1,0xee,0x10,0xfa]
|
||||
[0xf1,0xee,0x10,0xfa]
|
||||
[0xf1,0xee,0x10,0xaa]
|
||||
[0xf0,0xee,0x10,0x2a]
|
||||
[0xf0,0xee,0x10,0x3a]
|
||||
[0xf7,0xee,0x10,0x4a]
|
||||
[0xf6,0xee,0x10,0x5a]
|
||||
[0xf5,0xee,0x10,0x6a]
|
||||
[0xf1,0xee,0x10,0xda]
|
||||
|
||||
# CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
|
||||
# CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
|
||||
# CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
|
||||
# CHECK-V7A: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
|
||||
# ERROR-V7A: invalid instruction encoding
|
||||
# ERROR-V7A: invalid instruction encoding
|
||||
# ERROR-V7A: invalid instruction encoding
|
||||
# ERROR-V7A: invalid instruction encoding
|
||||
# ERROR-V7A: invalid instruction encoding
|
||||
# ERROR-V7A: potentially undefined instruction encoding
|
||||
|
||||
# CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
|
||||
# CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
|
||||
# CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
|
||||
# CHECK-V7M: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
|
||||
# ERROR-V7M: invalid instruction encoding
|
||||
# ERROR-V7M: invalid instruction encoding
|
||||
# ERROR-V7M: invalid instruction encoding
|
||||
# ERROR-V7M: invalid instruction encoding
|
||||
# ERROR-V7M: invalid instruction encoding
|
||||
# ERROR-V7M: potentially undefined instruction encoding
|
||||
|
||||
# CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
|
||||
# CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
|
||||
# CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
|
||||
# CHECK-V8A: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
|
||||
# CHECK-V8A: vmrs r2, fpsid @ encoding: [0xf0,0xee,0x10,0x2a]
|
||||
# CHECK-V8A: vmrs r3, fpsid @ encoding: [0xf0,0xee,0x10,0x3a]
|
||||
# CHECK-V8A: vmrs r4, mvfr0 @ encoding: [0xf7,0xee,0x10,0x4a]
|
||||
# CHECK-V8A: vmrs r5, mvfr1 @ encoding: [0xf6,0xee,0x10,0x5a]
|
||||
# CHECK-V8A: vmrs r6, mvfr2 @ encoding: [0xf5,0xee,0x10,0x6a]
|
||||
# CHECK-V8A: vmrs sp, fpscr @ encoding: [0xf1,0xee,0x10,0xda]
|
||||
|
||||
# CHECK-V8M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
|
||||
# CHECK-V8M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
|
||||
# CHECK-V8M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
|
||||
# CHECK-V8M: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
|
||||
# ERROR-V8M: invalid instruction encoding
|
||||
# ERROR-V8M: invalid instruction encoding
|
||||
# ERROR-V8M: invalid instruction encoding
|
||||
# ERROR-V8M: invalid instruction encoding
|
||||
# ERROR-V8M: invalid instruction encoding
|
||||
# ERROR-V8M: potentially undefined instruction encoding
|
||||
|
||||
# ERROR-NOVFP: invalid instruction encoding
|
||||
# ERROR-NOVFP: invalid instruction encoding
|
||||
# ERROR-NOVFP: invalid instruction encoding
|
||||
# ERROR-NOVFP: invalid instruction encoding
|
||||
# ERROR-NOVFP: invalid instruction encoding
|
||||
# ERROR-NOVFP: invalid instruction encoding
|
||||
# ERROR-NOVFP: invalid instruction encoding
|
||||
# ERROR-NOVFP: invalid instruction encoding
|
||||
# ERROR-NOVFP: invalid instruction encoding
|
||||
# ERROR-NOVFP: invalid instruction encoding
|
||||
|
||||
[0xe1,0xee,0x10,0xfa]
|
||||
[0xe1,0xee,0x10,0x0a]
|
||||
[0xe8,0xee,0x10,0x1a]
|
||||
[0xe0,0xee,0x10,0x2a]
|
||||
[0xe1,0xee,0x10,0xaa]
|
||||
[0xe1,0xee,0x10,0xda]
|
||||
|
||||
# ERROR-V7A: potentially undefined instruction encoding
|
||||
# CHECK-V7A: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
|
||||
# ERROR-V7A: invalid instruction encoding
|
||||
# ERROR-V7A: invalid instruction encoding
|
||||
# CHECK-V7A: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
|
||||
# ERROR-V7A: potentially undefined instruction encoding
|
||||
|
||||
# ERROR-V7M: potentially undefined instruction encoding
|
||||
# CHECK-V7M: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
|
||||
# ERROR-V7M: invalid instruction encoding
|
||||
# ERROR-V7M: invalid instruction encoding
|
||||
# CHECK-V7M: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
|
||||
# ERROR-V7M: potentially undefined instruction encoding
|
||||
|
||||
# ERROR-V8A: potentially undefined instruction encoding
|
||||
# CHECK-V8A: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
|
||||
# CHECK-V8A: vmsr fpexc, r1 @ encoding: [0xe8,0xee,0x10,0x1a]
|
||||
# CHECK-V8A: vmsr fpsid, r2 @ encoding: [0xe0,0xee,0x10,0x2a]
|
||||
# CHECK-V8A: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
|
||||
# CHECK-V8A: vmsr fpscr, sp @ encoding: [0xe1,0xee,0x10,0xda]
|
||||
|
||||
# ERROR-V8M: potentially undefined instruction encoding
|
||||
# CHECK-V8M: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
|
||||
# ERROR-V8M: invalid instruction encoding
|
||||
# ERROR-V8M: invalid instruction encoding
|
||||
# CHECK-V8M: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
|
||||
# ERROR-V8M: potentially undefined instruction encoding
|
||||
|
||||
# ERROR-NOVFP: invalid instruction encoding
|
||||
# ERROR-NOVFP: invalid instruction encoding
|
||||
# ERROR-NOVFP: invalid instruction encoding
|
||||
# ERROR-NOVFP: invalid instruction encoding
|
||||
# ERROR-NOVFP: invalid instruction encoding
|
||||
# ERROR-NOVFP: invalid instruction encoding
|
||||
|
||||
Loading…
Reference in New Issue