forked from OSchip/llvm-project
[mips] For the FP64A ABI, odd-numbered double-precision moves must not use mtc1/mfc1.
Summary: This is because the FP64A the hardware will redirect 32-bit reads/writes from/to odd-numbered registers to the upper 32-bits of the corresponding even register. In effect, simulating FR=0 mode when FR=0 mode is not available. Unfortunately, we have to make the decision to avoid mfc1/mtc1 before register allocation so we currently do this for even registers too. FPXX has a similar requirement on 32-bit architectures that lack mfhc1/mthc1 so this patch also handles the affected moves from the FPU for FPXX too. Moves to the FPU were supported by an earlier commit. Differential Revision: http://reviews.llvm.org/D4484 llvm-svn: 212938
This commit is contained in:
Daniel Sanders
parent
d73e7cc879
commit
7ddb0ab85f
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@ -137,12 +137,12 @@ MachinePointerInfo MipsFunctionInfo::callPtrInfo(const GlobalValue *Val) {
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return MachinePointerInfo(E);
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}
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int MipsFunctionInfo::getBuildPairF64_FI(const TargetRegisterClass *RC) {
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if (BuildPairF64_FI == -1) {
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BuildPairF64_FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
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RC->getAlignment(), false);
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int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) {
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if (MoveF64ViaSpillFI == -1) {
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MoveF64ViaSpillFI = MF.getFrameInfo()->CreateStackObject(
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RC->getSize(), RC->getAlignment(), false);
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}
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return BuildPairF64_FI;
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return MoveF64ViaSpillFI;
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}
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void MipsFunctionInfo::anchor() { }
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@ -55,7 +55,7 @@ public:
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MipsFunctionInfo(MachineFunction &MF)
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: MF(MF), SRetReturnReg(0), GlobalBaseReg(0), Mips16SPAliasReg(0),
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VarArgsFrameIndex(0), CallsEhReturn(false), SaveS2(false),
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BuildPairF64_FI(-1) {}
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MoveF64ViaSpillFI(-1) {}
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~MipsFunctionInfo();
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@ -97,7 +97,7 @@ public:
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void setSaveS2() { SaveS2 = true; }
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bool hasSaveS2() const { return SaveS2; }
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int getBuildPairF64_FI(const TargetRegisterClass *RC);
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int getMoveF64ViaSpillFI(const TargetRegisterClass *RC);
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std::map<const char *, const llvm::Mips16HardFloatInfo::FuncSignature *>
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StubsNeeded;
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@ -141,7 +141,7 @@ private:
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/// FrameIndex for expanding BuildPairF64 nodes to spill and reload when the
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/// O32 FPXX ABI is enabled. -1 is used to denote invalid index.
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int BuildPairF64_FI;
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int MoveF64ViaSpillFI;
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/// MipsCallEntry maps.
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StringMap<const MipsCallEntry *> ExternalCallEntries;
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@ -66,6 +66,8 @@ private:
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unsigned MFLoOpc);
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bool expandBuildPairF64(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, bool FP64) const;
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bool expandExtractElementF64(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, bool FP64) const;
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MachineFunction &MF;
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MachineRegisterInfo &MRI;
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@ -118,6 +120,14 @@ bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
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if (expandBuildPairF64(MBB, I, true))
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MBB.erase(I);
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return false;
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case Mips::ExtractElementF64:
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if (expandExtractElementF64(MBB, I, false))
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MBB.erase(I);
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return false;
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case Mips::ExtractElementF64_64:
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if (expandExtractElementF64(MBB, I, true))
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MBB.erase(I);
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return false;
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case TargetOpcode::COPY:
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if (!expandCopy(MBB, I))
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return false;
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@ -269,9 +279,10 @@ bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I,
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}
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/// This method expands the same instruction that MipsSEInstrInfo::
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/// expandBuildPairF64 does, for the case when ABI is fpxx and mthc1 is
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/// not available. It is implemented here because frame indexes are
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/// eliminated before MipsSEInstrInfo::expandBuildPairF64 is called.
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/// expandBuildPairF64 does, for the case when ABI is fpxx and mthc1 is not
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/// available and the case where the ABI is FP64A. It is implemented here
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/// because frame indexes are eliminated before MipsSEInstrInfo::
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/// expandBuildPairF64 is called.
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bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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bool FP64) const {
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@ -280,10 +291,18 @@ bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB,
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//
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// The case where dmtc1 is available doesn't need to be handled here
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// because it never creates a BuildPairF64 node.
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//
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// The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence
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// for odd-numbered double precision values (because the lower 32-bits is
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// transferred with mtc1 which is redirected to the upper half of the even
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// register). Unfortunately, we have to make this decision before register
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// allocation so for now we use a spill/reload sequence for all
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// double-precision values in regardless of being an odd/even register.
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const TargetMachine &TM = MF.getTarget();
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if (TM.getSubtarget<MipsSubtarget>().isABI_FPXX()
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&& !TM.getSubtarget<MipsSubtarget>().hasMTHC1()) {
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const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
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if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) ||
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(FP64 && !Subtarget.useOddSPReg())) {
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const MipsSEInstrInfo &TII =
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*static_cast<const MipsSEInstrInfo*>(TM.getInstrInfo());
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const MipsRegisterInfo &TRI =
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@ -294,13 +313,18 @@ bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB,
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unsigned HiReg = I->getOperand(2).getReg();
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// It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
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// the cases where mthc1 is not available).
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assert(!TM.getSubtarget<MipsSubtarget>().isFP64bit());
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// the cases where mthc1 is not available). 64-bit architectures and
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// MIPS32r2 or later can use FGR64 though.
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assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() ||
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!Subtarget.isFP64bit());
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const TargetRegisterClass *RC = &Mips::GPR32RegClass;
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const TargetRegisterClass *RC2 = &Mips::AFGR64RegClass;
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const TargetRegisterClass *RC2 =
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FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
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int FI = MF.getInfo<MipsFunctionInfo>()->getBuildPairF64_FI(RC2);
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// We re-use the same spill slot each time so that the stack frame doesn't
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// grow too much in functions with a large number of moves.
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int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC2);
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TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, &TRI,
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0);
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TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, &TRI,
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@ -312,6 +336,62 @@ bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB,
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return false;
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}
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/// This method expands the same instruction that MipsSEInstrInfo::
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/// expandExtractElementF64 does, for the case when ABI is fpxx and mfhc1 is not
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/// available and the case where the ABI is FP64A. It is implemented here
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/// because frame indexes are eliminated before MipsSEInstrInfo::
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/// expandExtractElementF64 is called.
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bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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bool FP64) const {
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// For fpxx and when mfhc1 is not available, use:
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// spill + reload via ldc1
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//
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// The case where dmfc1 is available doesn't need to be handled here
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// because it never creates a ExtractElementF64 node.
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//
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// The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence
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// for odd-numbered double precision values (because the lower 32-bits is
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// transferred with mfc1 which is redirected to the upper half of the even
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// register). Unfortunately, we have to make this decision before register
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// allocation so for now we use a spill/reload sequence for all
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// double-precision values in regardless of being an odd/even register.
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const TargetMachine &TM = MF.getTarget();
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const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
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if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) ||
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(FP64 && !Subtarget.useOddSPReg())) {
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const MipsSEInstrInfo &TII =
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*static_cast<const MipsSEInstrInfo *>(TM.getInstrInfo());
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const MipsRegisterInfo &TRI =
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*static_cast<const MipsRegisterInfo *>(TM.getRegisterInfo());
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unsigned DstReg = I->getOperand(0).getReg();
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unsigned SrcReg = I->getOperand(1).getReg();
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unsigned N = I->getOperand(2).getImm();
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// It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
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// the cases where mfhc1 is not available). 64-bit architectures and
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// MIPS32r2 or later can use FGR64 though.
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assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() ||
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!Subtarget.isFP64bit());
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const TargetRegisterClass *RC =
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FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
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const TargetRegisterClass *RC2 = &Mips::GPR32RegClass;
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// We re-use the same spill slot each time so that the stack frame doesn't
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// grow too much in functions with a large number of moves.
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int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC);
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TII.storeRegToStack(MBB, I, SrcReg, I->getOperand(1).isKill(), FI, RC, &TRI,
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0);
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TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &TRI, N * 4);
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return true;
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}
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return false;
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}
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MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI)
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: MipsFrameLowering(STI, STI.stackAlignment()) {}
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@ -512,6 +512,7 @@ void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
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void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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bool FP64) const {
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const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
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unsigned DstReg = I->getOperand(0).getReg();
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unsigned SrcReg = I->getOperand(1).getReg();
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unsigned N = I->getOperand(2).getImm();
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@ -521,7 +522,15 @@ void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
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unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
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unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
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if (SubIdx == Mips::sub_hi && TM.getSubtarget<MipsSubtarget>().hasMTHC1()) {
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// FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
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// in MipsSEFrameLowering.cpp.
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assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
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// FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
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// in MipsSEFrameLowering.cpp.
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assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
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if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) {
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// FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we
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// claim to read the whole 64-bits as part of a white lie used to
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// temporarily work around a widespread bug in the -mfp64 support.
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@ -543,6 +552,7 @@ void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
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void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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bool FP64) const {
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const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
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unsigned DstReg = I->getOperand(0).getReg();
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unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
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const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
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@ -564,10 +574,18 @@ void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
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// The case where dmtc1 is available doesn't need to be handled here
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// because it never creates a BuildPairF64 node.
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// FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
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// in MipsSEFrameLowering.cpp.
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assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
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// FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
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// in MipsSEFrameLowering.cpp.
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assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
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BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
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.addReg(LoReg);
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if (TM.getSubtarget<MipsSubtarget>().hasMTHC1()) {
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if (Subtarget.hasMTHC1()) {
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// FIXME: The .addReg(DstReg) is a white lie used to temporarily work
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// around a widespread bug in the -mfp64 support.
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// The problem is that none of the 32-bit fpu ops mention the fact
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@ -582,7 +600,7 @@ void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
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BuildMI(MBB, I, dl, get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg)
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.addReg(DstReg)
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.addReg(HiReg);
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} else if (TM.getSubtarget<MipsSubtarget>().isABI_FPXX())
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} else if (Subtarget.isABI_FPXX())
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llvm_unreachable("BuildPairF64 not expanded in frame lowering code!");
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else
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BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
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@ -153,9 +153,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
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false);
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if (!isABI_O32() && !useOddSPReg())
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report_fatal_error("-mattr=+nooddspreg is not currently permitted for a "
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"the O32 ABI.",
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false);
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report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
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if (IsFPXX && (isABI_N32() || isABI_N64()))
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report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
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@ -0,0 +1,197 @@
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; Test that the FP64A ABI performs double precision moves via a spill/reload.
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; The requirement is really that odd-numbered double precision registers do not
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; use mfc1/mtc1 to move the bottom 32-bits (because the hardware will redirect
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; this to the top 32-bits of the even register) but we have to make the decision
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; before register allocation so we do this for all double-precision values.
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; We don't test MIPS32r1 since support for 64-bit coprocessors (such as a 64-bit
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; FPU) on a 32-bit architecture was added in MIPS32r2.
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; FIXME: We currently don't test that attempting to use FP64 on MIPS32r1 is an
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; error either. This is because a large number of CodeGen tests are
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; incorrectly using this case. We should fix those test cases then add
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; this check here.
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; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-NO-FP64A-BE
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; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-FP64A-BE
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; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-NO-FP64A-LE
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; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-FP64A-LE
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; RUN: llc -march=mips64 -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-NO-FP64A
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; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A
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; RUN: llc -march=mips64el -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-NO-FP64A
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; RUN: not llc -march=mips64el -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A
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; 64-FP64A: LLVM ERROR: -mattr=+nooddspreg requires the O32 ABI.
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declare double @dbl();
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define double @call1(double %d, ...) {
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ret double %d
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; ALL-LABEL: call1:
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; 32R2-NO-FP64A-LE-NOT: addiu $sp, $sp
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; 32R2-NO-FP64A-LE: mtc1 $4, $f0
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; 32R2-NO-FP64A-LE: mthc1 $5, $f0
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; 32R2-NO-FP64A-BE-NOT: addiu $sp, $sp
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; 32R2-NO-FP64A-BE: mtc1 $5, $f0
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; 32R2-NO-FP64A-BE: mthc1 $4, $f0
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; 32R2-FP64A-LE: addiu $sp, $sp, -8
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; 32R2-FP64A-LE: sw $4, 0($sp)
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; 32R2-FP64A-LE: sw $5, 4($sp)
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; 32R2-FP64A-LE: ldc1 $f0, 0($sp)
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; 32R2-FP64A-BE: addiu $sp, $sp, -8
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; 32R2-FP64A-BE: sw $5, 0($sp)
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; 32R2-FP64A-BE: sw $4, 4($sp)
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; 32R2-FP64A-BE: ldc1 $f0, 0($sp)
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; 64-NO-FP64A: daddiu $sp, $sp, -64
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; 64-NO-FP64A: mov.d $f0, $f12
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}
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define double @call2(i32 %i, double %d) {
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ret double %d
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; ALL-LABEL: call2:
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; 32R2-NO-FP64A-LE: mtc1 $6, $f0
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; 32R2-NO-FP64A-LE: mthc1 $7, $f0
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; 32R2-NO-FP64A-BE: mtc1 $7, $f0
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; 32R2-NO-FP64A-BE: mthc1 $6, $f0
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; 32R2-FP64A-LE: addiu $sp, $sp, -8
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; 32R2-FP64A-LE: sw $6, 0($sp)
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; 32R2-FP64A-LE: sw $7, 4($sp)
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; 32R2-FP64A-LE: ldc1 $f0, 0($sp)
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; 32R2-FP64A-BE: addiu $sp, $sp, -8
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; 32R2-FP64A-BE: sw $7, 0($sp)
|
||||
; 32R2-FP64A-BE: sw $6, 4($sp)
|
||||
; 32R2-FP64A-BE: ldc1 $f0, 0($sp)
|
||||
|
||||
; 64-NO-FP64A-NOT: daddiu $sp, $sp
|
||||
; 64-NO-FP64A: mov.d $f0, $f13
|
||||
}
|
||||
|
||||
define double @call3(float %f1, float %f2, double %d) {
|
||||
ret double %d
|
||||
|
||||
; ALL-LABEL: call3:
|
||||
|
||||
; 32R2-NO-FP64A-LE: mtc1 $6, $f0
|
||||
; 32R2-NO-FP64A-LE: mthc1 $7, $f0
|
||||
|
||||
; 32R2-NO-FP64A-BE: mtc1 $7, $f0
|
||||
; 32R2-NO-FP64A-BE: mthc1 $6, $f0
|
||||
|
||||
; 32R2-FP64A-LE: addiu $sp, $sp, -8
|
||||
; 32R2-FP64A-LE: sw $6, 0($sp)
|
||||
; 32R2-FP64A-LE: sw $7, 4($sp)
|
||||
; 32R2-FP64A-LE: ldc1 $f0, 0($sp)
|
||||
|
||||
; 32R2-FP64A-BE: addiu $sp, $sp, -8
|
||||
; 32R2-FP64A-BE: sw $7, 0($sp)
|
||||
; 32R2-FP64A-BE: sw $6, 4($sp)
|
||||
; 32R2-FP64A-BE: ldc1 $f0, 0($sp)
|
||||
|
||||
; 64-NO-FP64A-NOT: daddiu $sp, $sp
|
||||
; 64-NO-FP64A: mov.d $f0, $f14
|
||||
}
|
||||
|
||||
define double @call4(float %f, double %d, ...) {
|
||||
ret double %d
|
||||
|
||||
; ALL-LABEL: call4:
|
||||
|
||||
; 32R2-NO-FP64A-LE: mtc1 $6, $f0
|
||||
; 32R2-NO-FP64A-LE: mthc1 $7, $f0
|
||||
|
||||
; 32R2-NO-FP64A-BE: mtc1 $7, $f0
|
||||
; 32R2-NO-FP64A-BE: mthc1 $6, $f0
|
||||
|
||||
; 32R2-FP64A-LE: addiu $sp, $sp, -8
|
||||
; 32R2-FP64A-LE: sw $6, 0($sp)
|
||||
; 32R2-FP64A-LE: sw $7, 4($sp)
|
||||
; 32R2-FP64A-LE: ldc1 $f0, 0($sp)
|
||||
|
||||
; 32R2-FP64A-BE: addiu $sp, $sp, -8
|
||||
; 32R2-FP64A-BE: sw $7, 0($sp)
|
||||
; 32R2-FP64A-BE: sw $6, 4($sp)
|
||||
; 32R2-FP64A-BE: ldc1 $f0, 0($sp)
|
||||
|
||||
; 64-NO-FP64A: daddiu $sp, $sp, -48
|
||||
; 64-NO-FP64A: mov.d $f0, $f13
|
||||
}
|
||||
|
||||
define double @call5(double %a, double %b, ...) {
|
||||
%1 = fsub double %a, %b
|
||||
ret double %1
|
||||
|
||||
; ALL-LABEL: call5:
|
||||
|
||||
; 32R2-NO-FP64A-LE-DAG: mtc1 $4, $[[T0:f[0-9]+]]
|
||||
; 32R2-NO-FP64A-LE-DAG: mthc1 $5, $[[T0:f[0-9]+]]
|
||||
; 32R2-NO-FP64A-LE-DAG: mtc1 $6, $[[T1:f[0-9]+]]
|
||||
; 32R2-NO-FP64A-LE-DAG: mthc1 $7, $[[T1:f[0-9]+]]
|
||||
; 32R2-NO-FP64A-LE: sub.d $f0, $[[T0]], $[[T1]]
|
||||
|
||||
; 32R2-NO-FP64A-BE-DAG: mtc1 $5, $[[T0:f[0-9]+]]
|
||||
; 32R2-NO-FP64A-BE-DAG: mthc1 $4, $[[T0:f[0-9]+]]
|
||||
; 32R2-NO-FP64A-BE-DAG: mtc1 $7, $[[T1:f[0-9]+]]
|
||||
; 32R2-NO-FP64A-BE-DAG: mthc1 $6, $[[T1:f[0-9]+]]
|
||||
; 32R2-NO-FP64A-BE: sub.d $f0, $[[T0]], $[[T1]]
|
||||
|
||||
; 32R2-FP64A-LE: addiu $sp, $sp, -8
|
||||
; 32R2-FP64A-LE: sw $6, 0($sp)
|
||||
; 32R2-FP64A-LE: sw $7, 4($sp)
|
||||
; 32R2-FP64A-LE: ldc1 $[[T1:f[0-9]+]], 0($sp)
|
||||
; 32R2-FP64A-LE: sw $4, 0($sp)
|
||||
; 32R2-FP64A-LE: sw $5, 4($sp)
|
||||
; 32R2-FP64A-LE: ldc1 $[[T0:f[0-9]+]], 0($sp)
|
||||
; 32R2-FP64A-LE: sub.d $f0, $[[T0]], $[[T1]]
|
||||
|
||||
; 32R2-FP64A-BE: addiu $sp, $sp, -8
|
||||
; 32R2-FP64A-BE: sw $7, 0($sp)
|
||||
; 32R2-FP64A-BE: sw $6, 4($sp)
|
||||
; 32R2-FP64A-BE: ldc1 $[[T1:f[0-9]+]], 0($sp)
|
||||
; 32R2-FP64A-BE: sw $5, 0($sp)
|
||||
; 32R2-FP64A-BE: sw $4, 4($sp)
|
||||
; 32R2-FP64A-BE: ldc1 $[[T0:f[0-9]+]], 0($sp)
|
||||
; 32R2-FP64A-BE: sub.d $f0, $[[T0]], $[[T1]]
|
||||
|
||||
; 64-NO-FP64A: sub.d $f0, $f12, $f13
|
||||
}
|
||||
|
||||
define double @move_from(double %d) {
|
||||
%1 = call double @dbl()
|
||||
%2 = call double @call2(i32 0, double %1)
|
||||
ret double %2
|
||||
|
||||
; ALL-LABEL: move_from:
|
||||
|
||||
; 32R2-NO-FP64A-LE-DAG: mfc1 $6, $f0
|
||||
; 32R2-NO-FP64A-LE-DAG: mfhc1 $7, $f0
|
||||
|
||||
; 32R2-NO-FP64A-BE-DAG: mfc1 $7, $f0
|
||||
; 32R2-NO-FP64A-BE-DAG: mfhc1 $6, $f0
|
||||
|
||||
; 32R2-FP64A-LE: addiu $sp, $sp, -32
|
||||
; 32R2-FP64A-LE: sdc1 $f0, 16($sp)
|
||||
; 32R2-FP64A-LE: lw $6, 16($sp)
|
||||
; FIXME: This store is redundant
|
||||
; 32R2-FP64A-LE: sdc1 $f0, 16($sp)
|
||||
; 32R2-FP64A-LE: lw $7, 20($sp)
|
||||
|
||||
; 32R2-FP64A-BE: addiu $sp, $sp, -32
|
||||
; 32R2-FP64A-BE: sdc1 $f0, 16($sp)
|
||||
; 32R2-FP64A-BE: lw $6, 20($sp)
|
||||
; FIXME: This store is redundant
|
||||
; 32R2-FP64A-BE: sdc1 $f0, 16($sp)
|
||||
; 32R2-FP64A-BE: lw $7, 16($sp)
|
||||
|
||||
; 64-NO-FP64A: mov.d $f13, $f0
|
||||
}
|
||||
|
|
@ -11,11 +11,12 @@
|
|||
; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=64-FPXX
|
||||
|
||||
; RUN-TODO: llc -march=mips64 -mcpu=mips4 -mattr=-n64,+o32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=4-O32-NOFPXX
|
||||
; RUN-TOOD: llc -march=mips64 -mcpu=mips4 -mattr=-n64,+o32 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=4-O32-FPXX
|
||||
; RUN-TODO: llc -march=mips64 -mcpu=mips4 -mattr=-n64,+o32 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=4-O32-FPXX
|
||||
|
||||
; RUN-TODO: llc -march=mips64 -mcpu=mips64 -mattr=-n64,+o32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-O32-NOFPXX
|
||||
; RUN-TOOD: llc -march=mips64 -mcpu=mips64 -mattr=-n64,+o32 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-O32-FPXX
|
||||
; RUN-TODO: llc -march=mips64 -mcpu=mips64 -mattr=-n64,+o32 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-O32-FPXX
|
||||
|
||||
declare double @dbl();
|
||||
|
||||
; 4-FPXX: LLVM ERROR: FPXX is not permitted for the N32/N64 ABI's.
|
||||
; 64-FPXX: LLVM ERROR: FPXX is not permitted for the N32/N64 ABI's.
|
||||
|
|
@ -140,3 +141,81 @@ define double @test5() {
|
|||
|
||||
; 64-NOFPXX: dmtc1 $zero, $f0
|
||||
}
|
||||
|
||||
define double @test6(double %a, double %b, ...) {
|
||||
%1 = fsub double %a, %b
|
||||
ret double %1
|
||||
|
||||
; ALL-LABEL: test6:
|
||||
|
||||
; 32-NOFPXX-DAG: mtc1 $4, $[[T0:f[0-9]+]]
|
||||
; 32-NOFPXX-DAG: mtc1 $5, ${{f[0-9]*[13579]}}
|
||||
; 32-NOFPXX-DAG: mtc1 $6, $[[T1:f[0-9]+]]
|
||||
; 32-NOFPXX-DAG: mtc1 $7, ${{f[0-9]*[13579]}}
|
||||
; 32-NOFPXX: sub.d $f0, $[[T0]], $[[T1]]
|
||||
|
||||
; 32-FPXX: addiu $sp, $sp, -8
|
||||
; 32-FPXX: sw $6, 0($sp)
|
||||
; 32-FPXX: sw $7, 4($sp)
|
||||
; 32-FPXX: ldc1 $[[T1:f[0-9]+]], 0($sp)
|
||||
; 32-FPXX: sw $4, 0($sp)
|
||||
; 32-FPXX: sw $5, 4($sp)
|
||||
; 32-FPXX: ldc1 $[[T0:f[0-9]+]], 0($sp)
|
||||
; 32-FPXX: sub.d $f0, $[[T0]], $[[T1]]
|
||||
|
||||
; 32R2-NOFPXX-DAG: mtc1 $4, $[[T0:f[0-9]+]]
|
||||
; 32R2-NOFPXX-DAG: mthc1 $5, $[[T0]]
|
||||
; 32R2-NOFPXX-DAG: mtc1 $6, $[[T1:f[0-9]+]]
|
||||
; 32R2-NOFPXX-DAG: mthc1 $7, $[[T1]]
|
||||
; 32R2-NOFPXX: sub.d $f0, $[[T0]], $[[T1]]
|
||||
|
||||
; 32R2-FPXX-DAG: mtc1 $4, $[[T0:f[0-9]+]]
|
||||
; 32R2-FPXX-DAG: mthc1 $5, $[[T0]]
|
||||
; 32R2-FPXX-DAG: mtc1 $6, $[[T1:f[0-9]+]]
|
||||
; 32R2-FPXX-DAG: mthc1 $7, $[[T1]]
|
||||
; 32R2-FPXX: sub.d $f0, $[[T0]], $[[T1]]
|
||||
|
||||
; floats/doubles are not passed in integer registers for n64, so dmtc1 is not used.
|
||||
; 4-NOFPXX: sub.d $f0, $f12, $f13
|
||||
|
||||
; floats/doubles are not passed in integer registers for n64, so dmtc1 is not used.
|
||||
; 64-NOFPXX: sub.d $f0, $f12, $f13
|
||||
}
|
||||
|
||||
define double @move_from1(double %d) {
|
||||
%1 = call double @dbl()
|
||||
%2 = call double @test2(i32 0, double %1)
|
||||
ret double %2
|
||||
|
||||
; ALL-LABEL: move_from1:
|
||||
|
||||
; 32-NOFPXX-DAG: mfc1 $6, $f0
|
||||
; 32-NOFPXX-DAG: mfc1 $7, $f1
|
||||
|
||||
; 32-FPXX: addiu $sp, $sp, -32
|
||||
; 32-FPXX: sdc1 $f0, 16($sp)
|
||||
; 32-FPXX: lw $6, 16($sp)
|
||||
; FIXME: This store is redundant
|
||||
; 32-FPXX: sdc1 $f0, 16($sp)
|
||||
; 32-FPXX: lw $7, 20($sp)
|
||||
|
||||
; 32R2-NOFPXX-DAG: mfc1 $6, $f0
|
||||
; 32R2-NOFPXX-DAG: mfhc1 $7, $f0
|
||||
|
||||
; 32R2-FPXX-DAG: mfc1 $6, $f0
|
||||
; 32R2-FPXX-DAG: mfhc1 $7, $f0
|
||||
|
||||
; floats/doubles are not passed in integer registers for n64, so dmfc1 is not used.
|
||||
; We can't use inline assembly to force a copy either because trying to force
|
||||
; a copy to a GPR this way fails with ; "couldn't allocate input reg for
|
||||
; constraint 'r'". It therefore seems impossible to test the generation of dmfc1
|
||||
; in a simple test.
|
||||
; 4-NOFPXX: mov.d $f13, $f0
|
||||
|
||||
; floats/doubles are not passed in integer registers for n64, so dmfc1 is not used.
|
||||
; We can't use inline assembly to force a copy either because trying to force
|
||||
; a copy to a GPR this way fails with ; "couldn't allocate input reg for
|
||||
; constraint 'r'". It therefore seems impossible to test the generation of dmfc1
|
||||
; in a simple test.
|
||||
; 64-NOFPXX: mov.d $f13, $f0
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue