Add encodings for VNMUL[SD].

llvm-svn: 116375
This commit is contained in:
Bill Wendling 2010-10-12 23:47:37 +00:00
parent da349bab8a
commit 7dd8c0b991
2 changed files with 27 additions and 6 deletions

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@ -239,13 +239,15 @@ def VMULS : ASbIn_Encode<0b11100, 0b10, 0, 0,
IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm", IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
[(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]>; [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]>;
def VNMULD : ADbI<0b11100, 0b10, 1, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b), def VNMULD : ADbI_Encode<0b11100, 0b10, 1, 0,
IIC_fpMUL64, "vnmul", ".f64\t$dst, $a, $b", (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
[(set DPR:$dst, (fneg (fmul DPR:$a, (f64 DPR:$b))))]>; IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
[(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
def VNMULS : ASbI<0b11100, 0b10, 1, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b), def VNMULS : ASbI_Encode<0b11100, 0b10, 1, 0,
IIC_fpMUL32, "vnmul", ".f32\t$dst, $a, $b", (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
[(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]>; IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
[(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]>;
// Match reassociated forms only if not sign dependent rounding. // Match reassociated forms only if not sign dependent rounding.
def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)), def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),

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@ -70,6 +70,25 @@ entry:
ret float %mul ret float %mul
} }
define double @f9(double %a, double %b) nounwind readnone {
entry:
; CHECK: f9
; CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee]
%mul = fmul double %a, %b
%sub = fsub double -0.000000e+00, %mul
ret double %sub
}
define void @f10(float %a, float %b, float* %c) nounwind readnone {
entry:
; CHECK: f10
; CHECK: vnmul.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x20,0xee]
%mul = fmul float %a, %b
%sub = fsub float -0.000000e+00, %mul
store float %sub, float* %c, align 4
ret void
}
define i1 @f100(double %a, double %b) nounwind readnone { define i1 @f100(double %a, double %b) nounwind readnone {
entry: entry:
; CHECK: f100 ; CHECK: f100