forked from OSchip/llvm-project
Swap the operands of a select node if the false (the second) operand is 0.
For example, this pattern (select (setcc lhs, rhs, cc), true, 0) is transformed to this one: (select (setcc lhs, rhs, inverse(cc)), 0, true) This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to replace 0 with $zero. llvm-svn: 152285
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@ -576,6 +576,39 @@ static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG,
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return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc());
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}
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static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG& DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const MipsSubtarget* Subtarget) {
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if (DCI.isBeforeLegalizeOps())
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return SDValue();
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SDValue SetCC = N->getOperand(0);
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if ((SetCC.getOpcode() != ISD::SETCC) ||
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!SetCC.getOperand(0).getValueType().isInteger())
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return SDValue();
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SDValue False = N->getOperand(2);
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EVT FalseTy = False.getValueType();
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if (!FalseTy.isInteger())
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return SDValue();
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
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if (!CN || CN->getZExtValue())
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return SDValue();
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const DebugLoc DL = N->getDebugLoc();
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ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
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SDValue True = N->getOperand(1);
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SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
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SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
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return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
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}
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static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const MipsSubtarget* Subtarget) {
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@ -686,6 +719,8 @@ SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
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return PerformDivRemCombine(N, DAG, DCI, Subtarget);
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case ISD::SETCC:
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return PerformSETCCCombine(N, DAG, DCI, Subtarget);
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case ISD::SELECT:
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return PerformSELECTCombine(N, DAG, DCI, Subtarget);
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case ISD::AND:
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return PerformANDCombine(N, DAG, DCI, Subtarget);
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case ISD::OR:
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