Don't add implicit regs

llvm-svn: 4840
2002-12-01 23:24:58 +00:00 · 2002-12-01 23:24:58 +00:00 · 7dcb1436da
parent 2ad3501d3f
commit 7dcb1436da
1 changed files with 1 additions and 1 deletions
--- a/llvm/lib/Target/X86/InstSelectSimple.cpp
+++ b/llvm/lib/Target/X86/InstSelectSimple.cpp
@ -502,7 +502,7 @@ void ISel::visitDivRem(BinaryOperator &I) {

  if (isSigned) {
    // Emit a sign extension instruction...
-    BuildMI(BB, ExtOpcode[Class], 1, ExtReg).addReg(Reg);
+    BuildMI(BB, ExtOpcode[Class], 0);
  } else {
    // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
    BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);