forked from OSchip/llvm-project
[AArch64] Refactor identification of SIMD immediates
Get rid of icky goto loops and make the code easier to maintain (NFC). Differential revision: https://reviews.llvm.org/D42723 llvm-svn: 324903
This commit is contained in:
Evandro Menezes
parent
cfd451b746
commit
7dc0f1ec45
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@ -6234,96 +6234,235 @@ static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
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return false;
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}
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// Try 64-bit splatted SIMD immediate.
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static SDValue tryAdvSIMDModImm64(unsigned NewOp, SDValue Op, SelectionDAG &DAG,
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const APInt &Bits) {
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if (Bits.getHiBits(64) == Bits.getLoBits(64)) {
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uint64_t Value = Bits.zextOrTrunc(64).getZExtValue();
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EVT VT = Op.getValueType();
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MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v2i64 : MVT::f64;
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if (AArch64_AM::isAdvSIMDModImmType10(Value)) {
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Value = AArch64_AM::encodeAdvSIMDModImmType10(Value);
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SDLoc dl(Op);
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SDValue Mov = DAG.getNode(NewOp, dl, MovTy,
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DAG.getConstant(Value, dl, MVT::i32));
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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}
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return SDValue();
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}
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// Try 32-bit splatted SIMD immediate.
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static SDValue tryAdvSIMDModImm32(unsigned NewOp, SDValue Op, SelectionDAG &DAG,
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const APInt &Bits,
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const SDValue *LHS = nullptr) {
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if (Bits.getHiBits(64) == Bits.getLoBits(64)) {
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uint64_t Value = Bits.zextOrTrunc(64).getZExtValue();
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EVT VT = Op.getValueType();
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MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
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bool isAdvSIMDModImm = false;
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uint64_t Shift;
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if ((isAdvSIMDModImm = AArch64_AM::isAdvSIMDModImmType1(Value))) {
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Value = AArch64_AM::encodeAdvSIMDModImmType1(Value);
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Shift = 0;
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}
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else if ((isAdvSIMDModImm = AArch64_AM::isAdvSIMDModImmType2(Value))) {
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Value = AArch64_AM::encodeAdvSIMDModImmType2(Value);
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Shift = 8;
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}
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else if ((isAdvSIMDModImm = AArch64_AM::isAdvSIMDModImmType3(Value))) {
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Value = AArch64_AM::encodeAdvSIMDModImmType3(Value);
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Shift = 16;
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}
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else if ((isAdvSIMDModImm = AArch64_AM::isAdvSIMDModImmType4(Value))) {
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Value = AArch64_AM::encodeAdvSIMDModImmType4(Value);
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Shift = 24;
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}
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if (isAdvSIMDModImm) {
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SDLoc dl(Op);
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SDValue Mov;
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if (LHS)
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Mov = DAG.getNode(NewOp, dl, MovTy, *LHS,
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DAG.getConstant(Value, dl, MVT::i32),
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DAG.getConstant(Shift, dl, MVT::i32));
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else
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Mov = DAG.getNode(NewOp, dl, MovTy,
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DAG.getConstant(Value, dl, MVT::i32),
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DAG.getConstant(Shift, dl, MVT::i32));
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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}
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return SDValue();
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}
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// Try 16-bit splatted SIMD immediate.
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static SDValue tryAdvSIMDModImm16(unsigned NewOp, SDValue Op, SelectionDAG &DAG,
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const APInt &Bits,
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const SDValue *LHS = nullptr) {
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if (Bits.getHiBits(64) == Bits.getLoBits(64)) {
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uint64_t Value = Bits.zextOrTrunc(64).getZExtValue();
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EVT VT = Op.getValueType();
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MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
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bool isAdvSIMDModImm = false;
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uint64_t Shift;
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if ((isAdvSIMDModImm = AArch64_AM::isAdvSIMDModImmType5(Value))) {
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Value = AArch64_AM::encodeAdvSIMDModImmType5(Value);
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Shift = 0;
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}
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else if ((isAdvSIMDModImm = AArch64_AM::isAdvSIMDModImmType6(Value))) {
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Value = AArch64_AM::encodeAdvSIMDModImmType6(Value);
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Shift = 8;
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}
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if (isAdvSIMDModImm) {
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SDLoc dl(Op);
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SDValue Mov;
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if (LHS)
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Mov = DAG.getNode(NewOp, dl, MovTy, *LHS,
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DAG.getConstant(Value, dl, MVT::i32),
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DAG.getConstant(Shift, dl, MVT::i32));
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else
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Mov = DAG.getNode(NewOp, dl, MovTy,
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DAG.getConstant(Value, dl, MVT::i32),
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DAG.getConstant(Shift, dl, MVT::i32));
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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}
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return SDValue();
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}
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// Try 32-bit splatted SIMD immediate with shifted ones.
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static SDValue tryAdvSIMDModImm321s(unsigned NewOp, SDValue Op,
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SelectionDAG &DAG, const APInt &Bits) {
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if (Bits.getHiBits(64) == Bits.getLoBits(64)) {
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uint64_t Value = Bits.zextOrTrunc(64).getZExtValue();
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EVT VT = Op.getValueType();
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MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
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bool isAdvSIMDModImm = false;
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uint64_t Shift;
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if ((isAdvSIMDModImm = AArch64_AM::isAdvSIMDModImmType7(Value))) {
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Value = AArch64_AM::encodeAdvSIMDModImmType7(Value);
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Shift = 264;
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}
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else if ((isAdvSIMDModImm = AArch64_AM::isAdvSIMDModImmType8(Value))) {
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Value = AArch64_AM::encodeAdvSIMDModImmType8(Value);
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Shift = 272;
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}
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if (isAdvSIMDModImm) {
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SDLoc dl(Op);
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SDValue Mov = DAG.getNode(NewOp, dl, MovTy,
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DAG.getConstant(Value, dl, MVT::i32),
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DAG.getConstant(Shift, dl, MVT::i32));
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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}
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return SDValue();
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}
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// Try 8-bit splatted SIMD immediate.
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static SDValue tryAdvSIMDModImm8(unsigned NewOp, SDValue Op, SelectionDAG &DAG,
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const APInt &Bits) {
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if (Bits.getHiBits(64) == Bits.getLoBits(64)) {
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uint64_t Value = Bits.zextOrTrunc(64).getZExtValue();
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EVT VT = Op.getValueType();
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MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
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if (AArch64_AM::isAdvSIMDModImmType9(Value)) {
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Value = AArch64_AM::encodeAdvSIMDModImmType9(Value);
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SDLoc dl(Op);
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SDValue Mov = DAG.getNode(NewOp, dl, MovTy,
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DAG.getConstant(Value, dl, MVT::i32));
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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}
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return SDValue();
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}
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// Try FP splatted SIMD immediate.
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static SDValue tryAdvSIMDModImmFP(unsigned NewOp, SDValue Op, SelectionDAG &DAG,
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const APInt &Bits) {
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if (Bits.getHiBits(64) == Bits.getLoBits(64)) {
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uint64_t Value = Bits.zextOrTrunc(64).getZExtValue();
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EVT VT = Op.getValueType();
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bool isWide = (VT.getSizeInBits() == 128);
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MVT MovTy;
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bool isAdvSIMDModImm = false;
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if ((isAdvSIMDModImm = AArch64_AM::isAdvSIMDModImmType11(Value))) {
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Value = AArch64_AM::encodeAdvSIMDModImmType11(Value);
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MovTy = isWide ? MVT::v4f32 : MVT::v2f32;
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}
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else if ((isAdvSIMDModImm = AArch64_AM::isAdvSIMDModImmType12(Value))) {
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Value = AArch64_AM::encodeAdvSIMDModImmType12(Value);
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MovTy = isWide ? MVT::v2f64 : MVT::f64;
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}
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if (isAdvSIMDModImm) {
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SDLoc dl(Op);
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SDValue Mov = DAG.getNode(NewOp, dl, MovTy,
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DAG.getConstant(Value, dl, MVT::i32));
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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}
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return SDValue();
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}
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SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
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SelectionDAG &DAG) const {
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BuildVectorSDNode *BVN =
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dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
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SDValue LHS = Op.getOperand(0);
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SDLoc dl(Op);
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EVT VT = Op.getValueType();
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BuildVectorSDNode *BVN =
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dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
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if (!BVN) {
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// AND commutes, so try swapping the operands.
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LHS = Op.getOperand(1);
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BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
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}
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if (!BVN)
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return Op;
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APInt CnstBits(VT.getSizeInBits(), 0);
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APInt DefBits(VT.getSizeInBits(), 0);
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APInt UndefBits(VT.getSizeInBits(), 0);
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if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
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if (resolveBuildVector(BVN, DefBits, UndefBits)) {
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SDValue NewOp;
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// We only have BIC vector immediate instruction, which is and-not.
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CnstBits = ~CnstBits;
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// We make use of a little bit of goto ickiness in order to avoid having to
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// duplicate the immediate matching logic for the undef toggled case.
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bool SecondTry = false;
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AttemptModImm:
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if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
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CnstBits = CnstBits.zextOrTrunc(64);
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uint64_t CnstVal = CnstBits.getZExtValue();
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if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
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CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
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MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
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SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
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DAG.getConstant(CnstVal, dl, MVT::i32),
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DAG.getConstant(0, dl, MVT::i32));
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
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CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
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MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
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SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
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DAG.getConstant(CnstVal, dl, MVT::i32),
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DAG.getConstant(8, dl, MVT::i32));
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
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CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
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MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
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SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
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DAG.getConstant(CnstVal, dl, MVT::i32),
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DAG.getConstant(16, dl, MVT::i32));
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
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CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
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MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
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SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
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DAG.getConstant(CnstVal, dl, MVT::i32),
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DAG.getConstant(24, dl, MVT::i32));
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
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CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
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MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
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SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
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DAG.getConstant(CnstVal, dl, MVT::i32),
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DAG.getConstant(0, dl, MVT::i32));
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
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CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
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MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
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SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
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DAG.getConstant(CnstVal, dl, MVT::i32),
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DAG.getConstant(8, dl, MVT::i32));
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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DefBits = ~DefBits;
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if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::BICi, Op, DAG,
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DefBits, &LHS)) ||
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(NewOp = tryAdvSIMDModImm16(AArch64ISD::BICi, Op, DAG,
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DefBits, &LHS)))
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return NewOp;
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else {
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DefBits = ~UndefBits;
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if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::BICi, Op, DAG,
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DefBits, &LHS)) ||
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(NewOp = tryAdvSIMDModImm16(AArch64ISD::BICi, Op, DAG,
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DefBits, &LHS)))
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return NewOp;
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}
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if (SecondTry)
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goto FailedModImm;
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SecondTry = true;
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CnstBits = ~UndefBits;
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goto AttemptModImm;
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}
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// We can always fall back to a non-immediate AND.
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FailedModImm:
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// We can always fall back to a non-immediate AND.
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return Op;
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}
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@ -6434,96 +6573,40 @@ SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
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return Res;
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}
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BuildVectorSDNode *BVN =
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dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
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SDValue LHS = Op.getOperand(1);
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SDLoc dl(Op);
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SDValue LHS = Op.getOperand(0);
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EVT VT = Op.getValueType();
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// OR commutes, so try swapping the operands.
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BuildVectorSDNode *BVN =
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dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
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if (!BVN) {
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LHS = Op.getOperand(0);
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BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
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// OR commutes, so try swapping the operands.
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LHS = Op.getOperand(1);
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BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
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}
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if (!BVN)
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return Op;
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APInt CnstBits(VT.getSizeInBits(), 0);
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APInt DefBits(VT.getSizeInBits(), 0);
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APInt UndefBits(VT.getSizeInBits(), 0);
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if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
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// We make use of a little bit of goto ickiness in order to avoid having to
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// duplicate the immediate matching logic for the undef toggled case.
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bool SecondTry = false;
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AttemptModImm:
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if (resolveBuildVector(BVN, DefBits, UndefBits)) {
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SDValue NewOp;
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if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
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CnstBits = CnstBits.zextOrTrunc(64);
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uint64_t CnstVal = CnstBits.getZExtValue();
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if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
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CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
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MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
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SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
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DAG.getConstant(CnstVal, dl, MVT::i32),
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DAG.getConstant(0, dl, MVT::i32));
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
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CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
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MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
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SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
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DAG.getConstant(CnstVal, dl, MVT::i32),
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DAG.getConstant(8, dl, MVT::i32));
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
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CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
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MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
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SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
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DAG.getConstant(CnstVal, dl, MVT::i32),
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DAG.getConstant(16, dl, MVT::i32));
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
|
||||
MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32),
|
||||
DAG.getConstant(24, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
|
||||
if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
|
||||
MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32),
|
||||
DAG.getConstant(0, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
|
||||
if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
|
||||
MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32),
|
||||
DAG.getConstant(8, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::ORRi, Op, DAG,
|
||||
DefBits, &LHS)) ||
|
||||
(NewOp = tryAdvSIMDModImm16(AArch64ISD::ORRi, Op, DAG,
|
||||
DefBits, &LHS)))
|
||||
return NewOp;
|
||||
else {
|
||||
DefBits = UndefBits;
|
||||
if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::ORRi, Op, DAG,
|
||||
DefBits, &LHS)) ||
|
||||
(NewOp = tryAdvSIMDModImm16(AArch64ISD::ORRi, Op, DAG,
|
||||
DefBits, &LHS)))
|
||||
return NewOp;
|
||||
}
|
||||
|
||||
if (SecondTry)
|
||||
goto FailedModImm;
|
||||
SecondTry = true;
|
||||
CnstBits = UndefBits;
|
||||
goto AttemptModImm;
|
||||
}
|
||||
|
||||
// We can always fall back to a non-immediate OR.
|
||||
FailedModImm:
|
||||
// We can always fall back to a non-immediate OR.
|
||||
return Op;
|
||||
}
|
||||
|
||||
|
|
@ -6555,222 +6638,51 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
|
|||
SelectionDAG &DAG) const {
|
||||
SDLoc dl(Op);
|
||||
EVT VT = Op.getValueType();
|
||||
|
||||
Op = NormalizeBuildVector(Op, DAG);
|
||||
BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
|
||||
|
||||
APInt CnstBits(VT.getSizeInBits(), 0);
|
||||
APInt DefBits(VT.getSizeInBits(), 0);
|
||||
APInt UndefBits(VT.getSizeInBits(), 0);
|
||||
if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
|
||||
// We make use of a little bit of goto ickiness in order to avoid having to
|
||||
// duplicate the immediate matching logic for the undef toggled case.
|
||||
bool SecondTry = false;
|
||||
AttemptModImm:
|
||||
if (resolveBuildVector(BVN, DefBits, UndefBits)) {
|
||||
// Certain magic vector constants (used to express things like NOT
|
||||
// and NEG) are passed through unmodified. This allows codegen patterns
|
||||
// for these operations to match. Special-purpose patterns will lower
|
||||
// these immediates to MOVI if it proves necessary.
|
||||
uint64_t DefVal = DefBits.zextOrTrunc(64).getZExtValue();
|
||||
if (DefBits.getHiBits(64) == DefBits.getLoBits(64) &&
|
||||
VT.isInteger() && (DefVal == 0 || DefVal == UINT64_MAX))
|
||||
return Op;
|
||||
|
||||
if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
|
||||
CnstBits = CnstBits.zextOrTrunc(64);
|
||||
uint64_t CnstVal = CnstBits.getZExtValue();
|
||||
SDValue NewOp;
|
||||
if ((NewOp = tryAdvSIMDModImm64(AArch64ISD::MOVIedit, Op, DAG, DefBits)) ||
|
||||
(NewOp = tryAdvSIMDModImm32(AArch64ISD::MOVIshift, Op, DAG, DefBits)) ||
|
||||
(NewOp = tryAdvSIMDModImm321s(AArch64ISD::MOVImsl, Op, DAG, DefBits)) ||
|
||||
(NewOp = tryAdvSIMDModImm16(AArch64ISD::MOVIshift, Op, DAG, DefBits)) ||
|
||||
(NewOp = tryAdvSIMDModImm8(AArch64ISD::MOVI, Op, DAG, DefBits)) ||
|
||||
(NewOp = tryAdvSIMDModImmFP(AArch64ISD::FMOV, Op, DAG, DefBits)))
|
||||
return NewOp;
|
||||
|
||||
// Certain magic vector constants (used to express things like NOT
|
||||
// and NEG) are passed through unmodified. This allows codegen patterns
|
||||
// for these operations to match. Special-purpose patterns will lower
|
||||
// these immediates to MOVIs if it proves necessary.
|
||||
if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
|
||||
return Op;
|
||||
DefBits = ~DefBits;
|
||||
if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::MVNIshift, Op, DAG, DefBits)) ||
|
||||
(NewOp = tryAdvSIMDModImm321s(AArch64ISD::MVNImsl, Op, DAG, DefBits)) ||
|
||||
(NewOp = tryAdvSIMDModImm16(AArch64ISD::MVNIshift, Op, DAG, DefBits)))
|
||||
return NewOp;
|
||||
|
||||
// The many faces of MOVI...
|
||||
if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
|
||||
if (VT.getSizeInBits() == 128) {
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
DefBits = UndefBits;
|
||||
if ((NewOp = tryAdvSIMDModImm64(AArch64ISD::MOVIedit, Op, DAG, DefBits)) ||
|
||||
(NewOp = tryAdvSIMDModImm32(AArch64ISD::MOVIshift, Op, DAG, DefBits)) ||
|
||||
(NewOp = tryAdvSIMDModImm321s(AArch64ISD::MOVImsl, Op, DAG, DefBits)) ||
|
||||
(NewOp = tryAdvSIMDModImm16(AArch64ISD::MOVIshift, Op, DAG, DefBits)) ||
|
||||
(NewOp = tryAdvSIMDModImm8(AArch64ISD::MOVI, Op, DAG, DefBits)) ||
|
||||
(NewOp = tryAdvSIMDModImmFP(AArch64ISD::FMOV, Op, DAG, DefBits)))
|
||||
return NewOp;
|
||||
|
||||
// Support the V64 version via subregister insertion.
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
|
||||
if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
|
||||
MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32),
|
||||
DAG.getConstant(0, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
|
||||
if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
|
||||
MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32),
|
||||
DAG.getConstant(8, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
|
||||
if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
|
||||
MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32),
|
||||
DAG.getConstant(16, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
|
||||
if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
|
||||
MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32),
|
||||
DAG.getConstant(24, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
|
||||
if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
|
||||
MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32),
|
||||
DAG.getConstant(0, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
|
||||
if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
|
||||
MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32),
|
||||
DAG.getConstant(8, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
|
||||
if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
|
||||
MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32),
|
||||
DAG.getConstant(264, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
|
||||
if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
|
||||
MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32),
|
||||
DAG.getConstant(272, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
|
||||
if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
|
||||
MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
|
||||
// The few faces of FMOV...
|
||||
if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
|
||||
MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
|
||||
if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
|
||||
VT.getSizeInBits() == 128) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
|
||||
// The many faces of MVNI...
|
||||
CnstVal = ~CnstVal;
|
||||
if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
|
||||
MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32),
|
||||
DAG.getConstant(0, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
|
||||
if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
|
||||
MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32),
|
||||
DAG.getConstant(8, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
|
||||
if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
|
||||
MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32),
|
||||
DAG.getConstant(16, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
|
||||
if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
|
||||
MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32),
|
||||
DAG.getConstant(24, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
|
||||
if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
|
||||
MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32),
|
||||
DAG.getConstant(0, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
|
||||
if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
|
||||
MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32),
|
||||
DAG.getConstant(8, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
|
||||
if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
|
||||
MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32),
|
||||
DAG.getConstant(264, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
|
||||
if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
|
||||
CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
|
||||
MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
|
||||
SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
|
||||
DAG.getConstant(CnstVal, dl, MVT::i32),
|
||||
DAG.getConstant(272, dl, MVT::i32));
|
||||
return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
|
||||
}
|
||||
}
|
||||
|
||||
if (SecondTry)
|
||||
goto FailedModImm;
|
||||
SecondTry = true;
|
||||
CnstBits = UndefBits;
|
||||
goto AttemptModImm;
|
||||
DefBits = ~UndefBits;
|
||||
if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::MVNIshift, Op, DAG, DefBits)) ||
|
||||
(NewOp = tryAdvSIMDModImm321s(AArch64ISD::MVNImsl, Op, DAG, DefBits)) ||
|
||||
(NewOp = tryAdvSIMDModImm16(AArch64ISD::MVNIshift, Op, DAG, DefBits)))
|
||||
return NewOp;
|
||||
}
|
||||
FailedModImm:
|
||||
|
||||
// Scan through the operands to find some interesting properties we can
|
||||
// exploit:
|
||||
|
|
|
|||
Loading…
Reference in New Issue