diff --git a/llvm/include/llvm/CodeGen/RegisterScavenging.h b/llvm/include/llvm/CodeGen/RegisterScavenging.h index 122c78534253..3a0ce9914d9f 100644 --- a/llvm/include/llvm/CodeGen/RegisterScavenging.h +++ b/llvm/include/llvm/CodeGen/RegisterScavenging.h @@ -71,8 +71,8 @@ public: RegScavenger() : MBB(nullptr), NumRegUnits(0), Tracking(false) {} - /// Start tracking liveness from the begin of the specific basic block. - void enterBasicBlock(MachineBasicBlock *mbb); + /// Start tracking liveness from the begin of basic block \p MBB. + void enterBasicBlock(MachineBasicBlock &MBB); /// Move the internal MBB iterator and update register states. void forward(); diff --git a/llvm/lib/CodeGen/BranchFolding.cpp b/llvm/lib/CodeGen/BranchFolding.cpp index 0a6e88ea45b7..065bac015c5b 100644 --- a/llvm/lib/CodeGen/BranchFolding.cpp +++ b/llvm/lib/CodeGen/BranchFolding.cpp @@ -397,7 +397,7 @@ static unsigned ComputeCommonTailLength(MachineBasicBlock *MBB1, void BranchFolder::MaintainLiveIns(MachineBasicBlock *CurMBB, MachineBasicBlock *NewMBB) { if (RS) { - RS->enterBasicBlock(CurMBB); + RS->enterBasicBlock(*CurMBB); if (!CurMBB->empty()) RS->forward(std::prev(CurMBB->end())); for (unsigned int i = 1, e = TRI->getNumRegs(); i != e; i++) diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp index 84b202128e4b..7c3fe33cf750 100644 --- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp +++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp @@ -880,7 +880,7 @@ void PEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &Fn, unsigned FrameSetupOpcode = TII.getCallFrameSetupOpcode(); unsigned FrameDestroyOpcode = TII.getCallFrameDestroyOpcode(); - if (RS && !FrameIndexVirtualScavenging) RS->enterBasicBlock(BB); + if (RS && !FrameIndexVirtualScavenging) RS->enterBasicBlock(*BB); bool InsideCallSequence = false; @@ -991,7 +991,7 @@ PEI::scavengeFrameVirtualRegs(MachineFunction &Fn) { // Run through the instructions and find any virtual registers. for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { - RS->enterBasicBlock(&*BB); + RS->enterBasicBlock(*BB); int SPAdj = 0; diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp index 8fa1bf74b7e2..8e002749d3b9 100644 --- a/llvm/lib/CodeGen/RegisterScavenging.cpp +++ b/llvm/lib/CodeGen/RegisterScavenging.cpp @@ -49,9 +49,6 @@ void RegScavenger::initRegState() { // All register units start out unused. RegUnitsAvailable.set(); - if (!MBB) - return; - // Live-in registers are in use. for (const auto &LI : MBB->liveins()) setRegUsed(LI.PhysReg, LI.LaneMask); @@ -63,8 +60,8 @@ void RegScavenger::initRegState() { setRegUsed(I); } -void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) { - MachineFunction &MF = *mbb->getParent(); +void RegScavenger::enterBasicBlock(MachineBasicBlock &MBB) { + MachineFunction &MF = *MBB.getParent(); TII = MF.getSubtarget().getInstrInfo(); TRI = MF.getSubtarget().getRegisterInfo(); MRI = &MF.getRegInfo(); @@ -78,15 +75,15 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) { "Cannot use register scavenger with inaccurate liveness"); // Self-initialize. - if (!MBB) { + if (!this->MBB) { NumRegUnits = TRI->getNumRegUnits(); RegUnitsAvailable.resize(NumRegUnits); KillRegUnits.resize(NumRegUnits); DefRegUnits.resize(NumRegUnits); TmpRegUnits.resize(NumRegUnits); } + this->MBB = &MBB; - MBB = mbb; initRegState(); Tracking = false; diff --git a/llvm/lib/CodeGen/TailDuplication.cpp b/llvm/lib/CodeGen/TailDuplication.cpp index 2a8431c2bab2..7dca17ccd9ac 100644 --- a/llvm/lib/CodeGen/TailDuplication.cpp +++ b/llvm/lib/CodeGen/TailDuplication.cpp @@ -816,7 +816,7 @@ TailDuplicatePass::TailDuplicate(MachineBasicBlock *TailBB, if (RS && !TailBB->livein_empty()) { // Update PredBB livein. - RS->enterBasicBlock(PredBB); + RS->enterBasicBlock(*PredBB); if (!PredBB->empty()) RS->forward(std::prev(PredBB->end())); for (const auto &LI : TailBB->liveins()) { diff --git a/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp b/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp index d7088743bcd8..01f354d19e8d 100644 --- a/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp +++ b/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp @@ -497,7 +497,7 @@ bool AArch64A57FPLoadBalancing::colorChainSet(std::vector GV, int AArch64A57FPLoadBalancing::scavengeRegister(Chain *G, Color C, MachineBasicBlock &MBB) { RegScavenger RS; - RS.enterBasicBlock(&MBB); + RS.enterBasicBlock(MBB); RS.forward(MachineBasicBlock::iterator(G->getStart())); // Can we find an appropriate register that is available throughout the life diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 4b1b15f868a3..ed51b3bad1c6 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -744,7 +744,7 @@ unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB, Entry.addLiveIn(Reg); } - RS->enterBasicBlock(&Entry); + RS->enterBasicBlock(Entry); // FIXME: Can we scavenge an SReg_64 and access the subregs? unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0); unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0); diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp index da8ada4e5391..c439a5fe9f54 100644 --- a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp +++ b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp @@ -326,7 +326,7 @@ unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm, int Reg =0; int SpReg = 0; - rs.enterBasicBlock(&MBB); + rs.enterBasicBlock(MBB); rs.forward(II); // // We need to know which registers can be used, in the case where there diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp index 1d592286f430..aadf64d0bbec 100644 --- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -596,7 +596,7 @@ PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB, (!UseAtEnd && (&MBB->getParent()->front() == MBB))) return true; - RS.enterBasicBlock(MBB); + RS.enterBasicBlock(*MBB); if (UseAtEnd && !MBB->empty()) { // The scratch register will be used at the end of the block, so must diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyPEI.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyPEI.cpp index 538011ea25c4..5d720869be9e 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyPEI.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyPEI.cpp @@ -867,7 +867,7 @@ void WasmPEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &Fn, unsigned FrameSetupOpcode = TII.getCallFrameSetupOpcode(); unsigned FrameDestroyOpcode = TII.getCallFrameDestroyOpcode(); - if (RS && !FrameIndexVirtualScavenging) RS->enterBasicBlock(BB); + if (RS && !FrameIndexVirtualScavenging) RS->enterBasicBlock(*BB); bool InsideCallSequence = false; @@ -977,7 +977,7 @@ WasmPEI::scavengeFrameVirtualRegs(MachineFunction &Fn) { // Run through the instructions and find any virtual registers. for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { - RS->enterBasicBlock(&*BB); + RS->enterBasicBlock(*BB); int SPAdj = 0;