diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index b51e4e70330d..7327d42138e0 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -550,6 +550,37 @@ def : InstAlias<"csrci $csr, $imm", (CSRRCI X0, uimm12:$csr, uimm5:$imm)>; def : InstAlias<"sfence.vma", (SFENCE_VMA X0, X0)>; def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>; +let EmitPriority = 0 in { +def : InstAlias<"add $rd, $rs1, $imm12", + (ADDI GPR:$rd, GPR:$rs1, simm12:$imm12)>; +def : InstAlias<"and $rd, $rs1, $imm12", + (ANDI GPR:$rd, GPR:$rs1, simm12:$imm12)>; +def : InstAlias<"xor $rd, $rs1, $imm12", + (XORI GPR:$rd, GPR:$rs1, simm12:$imm12)>; +def : InstAlias<"or $rd, $rs1, $imm12", + (ORI GPR:$rd, GPR:$rs1, simm12:$imm12)>; +def : InstAlias<"sll $rd, $rs1, $shamt", + (SLLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>; +def : InstAlias<"srl $rd, $rs1, $shamt", + (SRLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>; +def : InstAlias<"sra $rd, $rs1, $shamt", + (SRAI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>; +let Predicates = [IsRV64] in { +def : InstAlias<"addw $rd, $rs1, $imm12", + (ADDIW GPR:$rd, GPR:$rs1, simm12:$imm12)>; +def : InstAlias<"sllw $rd, $rs1, $shamt", + (SLLIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>; +def : InstAlias<"srlw $rd, $rs1, $shamt", + (SRLIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>; +def : InstAlias<"sraw $rd, $rs1, $shamt", + (SRAIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>; +} // Predicates = [IsRV64] +def : InstAlias<"slt $rd, $rs1, $imm12", + (SLTI GPR:$rd, GPR:$rs1, simm12:$imm12)>; +def : InstAlias<"sltu $rd, $rs1, $imm12", + (SLTIU GPR:$rd, GPR:$rs1, simm12:$imm12)>; +} + //===----------------------------------------------------------------------===// // Pseudo-instructions and codegen patterns // diff --git a/llvm/test/MC/RISCV/rv32i-aliases-invalid.s b/llvm/test/MC/RISCV/rv32i-aliases-invalid.s index 37cd36c3b400..b50a8e4033e2 100644 --- a/llvm/test/MC/RISCV/rv32i-aliases-invalid.s +++ b/llvm/test/MC/RISCV/rv32i-aliases-invalid.s @@ -11,5 +11,13 @@ li t4, foo # CHECK: :[[@LINE]]:8: error: immediate must be an integer i negw x1, x2 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled sext.w x3, x4 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled +sll x2, x3, 32 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31] +srl x2, x3, 32 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31] +sra x2, x3, 32 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31] + +sll x2, x3, -1 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31] +srl x2, x3, -2 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31] +sra x2, x3, -3 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31] + foo: .space 4 diff --git a/llvm/test/MC/RISCV/rv32i-invalid.s b/llvm/test/MC/RISCV/rv32i-invalid.s index 96874e907d0b..aa1ce4011bfb 100644 --- a/llvm/test/MC/RISCV/rv32i-invalid.s +++ b/llvm/test/MC/RISCV/rv32i-invalid.s @@ -69,6 +69,7 @@ csrrci x0, 43, %pcrel_lo(d) # CHECK: :[[@LINE]]:16: error: immediate must be an ori a0, a1, %hi(foo) # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [-2048, 2047] andi ra, sp, %pcrel_hi(123) # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [-2048, 2047] xori a2, a3, %hi(345) # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [-2048, 2047] +add a1, a2, (a3) # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [-2048, 2047] ## uimm12 csrrw a0, %lo(1), a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095] @@ -126,7 +127,6 @@ sraw t0, s2, zero # CHECK: :[[@LINE]]:1: error: instruction use requires an opti # Invalid operand types xori sp, 22, 220 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction sub t0, t2, 1 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction -add a1, a2, (a3) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction # Too many operands add ra, zero, zero, zero # CHECK: :[[@LINE]]:21: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv64i-aliases-invalid.s b/llvm/test/MC/RISCV/rv64i-aliases-invalid.s index e21601b51a4b..f3f2acc473dd 100644 --- a/llvm/test/MC/RISCV/rv64i-aliases-invalid.s +++ b/llvm/test/MC/RISCV/rv64i-aliases-invalid.s @@ -8,5 +8,21 @@ rdinstreth x29 # CHECK: :[[@LINE]]:1: error: instruction use requires an option rdcycleh x27 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled rdtimeh x28 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled +sll x2, x3, 64 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63] +srl x2, x3, 64 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63] +sra x2, x3, 64 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63] + +sll x2, x3, -1 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63] +srl x2, x3, -2 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63] +sra x2, x3, -3 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63] + +sllw x2, x3, 32 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31] +srlw x2, x3, 32 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31] +sraw x2, x3, 32 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31] + +sllw x2, x3, -1 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31] +srlw x2, x3, -2 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31] +sraw x2, x3, -3 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31] + foo: .space 8 diff --git a/llvm/test/MC/RISCV/rv64i-aliases-valid.s b/llvm/test/MC/RISCV/rv64i-aliases-valid.s index f00c75f58a07..bc0dc527cc42 100644 --- a/llvm/test/MC/RISCV/rv64i-aliases-valid.s +++ b/llvm/test/MC/RISCV/rv64i-aliases-valid.s @@ -111,3 +111,21 @@ negw x31, x1 # CHECK-INST: addiw t6, ra, 0 # CHECK-ALIAS: sext.w t6, ra sext.w x31, x1 + +# The following aliases are accepted as input but the canonical form +# of the instruction will always be printed. +# CHECK-INST: addiw a2, a3, 4 +# CHECK-ALIAS: addiw a2, a3, 4 +addw a2,a3,4 + +# CHECK-INST: slliw a2, a3, 4 +# CHECK-ALIAS: slliw a2, a3, 4 +sllw a2,a3,4 + +# CHECK-INST: srliw a2, a3, 4 +# CHECK-ALIAS: srliw a2, a3, 4 +srlw a2,a3,4 + +# CHECK-INST: sraiw a2, a3, 4 +# CHECK-ALIAS: sraiw a2, a3, 4 +sraw a2,a3,4 diff --git a/llvm/test/MC/RISCV/rvi-aliases-valid.s b/llvm/test/MC/RISCV/rvi-aliases-valid.s index eafa486a8fae..e2b22c1d49e4 100644 --- a/llvm/test/MC/RISCV/rvi-aliases-valid.s +++ b/llvm/test/MC/RISCV/rvi-aliases-valid.s @@ -155,3 +155,41 @@ sfence.vma # CHECK-INST: sfence.vma a0, zero # CHECK-ALIAS: sfence.vma a0 sfence.vma a0 + +# The following aliases are accepted as input but the canonical form +# of the instruction will always be printed. +# CHECK-INST: addi a2, a3, 4 +# CHECK-ALIAS: addi a2, a3, 4 +add a2,a3,4 + +# CHECK-INST: andi a2, a3, 4 +# CHECK-ALIAS: andi a2, a3, 4 +and a2,a3,4 + +# CHECK-INST: xori a2, a3, 4 +# CHECK-ALIAS: xori a2, a3, 4 +xor a2,a3,4 + +# CHECK-INST: ori a2, a3, 4 +# CHECK-ALIAS: ori a2, a3, 4 +or a2,a3,4 + +# CHECK-INST: slli a2, a3, 4 +# CHECK-ALIAS: slli a2, a3, 4 +sll a2,a3,4 + +# CHECK-INST: srli a2, a3, 4 +# CHECK-ALIAS: srli a2, a3, 4 +srl a2,a3,4 + +# CHECK-INST: srai a2, a3, 4 +# CHECK-ALIAS: srai a2, a3, 4 +sra a2,a3,4 + +# CHECK-INST: slti a2, a3, 4 +# CHECK-ALIAS: slti a2, a3, 4 +slt a2,a3,4 + +# CHECK-INST: sltiu a2, a3, 4 +# CHECK-ALIAS: sltiu a2, a3, 4 +sltu a2,a3,4