forked from OSchip/llvm-project
[AMDGPU][MC][GFX9] Corrected parsing of v_cndmask_b32_sdwa
See https://bugs.llvm.org/show_bug.cgi?id=43607 Reviewers: arsenm, rampitec Differential Revision: https://reviews.llvm.org/D69095 llvm-svn: 375231
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llvm
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@ -1423,9 +1423,12 @@ public:
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void cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands);
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void cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands);
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void cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands);
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void cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands);
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void cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands);
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void cvtSDWA(MCInst &Inst, const OperandVector &Operands,
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uint64_t BasicInstType, bool skipVcc = false);
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uint64_t BasicInstType,
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bool SkipDstVcc = false,
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bool SkipSrcVcc = false);
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AMDGPUOperand::Ptr defaultBLGP() const;
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AMDGPUOperand::Ptr defaultCBSZ() const;
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@ -6813,7 +6816,11 @@ void AMDGPUAsmParser::cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands) {
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}
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void AMDGPUAsmParser::cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands) {
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cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, true);
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cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, true, true);
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}
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void AMDGPUAsmParser::cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands) {
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cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, false, true);
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}
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void AMDGPUAsmParser::cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands) {
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@ -6821,11 +6828,14 @@ void AMDGPUAsmParser::cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands) {
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}
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void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
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uint64_t BasicInstType, bool skipVcc) {
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uint64_t BasicInstType,
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bool SkipDstVcc,
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bool SkipSrcVcc) {
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using namespace llvm::AMDGPU::SDWA;
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OptionalImmIndexMap OptionalIdx;
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bool skippedVcc = false;
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bool SkipVcc = SkipDstVcc || SkipSrcVcc;
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bool SkippedVcc = false;
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unsigned I = 1;
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const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
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@ -6835,19 +6845,21 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
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for (unsigned E = Operands.size(); I != E; ++I) {
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AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
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if (skipVcc && !skippedVcc && Op.isReg() &&
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if (SkipVcc && !SkippedVcc && Op.isReg() &&
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(Op.getReg() == AMDGPU::VCC || Op.getReg() == AMDGPU::VCC_LO)) {
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// VOP2b (v_add_u32, v_sub_u32 ...) sdwa use "vcc" token as dst.
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// Skip it if it's 2nd (e.g. v_add_i32_sdwa v1, vcc, v2, v3)
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// or 4th (v_addc_u32_sdwa v1, vcc, v2, v3, vcc) operand.
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// Skip VCC only if we didn't skip it on previous iteration.
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// Note that src0 and src1 occupy 2 slots each because of modifiers.
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if (BasicInstType == SIInstrFlags::VOP2 &&
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(Inst.getNumOperands() == 1 || Inst.getNumOperands() == 5)) {
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skippedVcc = true;
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((SkipDstVcc && Inst.getNumOperands() == 1) ||
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(SkipSrcVcc && Inst.getNumOperands() == 5))) {
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SkippedVcc = true;
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continue;
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} else if (BasicInstType == SIInstrFlags::VOPC &&
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Inst.getNumOperands() == 0) {
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skippedVcc = true;
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SkippedVcc = true;
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continue;
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}
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}
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@ -6859,7 +6871,7 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
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} else {
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llvm_unreachable("Invalid operand type");
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}
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skippedVcc = false;
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SkippedVcc = false;
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}
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if (Inst.getOpcode() != AMDGPU::V_NOP_sdwa_gfx10 &&
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@ -224,7 +224,7 @@ multiclass VOP2eInst <string opName,
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foreach _ = BoolToList<P.HasExtSDWA>.ret in
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def _sdwa : VOP2_SDWA_Pseudo <opName, P> {
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let AsmMatchConverter = "cvtSdwaVOP2b";
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let AsmMatchConverter = "cvtSdwaVOP2e";
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}
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foreach _ = BoolToList<P.HasExtDPP>.ret in
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@ -594,6 +594,11 @@ v_cndmask_b32_sdwa v5, -1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:
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// GFX89: v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x0e]
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v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
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v_cndmask_b32_sdwa v5, vcc_lo, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
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// NOSICI: error: not a valid operand
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// NOVI: error: invalid operand for instruction
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// NOGFX9: error: invalid operand (violates constant bus restrictions)
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//===----------------------------------------------------------------------===//
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// Check VOPC opcodes
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//===----------------------------------------------------------------------===//
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