forked from OSchip/llvm-project
[AArch64]Add support to spill/fill D tuples such as DPair/DTriple/DQuad. There is no test cases for D tuple as the original test cases are too large. As the spill/fill of the D tuple is similar to the Q tuple, the correctness can be guaranteed.
llvm-svn: 198684
This commit is contained in:
Hao Liu
parent
e42fd0d34d
commit
7d11d99d20
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@ -477,12 +477,18 @@ AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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default:
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llvm_unreachable("Unknown size for regclass");
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}
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} else { // The spill of D tuples is implemented by Q tuples
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if (RC == &AArch64::QPairRegClass)
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} else { // For a super register class has more than one sub registers
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if (AArch64::DPairRegClass.hasSubClassEq(RC))
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StoreOp = AArch64::ST1x2_8B;
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else if (AArch64::DTripleRegClass.hasSubClassEq(RC))
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StoreOp = AArch64::ST1x3_8B;
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else if (AArch64::DQuadRegClass.hasSubClassEq(RC))
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StoreOp = AArch64::ST1x4_8B;
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else if (AArch64::QPairRegClass.hasSubClassEq(RC))
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StoreOp = AArch64::ST1x2_16B;
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else if (RC == &AArch64::QTripleRegClass)
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else if (AArch64::QTripleRegClass.hasSubClassEq(RC))
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StoreOp = AArch64::ST1x3_16B;
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else if (RC == &AArch64::QQuadRegClass)
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else if (AArch64::QQuadRegClass.hasSubClassEq(RC))
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StoreOp = AArch64::ST1x4_16B;
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else
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llvm_unreachable("Unknown reg class");
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@ -537,12 +543,18 @@ AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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default:
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llvm_unreachable("Unknown size for regclass");
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}
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} else { // The spill of D tuples is implemented by Q tuples
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if (RC == &AArch64::QPairRegClass)
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} else { // For a super register class has more than one sub registers
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if (AArch64::DPairRegClass.hasSubClassEq(RC))
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LoadOp = AArch64::LD1x2_8B;
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else if (AArch64::DTripleRegClass.hasSubClassEq(RC))
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LoadOp = AArch64::LD1x3_8B;
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else if (AArch64::DQuadRegClass.hasSubClassEq(RC))
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LoadOp = AArch64::LD1x4_8B;
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else if (AArch64::QPairRegClass.hasSubClassEq(RC))
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LoadOp = AArch64::LD1x2_16B;
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else if (RC == &AArch64::QTripleRegClass)
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else if (AArch64::QTripleRegClass.hasSubClassEq(RC))
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LoadOp = AArch64::LD1x3_16B;
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else if (RC == &AArch64::QQuadRegClass)
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else if (AArch64::QQuadRegClass.hasSubClassEq(RC))
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LoadOp = AArch64::LD1x4_16B;
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else
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llvm_unreachable("Unknown reg class");
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@ -649,6 +661,17 @@ void AArch64InstrInfo::getAddressConstraints(const MachineInstr &MI,
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MinOffset = -0x40 * AccessScale;
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MaxOffset = 0x3f * AccessScale;
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return;
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case AArch64::LD1x2_8B: case AArch64::ST1x2_8B:
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AccessScale = 16;
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MinOffset = 0;
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MaxOffset = 0xfff * AccessScale;
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return;
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case AArch64::LD1x3_8B: case AArch64::ST1x3_8B:
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AccessScale = 24;
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MinOffset = 0;
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MaxOffset = 0xfff * AccessScale;
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return;
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case AArch64::LD1x4_8B: case AArch64::ST1x4_8B:
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case AArch64::LD1x2_16B: case AArch64::ST1x2_16B:
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AccessScale = 32;
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MinOffset = 0;
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@ -77,7 +77,10 @@ AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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}
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static bool hasFrameOffset(int opcode) {
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return opcode != AArch64::LD1x2_16B && opcode != AArch64::LD1x3_16B &&
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return opcode != AArch64::LD1x2_8B && opcode != AArch64::LD1x3_8B &&
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opcode != AArch64::LD1x4_8B && opcode != AArch64::ST1x2_8B &&
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opcode != AArch64::ST1x3_8B && opcode != AArch64::ST1x4_8B &&
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opcode != AArch64::LD1x2_16B && opcode != AArch64::LD1x3_16B &&
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opcode != AArch64::LD1x4_16B && opcode != AArch64::ST1x2_16B &&
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opcode != AArch64::ST1x3_16B && opcode != AArch64::ST1x4_16B;
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}
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@ -30,7 +30,6 @@ def dsub_0 : SubRegIndex<64>;
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def dsub_1 : SubRegIndex<64, 64>;
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def dsub_2 : ComposedSubRegIndex<qsub_1, dsub_0>;
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def dsub_3 : ComposedSubRegIndex<qsub_1, dsub_1>;
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def dsub_4 : ComposedSubRegIndex<qsub_2, dsub_0>;
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}
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// Registers are identified with 5-bit ID numbers.
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@ -206,7 +205,7 @@ def FlagClass : RegisterClass<"AArch64", [i32], 32, (add NZCV)> {
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//===----------------------------------------------------------------------===//
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// Consecutive vector registers
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//===----------------------------------------------------------------------===//
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// 2 Consecutive 64-bit registers: D0_D1, D1_D2, ..., D30_D31
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// 2 Consecutive 64-bit registers: D0_D1, D1_D2, ..., D31_D0
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def Tuples2D : RegisterTuples<[dsub_0, dsub_1],
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[(rotl FPR64, 0), (rotl FPR64, 1)]>;
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@ -132,3 +132,44 @@ declare { <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld3.v4f32(i8*,
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declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld4.v16i8(i8*, i32)
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declare void @foo()
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; FIXME: We should not generate ld/st for such register spill/fill, because the
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; test case seems very simple and the register pressure is not high. If the
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; spill/fill algorithm is optimized, this test case may not be triggered. And
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; then we can delete it.
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; check the spill for Register Class QPair_with_qsub_0_in_FPR128Lo
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define <8 x i16> @test_2xFPR128Lo(i64 %got, i8* %ptr, <1 x i64> %a) {
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tail call void @llvm.arm.neon.vst2lane.v1i64(i8* %ptr, <1 x i64> zeroinitializer, <1 x i64> zeroinitializer, i32 0, i32 8)
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tail call void @foo()
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%sv = shufflevector <1 x i64> zeroinitializer, <1 x i64> %a, <2 x i32> <i32 0, i32 1>
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%1 = bitcast <2 x i64> %sv to <8 x i16>
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%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
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%3 = mul <8 x i16> %2, %2
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ret <8 x i16> %3
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}
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; check the spill for Register Class QTriple_with_qsub_0_in_FPR128Lo
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define <8 x i16> @test_3xFPR128Lo(i64 %got, i8* %ptr, <1 x i64> %a) {
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tail call void @llvm.arm.neon.vst3lane.v1i64(i8* %ptr, <1 x i64> zeroinitializer, <1 x i64> zeroinitializer, <1 x i64> zeroinitializer, i32 0, i32 8)
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tail call void @foo()
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%sv = shufflevector <1 x i64> zeroinitializer, <1 x i64> %a, <2 x i32> <i32 0, i32 1>
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%1 = bitcast <2 x i64> %sv to <8 x i16>
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%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
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%3 = mul <8 x i16> %2, %2
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ret <8 x i16> %3
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}
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; check the spill for Register Class QQuad_with_qsub_0_in_FPR128Lo
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define <8 x i16> @test_4xFPR128Lo(i64 %got, i8* %ptr, <1 x i64> %a) {
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tail call void @llvm.arm.neon.vst4lane.v1i64(i8* %ptr, <1 x i64> zeroinitializer, <1 x i64> zeroinitializer, <1 x i64> zeroinitializer, <1 x i64> zeroinitializer, i32 0, i32 8)
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tail call void @foo()
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%sv = shufflevector <1 x i64> zeroinitializer, <1 x i64> %a, <2 x i32> <i32 0, i32 1>
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%1 = bitcast <2 x i64> %sv to <8 x i16>
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%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
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%3 = mul <8 x i16> %2, %2
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ret <8 x i16> %3
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}
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declare void @llvm.arm.neon.vst2lane.v1i64(i8*, <1 x i64>, <1 x i64>, i32, i32)
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declare void @llvm.arm.neon.vst3lane.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, i32, i32)
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declare void @llvm.arm.neon.vst4lane.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32, i32)
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