From 7cecadb9afdff13b6e2e23b3a3966de9e94af05d Mon Sep 17 00:00:00 2001 From: Petar Avramovic Date: Mon, 28 Jan 2019 12:10:17 +0000 Subject: [PATCH] [MIPS GlobalISel] Select sub Lower G_USUBO and G_USUBE. Add narrowScalar for G_SUB. Legalize and select G_SUB for MIPS 32. Differential Revision: https://reviews.llvm.org/D53416 llvm-svn: 352351 --- .../CodeGen/GlobalISel/LegalizerHelper.cpp | 66 ++++ llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 4 +- llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp | 2 + .../GlobalISel/instruction-select/sub.mir | 31 ++ .../CodeGen/Mips/GlobalISel/legalizer/sub.mir | 342 ++++++++++++++++++ .../CodeGen/Mips/GlobalISel/llvm-ir/sub.ll | 158 ++++++++ .../Mips/GlobalISel/regbankselect/sub.mir | 30 ++ 7 files changed, 631 insertions(+), 2 deletions(-) create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index 62ed8af2c9a3..5db33b365400 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -343,6 +343,38 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI, MI.eraseFromParent(); return Legalized; } + case TargetOpcode::G_SUB: { + // FIXME: add support for when SizeOp0 isn't an exact multiple of + // NarrowSize. + if (SizeOp0 % NarrowSize != 0) + return UnableToLegalize; + + int NumParts = SizeOp0 / NarrowTy.getSizeInBits(); + + SmallVector Src1Regs, Src2Regs, DstRegs; + extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs); + extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs); + + unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy); + unsigned BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1)); + MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut}, + {Src1Regs[0], Src2Regs[0]}); + DstRegs.push_back(DstReg); + unsigned BorrowIn = BorrowOut; + for (int i = 1; i < NumParts; ++i) { + DstReg = MRI.createGenericVirtualRegister(NarrowTy); + BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1)); + + MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut}, + {Src1Regs[i], Src2Regs[i], BorrowIn}); + + DstRegs.push_back(DstReg); + BorrowIn = BorrowOut; + } + MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs); + MI.eraseFromParent(); + return Legalized; + } case TargetOpcode::G_MUL: return narrowScalarMul(MI, TypeIdx, NarrowTy); case TargetOpcode::G_EXTRACT: { @@ -1242,6 +1274,40 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) { MI.eraseFromParent(); return Legalized; } + case G_USUBO: { + unsigned Res = MI.getOperand(0).getReg(); + unsigned BorrowOut = MI.getOperand(1).getReg(); + unsigned LHS = MI.getOperand(2).getReg(); + unsigned RHS = MI.getOperand(3).getReg(); + + MIRBuilder.buildSub(Res, LHS, RHS); + MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS); + + MI.eraseFromParent(); + return Legalized; + } + case G_USUBE: { + unsigned Res = MI.getOperand(0).getReg(); + unsigned BorrowOut = MI.getOperand(1).getReg(); + unsigned LHS = MI.getOperand(2).getReg(); + unsigned RHS = MI.getOperand(3).getReg(); + unsigned BorrowIn = MI.getOperand(4).getReg(); + + unsigned TmpRes = MRI.createGenericVirtualRegister(Ty); + unsigned ZExtBorrowIn = MRI.createGenericVirtualRegister(Ty); + unsigned LHS_EQ_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1)); + unsigned LHS_ULT_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1)); + + MIRBuilder.buildSub(TmpRes, LHS, RHS); + MIRBuilder.buildZExt(ZExtBorrowIn, BorrowIn); + MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn); + MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LHS_EQ_RHS, LHS, RHS); + MIRBuilder.buildICmp(CmpInst::ICMP_ULT, LHS_ULT_RHS, LHS, RHS); + MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS); + + MI.eraseFromParent(); + return Legalized; + } } } diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp index ceab690b95b8..29c90ef6441c 100644 --- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp +++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp @@ -24,11 +24,11 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { const LLT s64 = LLT::scalar(64); const LLT p0 = LLT::pointer(0, 32); - getActionDefinitionsBuilder(G_ADD) + getActionDefinitionsBuilder({G_ADD, G_SUB}) .legalFor({s32}) .clampScalar(0, s32, s32); - getActionDefinitionsBuilder(G_UADDE) + getActionDefinitionsBuilder({G_UADDE, G_USUBO, G_USUBE}) .lowerFor({{s32, s1}}); getActionDefinitionsBuilder({G_LOAD, G_STORE}) diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp index 592cf5698fd0..03360addc18f 100644 --- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp +++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp @@ -82,7 +82,9 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { const ValueMapping *OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx]; switch (Opc) { + case G_TRUNC: case G_ADD: + case G_SUB: case G_LOAD: case G_STORE: case G_ZEXTLOAD: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub.mir new file mode 100644 index 000000000000..911073a7f8d4 --- /dev/null +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub.mir @@ -0,0 +1,31 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 +--- | + + define void @sub_i32(i32 %x, i32 %y) {entry: ret void} + +... +--- +name: sub_i32 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $a0, $a1 + + ; MIPS32-LABEL: name: sub_i32 + ; MIPS32: liveins: $a0, $a1 + ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 + ; MIPS32: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[COPY1]] + ; MIPS32: $v0 = COPY [[SUBu]] + ; MIPS32: RetRA implicit $v0 + %0:gprb(s32) = COPY $a0 + %1:gprb(s32) = COPY $a1 + %2:gprb(s32) = G_SUB %0, %1 + $v0 = COPY %2(s32) + RetRA implicit $v0 + +... diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir new file mode 100644 index 000000000000..aabb90705f2a --- /dev/null +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir @@ -0,0 +1,342 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 +--- | + + define void @sub_i32() {entry: ret void} + define void @sub_i8_sext() {entry: ret void} + define void @sub_i8_zext() {entry: ret void} + define void @sub_i8_aext() {entry: ret void} + define void @sub_i16_sext() {entry: ret void} + define void @sub_i16_zext() {entry: ret void} + define void @sub_i16_aext() {entry: ret void} + define void @sub_i64() {entry: ret void} + define void @sub_i128() {entry: ret void} + +... +--- +name: sub_i32 +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1 + + ; MIPS32-LABEL: name: sub_i32 + ; MIPS32: liveins: $a0, $a1 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]] + ; MIPS32: $v0 = COPY [[SUB]](s32) + ; MIPS32: RetRA implicit $v0 + %0:_(s32) = COPY $a0 + %1:_(s32) = COPY $a1 + %2:_(s32) = G_SUB %0, %1 + $v0 = COPY %2(s32) + RetRA implicit $v0 + +... +--- +name: sub_i8_sext +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1 + + ; MIPS32-LABEL: name: sub_i8_sext + ; MIPS32: liveins: $a0, $a1 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]] + ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) + ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]] + ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]] + ; MIPS32: $v0 = COPY [[ASHR]](s32) + ; MIPS32: RetRA implicit $v0 + %2:_(s32) = COPY $a0 + %0:_(s8) = G_TRUNC %2(s32) + %3:_(s32) = COPY $a1 + %1:_(s8) = G_TRUNC %3(s32) + %4:_(s8) = G_SUB %1, %0 + %5:_(s32) = G_SEXT %4(s8) + $v0 = COPY %5(s32) + RetRA implicit $v0 + +... +--- +name: sub_i8_zext +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1 + + ; MIPS32-LABEL: name: sub_i8_zext + ; MIPS32: liveins: $a0, $a1 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]] + ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; MIPS32: $v0 = COPY [[AND]](s32) + ; MIPS32: RetRA implicit $v0 + %2:_(s32) = COPY $a0 + %0:_(s8) = G_TRUNC %2(s32) + %3:_(s32) = COPY $a1 + %1:_(s8) = G_TRUNC %3(s32) + %4:_(s8) = G_SUB %1, %0 + %5:_(s32) = G_ZEXT %4(s8) + $v0 = COPY %5(s32) + RetRA implicit $v0 + +... +--- +name: sub_i8_aext +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1 + + ; MIPS32-LABEL: name: sub_i8_aext + ; MIPS32: liveins: $a0, $a1 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]] + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) + ; MIPS32: $v0 = COPY [[COPY4]](s32) + ; MIPS32: RetRA implicit $v0 + %2:_(s32) = COPY $a0 + %0:_(s8) = G_TRUNC %2(s32) + %3:_(s32) = COPY $a1 + %1:_(s8) = G_TRUNC %3(s32) + %4:_(s8) = G_SUB %1, %0 + %5:_(s32) = G_ANYEXT %4(s8) + $v0 = COPY %5(s32) + RetRA implicit $v0 + +... +--- +name: sub_i16_sext +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1 + + ; MIPS32-LABEL: name: sub_i16_sext + ; MIPS32: liveins: $a0, $a1 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]] + ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) + ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]] + ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]] + ; MIPS32: $v0 = COPY [[ASHR]](s32) + ; MIPS32: RetRA implicit $v0 + %2:_(s32) = COPY $a0 + %0:_(s16) = G_TRUNC %2(s32) + %3:_(s32) = COPY $a1 + %1:_(s16) = G_TRUNC %3(s32) + %4:_(s16) = G_SUB %1, %0 + %5:_(s32) = G_SEXT %4(s16) + $v0 = COPY %5(s32) + RetRA implicit $v0 + +... +--- +name: sub_i16_zext +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1 + + ; MIPS32-LABEL: name: sub_i16_zext + ; MIPS32: liveins: $a0, $a1 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]] + ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; MIPS32: $v0 = COPY [[AND]](s32) + ; MIPS32: RetRA implicit $v0 + %2:_(s32) = COPY $a0 + %0:_(s16) = G_TRUNC %2(s32) + %3:_(s32) = COPY $a1 + %1:_(s16) = G_TRUNC %3(s32) + %4:_(s16) = G_SUB %1, %0 + %5:_(s32) = G_ZEXT %4(s16) + $v0 = COPY %5(s32) + RetRA implicit $v0 + +... +--- +name: sub_i16_aext +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1 + + ; MIPS32-LABEL: name: sub_i16_aext + ; MIPS32: liveins: $a0, $a1 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]] + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) + ; MIPS32: $v0 = COPY [[COPY4]](s32) + ; MIPS32: RetRA implicit $v0 + %2:_(s32) = COPY $a0 + %0:_(s16) = G_TRUNC %2(s32) + %3:_(s32) = COPY $a1 + %1:_(s16) = G_TRUNC %3(s32) + %4:_(s16) = G_SUB %1, %0 + %5:_(s32) = G_ANYEXT %4(s16) + $v0 = COPY %5(s32) + RetRA implicit $v0 + +... +--- +name: sub_i64 +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1, $a2, $a3 + + ; MIPS32-LABEL: name: sub_i64 + ; MIPS32: liveins: $a0, $a1, $a2, $a3 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 + ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY3]], [[COPY1]] + ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY3]](s32), [[COPY1]] + ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY]] + ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; MIPS32: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]] + ; MIPS32: $v0 = COPY [[SUB2]](s32) + ; MIPS32: $v1 = COPY [[SUB]](s32) + ; MIPS32: RetRA implicit $v0, implicit $v1 + %2:_(s32) = COPY $a0 + %3:_(s32) = COPY $a1 + %0:_(s64) = G_MERGE_VALUES %3(s32), %2(s32) + %4:_(s32) = COPY $a2 + %5:_(s32) = COPY $a3 + %1:_(s64) = G_MERGE_VALUES %5(s32), %4(s32) + %6:_(s64) = G_SUB %1, %0 + %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64) + $v0 = COPY %8(s32) + $v1 = COPY %7(s32) + RetRA implicit $v0, implicit $v1 + +... +--- +name: sub_i128 +alignment: 2 +tracksRegLiveness: true +fixedStack: + - { id: 0, offset: 28, size: 4, alignment: 4, stack-id: 0, isImmutable: true } + - { id: 1, offset: 24, size: 4, alignment: 8, stack-id: 0, isImmutable: true } + - { id: 2, offset: 20, size: 4, alignment: 4, stack-id: 0, isImmutable: true } + - { id: 3, offset: 16, size: 4, alignment: 8, stack-id: 0, isImmutable: true } +body: | + bb.1.entry: + liveins: $a0, $a1, $a2, $a3 + + ; MIPS32-LABEL: name: sub_i128 + ; MIPS32: liveins: $a0, $a1, $a2, $a3 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 + ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0) + ; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load 4 from %fixed-stack.1, align 0) + ; MIPS32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 + ; MIPS32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load 4 from %fixed-stack.2, align 0) + ; MIPS32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 + ; MIPS32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load 4 from %fixed-stack.3, align 0) + ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[LOAD]], [[COPY]] + ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD]](s32), [[COPY]] + ; MIPS32: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32) + ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[LOAD1]], [[COPY1]] + ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; MIPS32: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]] + ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[LOAD1]](s32), [[COPY1]] + ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD1]](s32), [[COPY1]] + ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) + ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32) + ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) + ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]] + ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[COPY5]], [[COPY6]] + ; MIPS32: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[SELECT]](s32) + ; MIPS32: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[LOAD2]], [[COPY2]] + ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; MIPS32: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) + ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C2]] + ; MIPS32: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[AND2]] + ; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[LOAD2]](s32), [[COPY2]] + ; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD2]](s32), [[COPY2]] + ; MIPS32: [[COPY9:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) + ; MIPS32: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ICMP4]](s32) + ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; MIPS32: [[COPY11:%[0-9]+]]:_(s32) = COPY [[ICMP3]](s32) + ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]] + ; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[COPY9]], [[COPY10]] + ; MIPS32: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[LOAD3]], [[COPY3]] + ; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; MIPS32: [[COPY12:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32) + ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C4]] + ; MIPS32: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB5]], [[AND4]] + ; MIPS32: $v0 = COPY [[SUB]](s32) + ; MIPS32: $v1 = COPY [[SUB2]](s32) + ; MIPS32: $a0 = COPY [[SUB4]](s32) + ; MIPS32: $a1 = COPY [[SUB6]](s32) + ; MIPS32: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1 + %2:_(s32) = COPY $a0 + %3:_(s32) = COPY $a1 + %4:_(s32) = COPY $a2 + %5:_(s32) = COPY $a3 + %0:_(s128) = G_MERGE_VALUES %2(s32), %3(s32), %4(s32), %5(s32) + %10:_(p0) = G_FRAME_INDEX %fixed-stack.3 + %6:_(s32) = G_LOAD %10(p0) :: (load 4 from %fixed-stack.3, align 0) + %11:_(p0) = G_FRAME_INDEX %fixed-stack.2 + %7:_(s32) = G_LOAD %11(p0) :: (load 4 from %fixed-stack.2, align 0) + %12:_(p0) = G_FRAME_INDEX %fixed-stack.1 + %8:_(s32) = G_LOAD %12(p0) :: (load 4 from %fixed-stack.1, align 0) + %13:_(p0) = G_FRAME_INDEX %fixed-stack.0 + %9:_(s32) = G_LOAD %13(p0) :: (load 4 from %fixed-stack.0, align 0) + %1:_(s128) = G_MERGE_VALUES %6(s32), %7(s32), %8(s32), %9(s32) + %14:_(s128) = G_SUB %1, %0 + %15:_(s32), %16:_(s32), %17:_(s32), %18:_(s32) = G_UNMERGE_VALUES %14(s128) + $v0 = COPY %15(s32) + $v1 = COPY %16(s32) + $a0 = COPY %17(s32) + $a1 = COPY %18(s32) + RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1 + +... diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll new file mode 100644 index 000000000000..e97fed213b09 --- /dev/null +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll @@ -0,0 +1,158 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32 + +define i32 @sub_i32(i32 %x, i32 %y) { +; MIPS32-LABEL: sub_i32: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: subu $2, $4, $5 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %z = sub i32 %x, %y + ret i32 %z +} + +define signext i8 @sub_i8_sext(i8 signext %a, i8 signext %b) { +; MIPS32-LABEL: sub_i8_sext: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: subu $4, $5, $4 +; MIPS32-NEXT: sll $4, $4, 24 +; MIPS32-NEXT: sra $2, $4, 24 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %sub = sub i8 %b, %a + ret i8 %sub +} + +define zeroext i8 @sub_i8_zext(i8 zeroext %a, i8 zeroext %b) { +; MIPS32-LABEL: sub_i8_zext: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: subu $4, $5, $4 +; MIPS32-NEXT: lui $5, 0 +; MIPS32-NEXT: ori $5, $5, 255 +; MIPS32-NEXT: and $2, $4, $5 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %sub = sub i8 %b, %a + ret i8 %sub +} + +define i8 @sub_i8_aext(i8 %a, i8 %b) { +; MIPS32-LABEL: sub_i8_aext: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: subu $2, $5, $4 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %sub = sub i8 %b, %a + ret i8 %sub +} + +define signext i16 @sub_i16_sext(i16 signext %a, i16 signext %b) { +; MIPS32-LABEL: sub_i16_sext: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: subu $4, $5, $4 +; MIPS32-NEXT: sll $4, $4, 16 +; MIPS32-NEXT: sra $2, $4, 16 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %sub = sub i16 %b, %a + ret i16 %sub +} + +define zeroext i16 @sub_i16_zext(i16 zeroext %a, i16 zeroext %b) { +; MIPS32-LABEL: sub_i16_zext: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: subu $4, $5, $4 +; MIPS32-NEXT: lui $5, 0 +; MIPS32-NEXT: ori $5, $5, 65535 +; MIPS32-NEXT: and $2, $4, $5 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %sub = sub i16 %b, %a + ret i16 %sub +} + +define i16 @sub_i16_aext(i16 %a, i16 %b) { +; MIPS32-LABEL: sub_i16_aext: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: subu $2, $5, $4 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %sub = sub i16 %b, %a + ret i16 %sub +} + +define i64 @sub_i64(i64 %a, i64 %b) { +; MIPS32-LABEL: sub_i64: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: subu $2, $6, $4 +; MIPS32-NEXT: sltu $4, $6, $4 +; MIPS32-NEXT: subu $5, $7, $5 +; MIPS32-NEXT: lui $6, 0 +; MIPS32-NEXT: ori $6, $6, 1 +; MIPS32-NEXT: and $4, $4, $6 +; MIPS32-NEXT: subu $3, $5, $4 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %sub = sub i64 %b, %a + ret i64 %sub +} + +define i128 @sub_i128(i128 %a, i128 %b) { +; MIPS32-LABEL: sub_i128: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $sp, 16 +; MIPS32-NEXT: lw $1, 0($1) +; MIPS32-NEXT: addiu $2, $sp, 20 +; MIPS32-NEXT: lw $2, 0($2) +; MIPS32-NEXT: addiu $3, $sp, 24 +; MIPS32-NEXT: lw $3, 0($3) +; MIPS32-NEXT: addiu $8, $sp, 28 +; MIPS32-NEXT: lw $8, 0($8) +; MIPS32-NEXT: subu $9, $1, $4 +; MIPS32-NEXT: sltu $1, $1, $4 +; MIPS32-NEXT: subu $4, $2, $5 +; MIPS32-NEXT: lui $10, 0 +; MIPS32-NEXT: ori $10, $10, 1 +; MIPS32-NEXT: and $10, $1, $10 +; MIPS32-NEXT: subu $4, $4, $10 +; MIPS32-NEXT: xor $10, $2, $5 +; MIPS32-NEXT: sltiu $10, $10, 1 +; MIPS32-NEXT: sltu $2, $2, $5 +; MIPS32-NEXT: lui $5, 0 +; MIPS32-NEXT: ori $5, $5, 1 +; MIPS32-NEXT: and $5, $10, $5 +; MIPS32-NEXT: movn $2, $1, $5 +; MIPS32-NEXT: subu $1, $3, $6 +; MIPS32-NEXT: lui $5, 0 +; MIPS32-NEXT: ori $5, $5, 1 +; MIPS32-NEXT: and $5, $2, $5 +; MIPS32-NEXT: subu $1, $1, $5 +; MIPS32-NEXT: xor $5, $3, $6 +; MIPS32-NEXT: sltiu $5, $5, 1 +; MIPS32-NEXT: sltu $3, $3, $6 +; MIPS32-NEXT: lui $6, 0 +; MIPS32-NEXT: ori $6, $6, 1 +; MIPS32-NEXT: and $5, $5, $6 +; MIPS32-NEXT: movn $3, $2, $5 +; MIPS32-NEXT: subu $2, $8, $7 +; MIPS32-NEXT: lui $5, 0 +; MIPS32-NEXT: ori $5, $5, 1 +; MIPS32-NEXT: and $3, $3, $5 +; MIPS32-NEXT: subu $5, $2, $3 +; MIPS32-NEXT: move $2, $9 +; MIPS32-NEXT: move $3, $4 +; MIPS32-NEXT: move $4, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %sub = sub i128 %b, %a + ret i128 %sub +} diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir new file mode 100644 index 000000000000..487024783e60 --- /dev/null +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir @@ -0,0 +1,30 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 +--- | + + define void @sub_i32(i32 %x, i32 %y) {entry: ret void} + +... +--- +name: sub_i32 +alignment: 2 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $a0, $a1 + + ; MIPS32-LABEL: name: sub_i32 + ; MIPS32: liveins: $a0, $a1 + ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1 + ; MIPS32: [[SUB:%[0-9]+]]:gprb(s32) = G_SUB [[COPY]], [[COPY1]] + ; MIPS32: $v0 = COPY [[SUB]](s32) + ; MIPS32: RetRA implicit $v0 + %0:_(s32) = COPY $a0 + %1:_(s32) = COPY $a1 + %2:_(s32) = G_SUB %0, %1 + $v0 = COPY %2(s32) + RetRA implicit $v0 + +...