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Fixup VST1.32 with writeback instruction. Also re-factor non-writeback version. 

llvm-svn: 153573
This commit is contained in:
Richard Barton 2012-03-28 10:18:11 +00:00
parent 772c88b887
commit 7ce39497b4
2 changed files with 21 additions and 21 deletions
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34
llvm/lib/Target/ARM/ARMInstrNEON.td
View File

@ -1938,20 +1938,11 @@ class VSTQQQQLNWBPseudo<InstrItinClass itin>
// VST1LN : Vector Store (single element from one lane) // VST1LN : Vector Store (single element from one lane)
class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty, class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
PatFrag StoreOp, SDNode ExtractOp> PatFrag StoreOp, SDNode ExtractOp, Operand AddrMode>
: NLdStLn<1, 0b00, op11_8, op7_4, (outs), : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
(ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane), (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane),
IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "", IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
[(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> { [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]> {
let Rm = 0b1111;
let DecoderMethod = "DecodeVST1LN";
}
class VST1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
PatFrag StoreOp, SDNode ExtractOp>
: NLdStLn<1, 0b00, op11_8, op7_4, (outs),
(ins addrmode6oneL32:$Rn, DPR:$Vd, nohash_imm:$lane),
IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
[(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn)]>{
let Rm = 0b1111; let Rm = 0b1111;
let DecoderMethod = "DecodeVST1LN"; let DecoderMethod = "DecodeVST1LN";
} }
@ -1962,16 +1953,17 @@ class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
} }
def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8, def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
NEONvgetlaneu> { NEONvgetlaneu, addrmode6> {
let Inst{7-5} = lane{2-0}; let Inst{7-5} = lane{2-0};
} }
def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16, def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
NEONvgetlaneu> { NEONvgetlaneu, addrmode6> {
let Inst{7-6} = lane{1-0}; let Inst{7-6} = lane{1-0};
let Inst{4} = Rn{5}; let Inst{4} = Rn{5};
} }
def VST1LNd32 : VST1LN32<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> { def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt,
addrmode6oneL32> {
let Inst{7} = lane{0}; let Inst{7} = lane{0};
let Inst{5-4} = Rn{5-4}; let Inst{5-4} = Rn{5-4};
} }
@ -1987,14 +1979,14 @@ def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
// ...with address register writeback: // ...with address register writeback:
class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty, class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
PatFrag StoreOp, SDNode ExtractOp> PatFrag StoreOp, SDNode ExtractOp, Operand AdrMode>
: NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
(ins addrmode6:$Rn, am6offset:$Rm, (ins AdrMode:$Rn, am6offset:$Rm,
DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt, DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
"\\{$Vd[$lane]\\}, $Rn$Rm", "\\{$Vd[$lane]\\}, $Rn$Rm",
"$Rn.addr = $wb", "$Rn.addr = $wb",
[(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
addrmode6:$Rn, am6offset:$Rm))]> { AdrMode:$Rn, am6offset:$Rm))]> {
let DecoderMethod = "DecodeVST1LN"; let DecoderMethod = "DecodeVST1LN";
} }
class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp> class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
@ -2004,16 +1996,16 @@ class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
} }
def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8, def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
NEONvgetlaneu> { NEONvgetlaneu, addrmode6> {
let Inst{7-5} = lane{2-0}; let Inst{7-5} = lane{2-0};
} }
def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16, def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
NEONvgetlaneu> { NEONvgetlaneu, addrmode6> {
let Inst{7-6} = lane{1-0}; let Inst{7-6} = lane{1-0};
let Inst{4} = Rn{5}; let Inst{4} = Rn{5};
} }
def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store, def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
extractelt> { extractelt, addrmode6oneL32> {
let Inst{7} = lane{0}; let Inst{7} = lane{0};
let Inst{5-4} = Rn{5-4}; let Inst{5-4} = Rn{5-4};
} }

8
llvm/test/MC/ARM/neon-vst-encoding.s
View File

@ -268,3 +268,11 @@
@ rdar://11082188 @ rdar://11082188
vst2.8 {d8, d10}, [r4] vst2.8 {d8, d10}, [r4]
@ CHECK: vst2.8 {d8, d10}, [r4] @ encoding: [0x0f,0x89,0x04,0xf4] @ CHECK: vst2.8 {d8, d10}, [r4] @ encoding: [0x0f,0x89,0x04,0xf4]
vst1.32 {d9[1]}, [r3, :32]
vst1.32 {d27[1]}, [r9, :32]!
vst1.32 {d27[1]}, [r3, :32], r5
@ CHECK: vst1.32 {d9[1]}, [r3, :32] @ encoding: [0xbf,0x98,0x83,0xf4]
@ CHECK: vst1.32 {d27[1]}, [r9, :32]! @ encoding: [0xbd,0xb8,0xc9,0xf4]
@ CHECK: vst1.32 {d27[1]}, [r3, :32], r5 @ encoding: [0xb5,0xb8,0xc3,0xf4]