forked from OSchip/llvm-project
[NFC][TTI] Add Alignment for isLegalMasked[Gather/Scatter]
Add an extra parameter so alignment can be taken under consideration in gather/scatter legalization. Differential Revision: https://reviews.llvm.org/D71610
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@ -597,9 +597,9 @@ public:
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bool isLegalNTLoad(Type *DataType, Align Alignment) const;
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/// Return true if the target supports masked scatter.
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bool isLegalMaskedScatter(Type *DataType) const;
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bool isLegalMaskedScatter(Type *DataType, MaybeAlign Alignment) const;
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/// Return true if the target supports masked gather.
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bool isLegalMaskedGather(Type *DataType) const;
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bool isLegalMaskedGather(Type *DataType, MaybeAlign Alignment) const;
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/// Return true if the target supports masked compress store.
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bool isLegalMaskedCompressStore(Type *DataType) const;
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@ -1237,8 +1237,8 @@ public:
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virtual bool isLegalMaskedLoad(Type *DataType, MaybeAlign Alignment) = 0;
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virtual bool isLegalNTStore(Type *DataType, Align Alignment) = 0;
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virtual bool isLegalNTLoad(Type *DataType, Align Alignment) = 0;
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virtual bool isLegalMaskedScatter(Type *DataType) = 0;
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virtual bool isLegalMaskedGather(Type *DataType) = 0;
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virtual bool isLegalMaskedScatter(Type *DataType, MaybeAlign Alignment) = 0;
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virtual bool isLegalMaskedGather(Type *DataType, MaybeAlign Alignment) = 0;
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virtual bool isLegalMaskedCompressStore(Type *DataType) = 0;
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virtual bool isLegalMaskedExpandLoad(Type *DataType) = 0;
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virtual bool hasDivRemOp(Type *DataType, bool IsSigned) = 0;
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@ -1537,11 +1537,11 @@ public:
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bool isLegalNTLoad(Type *DataType, Align Alignment) override {
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return Impl.isLegalNTLoad(DataType, Alignment);
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}
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bool isLegalMaskedScatter(Type *DataType) override {
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return Impl.isLegalMaskedScatter(DataType);
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bool isLegalMaskedScatter(Type *DataType, MaybeAlign Alignment) override {
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return Impl.isLegalMaskedScatter(DataType, Alignment);
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}
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bool isLegalMaskedGather(Type *DataType) override {
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return Impl.isLegalMaskedGather(DataType);
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bool isLegalMaskedGather(Type *DataType, MaybeAlign Alignment) override {
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return Impl.isLegalMaskedGather(DataType, Alignment);
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}
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bool isLegalMaskedCompressStore(Type *DataType) override {
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return Impl.isLegalMaskedCompressStore(DataType);
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@ -272,9 +272,13 @@ public:
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return Alignment >= DataSize && isPowerOf2_32(DataSize);
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}
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bool isLegalMaskedScatter(Type *DataType) { return false; }
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bool isLegalMaskedScatter(Type *DataType, MaybeAlign Alignment) {
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return false;
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}
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bool isLegalMaskedGather(Type *DataType) { return false; }
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bool isLegalMaskedGather(Type *DataType, MaybeAlign Alignment) {
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return false;
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}
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bool isLegalMaskedCompressStore(Type *DataType) { return false; }
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@ -315,12 +315,14 @@ bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
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return TTIImpl->isLegalNTLoad(DataType, Alignment);
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}
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bool TargetTransformInfo::isLegalMaskedGather(Type *DataType) const {
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return TTIImpl->isLegalMaskedGather(DataType);
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bool TargetTransformInfo::isLegalMaskedGather(Type *DataType,
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MaybeAlign Alignment) const {
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return TTIImpl->isLegalMaskedGather(DataType, Alignment);
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}
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bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType) const {
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return TTIImpl->isLegalMaskedScatter(DataType);
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bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType,
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MaybeAlign Alignment) const {
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return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
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}
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bool TargetTransformInfo::isLegalMaskedCompressStore(Type *DataType) const {
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@ -849,21 +849,20 @@ bool ScalarizeMaskedMemIntrin::optimizeCallInst(CallInst *CI,
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bool &ModifiedDT) {
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IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI);
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if (II) {
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unsigned Alignment;
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switch (II->getIntrinsicID()) {
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default:
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break;
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case Intrinsic::masked_load: {
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// Scalarize unsupported vector masked load
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unsigned Alignment =
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cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
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Alignment = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
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if (TTI->isLegalMaskedLoad(CI->getType(), MaybeAlign(Alignment)))
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return false;
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scalarizeMaskedLoad(CI, ModifiedDT);
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return true;
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}
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case Intrinsic::masked_store: {
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unsigned Alignment =
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cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue();
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Alignment = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue();
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if (TTI->isLegalMaskedStore(CI->getArgOperand(0)->getType(),
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MaybeAlign(Alignment)))
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return false;
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@ -871,12 +870,15 @@ bool ScalarizeMaskedMemIntrin::optimizeCallInst(CallInst *CI,
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return true;
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}
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case Intrinsic::masked_gather:
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if (TTI->isLegalMaskedGather(CI->getType()))
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Alignment = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
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if (TTI->isLegalMaskedGather(CI->getType(), MaybeAlign(Alignment)))
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return false;
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scalarizeMaskedGather(CI, ModifiedDT);
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return true;
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case Intrinsic::masked_scatter:
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if (TTI->isLegalMaskedScatter(CI->getArgOperand(0)->getType()))
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Alignment = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue();
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if (TTI->isLegalMaskedScatter(CI->getArgOperand(0)->getType(),
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MaybeAlign(Alignment)))
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return false;
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scalarizeMaskedScatter(CI, ModifiedDT);
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return true;
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@ -159,6 +159,10 @@ public:
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return isLegalMaskedLoad(DataTy, Alignment);
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}
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bool isLegalMaskedGather(Type *Ty, MaybeAlign Alignment) { return false; }
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bool isLegalMaskedScatter(Type *Ty, MaybeAlign Alignment) { return false; }
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int getMemcpyCost(const Instruction *I);
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int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp);
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@ -3296,8 +3296,10 @@ int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy,
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unsigned AddressSpace = PtrTy->getAddressSpace();
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bool Scalarize = false;
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if ((Opcode == Instruction::Load && !isLegalMaskedGather(SrcVTy)) ||
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(Opcode == Instruction::Store && !isLegalMaskedScatter(SrcVTy)))
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if ((Opcode == Instruction::Load &&
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!isLegalMaskedGather(SrcVTy, MaybeAlign(Alignment))) ||
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(Opcode == Instruction::Store &&
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!isLegalMaskedScatter(SrcVTy, MaybeAlign(Alignment))))
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Scalarize = true;
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// Gather / Scatter for vector 2 is not profitable on KNL / SKX
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// Vector-4 of gather/scatter instruction does not exist on KNL.
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@ -3420,7 +3422,7 @@ bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) {
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return isLegalMaskedExpandLoad(DataTy);
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}
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bool X86TTIImpl::isLegalMaskedGather(Type *DataTy) {
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bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, MaybeAlign Alignment) {
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// Some CPUs have better gather performance than others.
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// TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only
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// enable gather with a -march.
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@ -3458,11 +3460,11 @@ bool X86TTIImpl::isLegalMaskedGather(Type *DataTy) {
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return IntWidth == 32 || IntWidth == 64;
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}
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bool X86TTIImpl::isLegalMaskedScatter(Type *DataType) {
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bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, MaybeAlign Alignment) {
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// AVX2 doesn't support scatter
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if (!ST->hasAVX512())
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return false;
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return isLegalMaskedGather(DataType);
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return isLegalMaskedGather(DataType, Alignment);
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}
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bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) {
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@ -189,8 +189,8 @@ public:
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bool isLegalMaskedStore(Type *DataType, MaybeAlign Alignment);
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bool isLegalNTLoad(Type *DataType, Align Alignment);
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bool isLegalNTStore(Type *DataType, Align Alignment);
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bool isLegalMaskedGather(Type *DataType);
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bool isLegalMaskedScatter(Type *DataType);
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bool isLegalMaskedGather(Type *DataType, MaybeAlign Alignment);
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bool isLegalMaskedScatter(Type *DataType, MaybeAlign Alignment);
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bool isLegalMaskedExpandLoad(Type *DataType);
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bool isLegalMaskedCompressStore(Type *DataType);
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bool hasDivRemOp(Type *DataType, bool IsSigned);
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@ -1210,14 +1210,14 @@ public:
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/// Returns true if the target machine supports masked scatter operation
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/// for the given \p DataType.
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bool isLegalMaskedScatter(Type *DataType) {
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return TTI.isLegalMaskedScatter(DataType);
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bool isLegalMaskedScatter(Type *DataType, MaybeAlign Alignment) {
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return TTI.isLegalMaskedScatter(DataType, Alignment);
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}
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/// Returns true if the target machine supports masked gather operation
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/// for the given \p DataType.
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bool isLegalMaskedGather(Type *DataType) {
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return TTI.isLegalMaskedGather(DataType);
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bool isLegalMaskedGather(Type *DataType, MaybeAlign Alignment) {
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return TTI.isLegalMaskedGather(DataType, Alignment);
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}
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/// Returns true if the target machine can represent \p V as a masked gather
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@ -1228,7 +1228,9 @@ public:
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if (!LI && !SI)
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return false;
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auto *Ty = getMemInstValueType(V);
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return (LI && isLegalMaskedGather(Ty)) || (SI && isLegalMaskedScatter(Ty));
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MaybeAlign Align = getLoadStoreAlignment(V);
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return (LI && isLegalMaskedGather(Ty, Align)) ||
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(SI && isLegalMaskedScatter(Ty, Align));
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}
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/// Returns true if \p I is an instruction that will be scalarized with
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@ -4579,9 +4581,10 @@ bool LoopVectorizationCostModel::isScalarWithPredication(Instruction *I, unsigne
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return WideningDecision == CM_Scalarize;
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}
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const MaybeAlign Alignment = getLoadStoreAlignment(I);
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return isa<LoadInst>(I) ?
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!(isLegalMaskedLoad(Ty, Ptr, Alignment) || isLegalMaskedGather(Ty))
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: !(isLegalMaskedStore(Ty, Ptr, Alignment) || isLegalMaskedScatter(Ty));
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return isa<LoadInst>(I) ? !(isLegalMaskedLoad(Ty, Ptr, Alignment) ||
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isLegalMaskedGather(Ty, Alignment))
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: !(isLegalMaskedStore(Ty, Ptr, Alignment) ||
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isLegalMaskedScatter(Ty, Alignment));
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}
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case Instruction::UDiv:
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case Instruction::SDiv:
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