forked from OSchip/llvm-project
parent
d84a63398e
commit
7ccd1b86bd
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@ -1,8 +1,4 @@
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; RUN: llc < %s -march=x86 -mattr=+sse2 > %t
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; RUN: grep shll %t | grep 12
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; RUN: grep pslldq %t | grep 12
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; RUN: grep psrldq %t | grep 8
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; RUN: grep psrldq %t | grep 12
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; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
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; There are no MMX operations in @t1
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define void @t1(i32 %a, x86_mmx* %P) nounwind {
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@ -12,22 +8,36 @@ define void @t1(i32 %a, x86_mmx* %P) nounwind {
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%tmp23 = bitcast <2 x i32> %tmp22 to x86_mmx
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store x86_mmx %tmp23, x86_mmx* %P
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ret void
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; CHECK: t1:
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; CHECK-NOT: %mm
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; CHECK: shll $12
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; CHECK-NOT: %mm
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}
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define <4 x float> @t2(<4 x float>* %P) nounwind {
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%tmp1 = load <4 x float>* %P
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%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 4, i32 4, i32 4, i32 0 >
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ret <4 x float> %tmp2
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; CHECK: t2:
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; CHECK: pslldq $12
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}
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define <4 x float> @t3(<4 x float>* %P) nounwind {
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%tmp1 = load <4 x float>* %P
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%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 2, i32 3, i32 4, i32 4 >
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ret <4 x float> %tmp2
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; CHECK: t3:
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; CHECK: psrldq $8
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}
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define <4 x float> @t4(<4 x float>* %P) nounwind {
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%tmp1 = load <4 x float>* %P
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%tmp2 = shufflevector <4 x float> zeroinitializer, <4 x float> %tmp1, <4 x i32> < i32 7, i32 0, i32 0, i32 0 >
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ret <4 x float> %tmp2
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; CHECK: t4:
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; CHECK: psrldq $12
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}
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