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Reduce uses of getRegClass 

llvm-svn: 15973
This commit is contained in:
Chris Lattner 2004-08-21 20:13:52 +00:00
parent a440d5b081
commit 7c98308013
1 changed files with 11 additions and 14 deletions
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25
llvm/lib/Target/X86/X86RegisterInfo.cpp
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@ -44,13 +44,13 @@ namespace {
X86RegisterInfo::X86RegisterInfo() X86RegisterInfo::X86RegisterInfo()
: X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {} : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
static unsigned getIdx(const TargetRegisterClass *RC) { static unsigned getIdx(unsigned SpillSize) {
switch (RC->getSize()) { switch (SpillSize) {
default: assert(0 && "Invalid data size!"); default: assert(0 && "Invalid data size!");
case 1: return 0; case 8: return 0;
case 2: return 1; case 16: return 1;
case 4: return 2; case 32: return 2;
case 10: return 3; case 80: return 3;
} }
} }
@ -59,10 +59,8 @@ void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
unsigned SrcReg, int FrameIdx) const { unsigned SrcReg, int FrameIdx) const {
static const unsigned Opcode[] = static const unsigned Opcode[] =
{ X86::MOV8mr, X86::MOV16mr, X86::MOV32mr, X86::FSTP80m }; { X86::MOV8mr, X86::MOV16mr, X86::MOV32mr, X86::FSTP80m };
const TargetRegisterClass *RC = getRegClass(SrcReg); unsigned Idx = getIdx(getSpillSize(SrcReg));
MachineInstr *I = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5), addFrameReference(BuildMI(MBB, MI, Opcode[Idx], 5), FrameIdx).addReg(SrcReg);
FrameIdx).addReg(SrcReg);
MBB.insert(MI, I);
} }
void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
@ -70,9 +68,8 @@ void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
unsigned DestReg, int FrameIdx)const{ unsigned DestReg, int FrameIdx)const{
static const unsigned Opcode[] = static const unsigned Opcode[] =
{ X86::MOV8rm, X86::MOV16rm, X86::MOV32rm, X86::FLD80m }; { X86::MOV8rm, X86::MOV16rm, X86::MOV32rm, X86::FLD80m };
const TargetRegisterClass *RC = getRegClass(DestReg); unsigned Idx = getIdx(getSpillSize(DestReg));
unsigned OC = Opcode[getIdx(RC)]; addFrameReference(BuildMI(MBB, MI, Opcode[Idx], 4, DestReg), FrameIdx);
MBB.insert(MI, addFrameReference(BuildMI(OC, 4, DestReg), FrameIdx));
} }
void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
@ -81,7 +78,7 @@ void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
const TargetRegisterClass *RC) const { const TargetRegisterClass *RC) const {
static const unsigned Opcode[] = static const unsigned Opcode[] =
{ X86::MOV8rr, X86::MOV16rr, X86::MOV32rr, X86::FpMOV }; { X86::MOV8rr, X86::MOV16rr, X86::MOV32rr, X86::FpMOV };
MBB.insert(MI, BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg)); BuildMI(MBB, MI, Opcode[getIdx(RC->getSize()*8)], 1, DestReg).addReg(SrcReg);
} }
static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex, static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex,