[AggressiveInstCombine] Update tests to use opaque pointers (NFC)

Update performed using (without manual fixup):
https://gist.github.com/nikic/98357b71fd67756b0f064c9517b62a34

llvm/test/Transforms/AggressiveInstCombine/funnel.ll

@@ -442,7 +442,7 @@ end:
 ; being cautious not to cause a potential perf pessimization for
 ; targets that do not have a fshate instruction.
 
-define i32 @could_be_fshr(i32 %a, i32 %b, i32 %c, i32* %p) {
+define i32 @could_be_fshr(i32 %a, i32 %b, i32 %c, ptr %p) {
 ; CHECK-LABEL: @could_be_fshr(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[C:%.*]], 0
@@ -452,7 +452,7 @@ define i32 @could_be_fshr(i32 %a, i32 %b, i32 %c, i32* %p) {
 ; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[A:%.*]], [[SUB]]
 ; CHECK-NEXT:    [[SHR:%.*]] = lshr i32 [[B:%.*]], [[C]]
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHL]], [[SHR]]
-; CHECK-NEXT:    store i32 [[OR]], i32* [[P:%.*]], align 4
+; CHECK-NEXT:    store i32 [[OR]], ptr [[P:%.*]], align 4
 ; CHECK-NEXT:    br label [[END]]
 ; CHECK:       end:
 ; CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[B]], [[ENTRY:%.*]] ], [ [[OR]], [[FSHBB]] ]
@@ -467,7 +467,7 @@ fshbb:
   %shl = shl i32 %a, %sub
   %shr = lshr i32 %b, %c
   %or = or i32 %shl, %shr
-  store i32 %or, i32* %p
+  store i32 %or, ptr %p
   br label %end
 
 end:
@@ -484,13 +484,13 @@ declare i32 @f(...)
 define i32 @PR48068() {
 ; CHECK-LABEL: @PR48068(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[CALL:%.*]] = call i32 bitcast (i32 (...)* @i to i32 ()*)()
-; CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* @a, align 4
+; CHECK-NEXT:    [[CALL:%.*]] = call i32 @i()
+; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr @a, align 4
 ; CHECK-NEXT:    [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP0]], 0
 ; CHECK-NEXT:    br i1 [[TOBOOL_NOT]], label [[IF_END:%.*]], label [[IF_THEN:%.*]]
 ; CHECK:       if.then:
 ; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[CALL]], [[TMP0]]
-; CHECK-NEXT:    [[CALL_I:%.*]] = call i32 bitcast (i32 (...)* @f to i32 ()*)()
+; CHECK-NEXT:    [[CALL_I:%.*]] = call i32 @f()
 ; CHECK-NEXT:    [[SUB_I:%.*]] = sub nsw i32 32, [[TMP0]]
 ; CHECK-NEXT:    [[SHR_I:%.*]] = lshr i32 [[CALL_I]], [[SUB_I]]
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHL]], [[SHR_I]]
@@ -500,14 +500,14 @@ define i32 @PR48068() {
 ; CHECK-NEXT:    ret i32 [[H_0]]
 ;
 entry:
-  %call = call i32 bitcast (i32 (...)* @i to i32 ()*)()
-  %0 = load i32, i32* @a, align 4
+  %call = call i32 @i()
+  %0 = load i32, ptr @a, align 4
   %tobool.not = icmp eq i32 %0, 0
   br i1 %tobool.not, label %if.end, label %if.then
 
 if.then:                                          ; preds = %entry
   %shl = shl i32 %call, %0
-  %call.i = call i32 bitcast (i32 (...)* @f to i32 ()*)()
+  %call.i = call i32 @f()
   %sub.i = sub nsw i32 32, %0
   %shr.i = lshr i32 %call.i, %sub.i
   %or = or i32 %shl, %shr.i

llvm/test/Transforms/AggressiveInstCombine/pr50555.ll

@@ -1,23 +1,23 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -passes=aggressive-instcombine -S | FileCheck %s
 
-define void @trunc_one_add(i16* %a, i8 %b) {
+define void @trunc_one_add(ptr %a, i8 %b) {
 ; CHECK-LABEL: @trunc_one_add(
 ; CHECK-NEXT:    [[ZEXT:%.*]] = zext i8 [[B:%.*]] to i16
 ; CHECK-NEXT:    [[SHR:%.*]] = lshr i16 [[ZEXT]], 1
 ; CHECK-NEXT:    [[ADD:%.*]] = add i16 [[ZEXT]], [[SHR]]
-; CHECK-NEXT:    store i16 [[ADD]], i16* [[A:%.*]], align 2
+; CHECK-NEXT:    store i16 [[ADD]], ptr [[A:%.*]], align 2
 ; CHECK-NEXT:    ret void
 ;
   %zext = zext i8 %b to i32
   %shr = lshr i32 %zext, 1
   %add = add nsw i32 %zext, %shr
   %trunc = trunc i32 %add to i16
-  store i16 %trunc, i16* %a, align 2
+  store i16 %trunc, ptr %a, align 2
   ret void
 }
 
-define void @trunc_two_adds(i16* %a, i8 %b, i8 %c) {
+define void @trunc_two_adds(ptr %a, i8 %b, i8 %c) {
 ; CHECK-LABEL: @trunc_two_adds(
 ; CHECK-NEXT:    [[ZEXT1:%.*]] = zext i8 [[B:%.*]] to i16
 ; CHECK-NEXT:    [[ZEXT2:%.*]] = zext i8 [[C:%.*]] to i16
@@ -25,7 +25,7 @@ define void @trunc_two_adds(i16* %a, i8 %b, i8 %c) {
 ; CHECK-NEXT:    [[SHR1:%.*]] = lshr i16 [[ADD1]], 1
 ; CHECK-NEXT:    [[ADD2:%.*]] = add i16 [[ADD1]], [[SHR1]]
 ; CHECK-NEXT:    [[SHR2:%.*]] = lshr i16 [[ADD2]], 2
-; CHECK-NEXT:    store i16 [[SHR2]], i16* [[A:%.*]], align 2
+; CHECK-NEXT:    store i16 [[SHR2]], ptr [[A:%.*]], align 2
 ; CHECK-NEXT:    ret void
 ;
   %zext1 = zext i8 %b to i32
@@ -35,6 +35,6 @@ define void @trunc_two_adds(i16* %a, i8 %b, i8 %c) {
   %add2 = add nuw nsw i32 %add1, %shr1
   %shr2 = lshr i32 %add2, 2
   %trunc = trunc i32 %shr2 to i16
-  store i16 %trunc, i16* %a, align 2
+  store i16 %trunc, ptr %a, align 2
   ret void
 }

llvm/test/Transforms/AggressiveInstCombine/rotate.ll

@@ -437,7 +437,7 @@ end:
 ; being cautious not to cause a potential perf pessimization for
 ; targets that do not have a rotate instruction.
 
-define i32 @could_be_rotr(i32 %a, i32 %b, i32* %p) {
+define i32 @could_be_rotr(i32 %a, i32 %b, ptr %p) {
 ; CHECK-LABEL: @could_be_rotr(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[B:%.*]], 0
@@ -447,7 +447,7 @@ define i32 @could_be_rotr(i32 %a, i32 %b, i32* %p) {
 ; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[A:%.*]], [[SUB]]
 ; CHECK-NEXT:    [[SHR:%.*]] = lshr i32 [[A]], [[B]]
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHL]], [[SHR]]
-; CHECK-NEXT:    store i32 [[OR]], i32* [[P:%.*]], align 4
+; CHECK-NEXT:    store i32 [[OR]], ptr [[P:%.*]], align 4
 ; CHECK-NEXT:    br label [[END]]
 ; CHECK:       end:
 ; CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[A]], [[ENTRY:%.*]] ], [ [[OR]], [[ROTBB]] ]
@@ -462,7 +462,7 @@ rotbb:
   %shl = shl i32 %a, %sub
   %shr = lshr i32 %a, %b
   %or = or i32 %shl, %shr
-  store i32 %or, i32* %p
+  store i32 %or, ptr %p
   br label %end
 
 end:

llvm/test/Transforms/AggressiveInstCombine/trunc_ashr.ll

@@ -103,7 +103,7 @@ define i32 @ashr_check_no_overflow(i32 %x, i16 %amt) {
   ret i32 %trunc
 }
 
-define void @ashr_big_dag(i16* %a, i8 %b, i8 %c) {
+define void @ashr_big_dag(ptr %a, i8 %b, i8 %c) {
 ; CHECK-LABEL: @ashr_big_dag(
 ; CHECK-NEXT:    [[ZEXT1:%.*]] = zext i8 [[B:%.*]] to i16
 ; CHECK-NEXT:    [[ZEXT2:%.*]] = zext i8 [[C:%.*]] to i16
@@ -113,7 +113,7 @@ define void @ashr_big_dag(i16* %a, i8 %b, i8 %c) {
 ; CHECK-NEXT:    [[ADD2:%.*]] = add i16 [[ADD1]], [[SHR1]]
 ; CHECK-NEXT:    [[SFT2:%.*]] = and i16 [[ADD2]], 7
 ; CHECK-NEXT:    [[SHR2:%.*]] = ashr i16 [[ADD2]], [[SFT2]]
-; CHECK-NEXT:    store i16 [[SHR2]], i16* [[A:%.*]], align 2
+; CHECK-NEXT:    store i16 [[SHR2]], ptr [[A:%.*]], align 2
 ; CHECK-NEXT:    ret void
 ;
   %zext1 = zext i8 %b to i32
@@ -125,7 +125,7 @@ define void @ashr_big_dag(i16* %a, i8 %b, i8 %c) {
   %sft2 = and i32 %add2, 7
   %shr2 = ashr i32 %add2, %sft2
   %trunc = trunc i32 %shr2 to i16
-  store i16 %trunc, i16* %a, align 2
+  store i16 %trunc, ptr %a, align 2
   ret void
 }
 

llvm/test/Transforms/AggressiveInstCombine/trunc_lshr.ll

@@ -87,7 +87,7 @@ define i32 @lshr_check_no_overflow(i32 %x, i16 %amt) {
   ret i32 %trunc
 }
 
-define void @lshr_big_dag(i16* %a, i8 %b, i8 %c) {
+define void @lshr_big_dag(ptr %a, i8 %b, i8 %c) {
 ; CHECK-LABEL: @lshr_big_dag(
 ; CHECK-NEXT:    [[ZEXT1:%.*]] = zext i8 [[B:%.*]] to i16
 ; CHECK-NEXT:    [[ZEXT2:%.*]] = zext i8 [[C:%.*]] to i16
@@ -97,7 +97,7 @@ define void @lshr_big_dag(i16* %a, i8 %b, i8 %c) {
 ; CHECK-NEXT:    [[ADD2:%.*]] = add i16 [[ADD1]], [[SHR1]]
 ; CHECK-NEXT:    [[SFT2:%.*]] = and i16 [[ADD2]], 7
 ; CHECK-NEXT:    [[SHR2:%.*]] = lshr i16 [[ADD2]], [[SFT2]]
-; CHECK-NEXT:    store i16 [[SHR2]], i16* [[A:%.*]], align 2
+; CHECK-NEXT:    store i16 [[SHR2]], ptr [[A:%.*]], align 2
 ; CHECK-NEXT:    ret void
 ;
   %zext1 = zext i8 %b to i32
@@ -109,7 +109,7 @@ define void @lshr_big_dag(i16* %a, i8 %b, i8 %c) {
   %sft2 = and i32 %add2, 7
   %shr2 = lshr i32 %add2, %sft2
   %trunc = trunc i32 %shr2 to i16
-  store i16 %trunc, i16* %a, align 2
+  store i16 %trunc, ptr %a, align 2
   ret void
 }