forked from OSchip/llvm-project
[ARM] Fix lsrl with a 128/256 bit shift amount or a shift of 32
This patch fixes shifts by a 128/256 bit shift amount. It also fixes codegen for shifts of 32 by delegating to LLVM's default optimisation instead of emitting a long shift. Tests that used to generate long shifts of 32 are updated to check for the more optimised codegen. Differential revision: https://reviews.llvm.org/D66519 llvm-svn: 369626
This commit is contained in:
Sam Tebbs
parent
36162014c4
commit
7c6b229204
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@ -5938,14 +5938,15 @@ static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
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unsigned ShPartsOpc = ARMISD::LSLL;
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ConstantSDNode *Con = dyn_cast<ConstantSDNode>(ShAmt);
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// If the shift amount is greater than 32 then do the default optimisation
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if (Con && Con->getZExtValue() > 32)
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// If the shift amount is greater than 32 or has a greater bitwidth than 64
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// then do the default optimisation
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if (ShAmt->getValueType(0).getSizeInBits() > 64 ||
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(Con && Con->getZExtValue() >= 32))
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return SDValue();
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// Extract the lower 32 bits of the shift amount if it's an i64
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if (ShAmt->getValueType(0) == MVT::i64)
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ShAmt = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, ShAmt,
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DAG.getConstant(0, dl, MVT::i32));
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// Extract the lower 32 bits of the shift amount if it's not an i32
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if (ShAmt->getValueType(0) != MVT::i32)
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ShAmt = DAG.getZExtOrTrunc(ShAmt, dl, MVT::i32);
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if (ShOpc == ISD::SRL) {
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if (!Con)
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@ -52,7 +52,8 @@ entry:
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define i64 @shift_left_imm_big2(i64 %x) {
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; CHECK-MVE-LABEL: shift_left_imm_big2:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: lsll r0, r1, #32
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; CHECK-MVE-NEXT: mov r1, r0
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; CHECK-MVE-NEXT: movs r0, #0
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: shift_left_imm_big2:
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@ -128,7 +129,8 @@ entry:
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define i64 @shift_right_imm_big2(i64 %x) {
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; CHECK-MVE-LABEL: shift_right_imm_big2:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: lsrl r0, r1, #32
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; CHECK-MVE-NEXT: mov r0, r1
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; CHECK-MVE-NEXT: movs r1, #0
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: shift_right_imm_big2:
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@ -219,3 +221,62 @@ entry:
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store i40 %bf.clear, i40* %0, align 1
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ret void
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}
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%struct.a = type { i96 }
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define void @lsll_128bit_shift(%struct.a* nocapture %x) local_unnamed_addr #0 {
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; CHECK-MVE-LABEL: lsll_128bit_shift:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: movs r1, #0
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; CHECK-MVE-NEXT: strd r1, r1, [r0]
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; CHECK-MVE-NEXT: str r1, [r0, #8]
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: lsll_128bit_shift:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: movs r1, #0
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; CHECK-NON-MVE-NEXT: str r1, [r0]
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; CHECK-NON-MVE-NEXT: str r1, [r0, #4]
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; CHECK-NON-MVE-NEXT: str r1, [r0, #8]
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; CHECK-NON-MVE-NEXT: bx lr
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entry:
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%0 = bitcast %struct.a* %x to i128*
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%bf.load = load i128, i128* %0, align 8
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%bf.clear4 = and i128 %bf.load, -79228162514264337593543950336
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store i128 %bf.clear4, i128* %0, align 8
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ret void
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}
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%struct.b = type { i184 }
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define void @lsll_256bit_shift(%struct.b* nocapture %x) local_unnamed_addr #0 {
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; CHECK-MVE-LABEL: lsll_256bit_shift:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: movs r1, #0
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; CHECK-MVE-NEXT: str r1, [r0, #16]
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; CHECK-MVE-NEXT: strd r1, r1, [r0, #8]
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; CHECK-MVE-NEXT: strd r1, r1, [r0]
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; CHECK-MVE-NEXT: ldrb r1, [r0, #23]
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; CHECK-MVE-NEXT: lsls r1, r1, #24
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; CHECK-MVE-NEXT: str r1, [r0, #20]
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: lsll_256bit_shift:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: movs r1, #0
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; CHECK-NON-MVE-NEXT: str r1, [r0, #16]
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; CHECK-NON-MVE-NEXT: str r1, [r0, #8]
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; CHECK-NON-MVE-NEXT: str r1, [r0, #12]
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; CHECK-NON-MVE-NEXT: str r1, [r0]
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; CHECK-NON-MVE-NEXT: str r1, [r0, #4]
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; CHECK-NON-MVE-NEXT: ldrb r1, [r0, #23]
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; CHECK-NON-MVE-NEXT: lsls r1, r1, #24
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; CHECK-NON-MVE-NEXT: str r1, [r0, #20]
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; CHECK-NON-MVE-NEXT: bx lr
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entry:
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%0 = bitcast %struct.b* %x to i192*
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%bf.load = load i192, i192* %0, align 8
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%bf.clear4 = and i192 %bf.load, -24519928653854221733733552434404946937899825954937634816
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store i192 %bf.clear4, i192* %0, align 8
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ret void
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}
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@ -40,43 +40,39 @@ entry:
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define arm_aapcs_vfpcc <2 x i64> @abs_v2i64(<2 x i64> %s1) {
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; CHECK-LABEL: abs_v2i64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
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; CHECK-NEXT: push {r4, r5, r6, r7, lr}
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; CHECK-NEXT: .save {r4, r5, r6, lr}
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; CHECK-NEXT: push {r4, r5, r6, lr}
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; CHECK-NEXT: vmov r12, s2
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: vmov r3, s3
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; CHECK-NEXT: vmov r1, s0
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; CHECK-NEXT: rsbs.w lr, r12, #0
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; CHECK-NEXT: sbc.w r5, r0, r3
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; CHECK-NEXT: cmp r3, #0
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; CHECK-NEXT: mov r2, lr
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; CHECK-NEXT: lsrl r2, r5, #32
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; CHECK-NEXT: mov.w r5, #0
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; CHECK-NEXT: it mi
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; CHECK-NEXT: movmi r5, #1
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; CHECK-NEXT: cmp r5, #0
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; CHECK-NEXT: it eq
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; CHECK-NEXT: moveq r2, r3
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; CHECK-NEXT: vmov r3, s1
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; CHECK-NEXT: rsbs r4, r1, #0
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; CHECK-NEXT: mov r6, r4
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; CHECK-NEXT: sbc.w r7, r0, r3
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; CHECK-NEXT: cmp r3, #0
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; CHECK-NEXT: lsrl r6, r7, #32
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; CHECK-NEXT: it mi
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; CHECK-NEXT: movmi r0, #1
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; CHECK-NEXT: movs r2, #0
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; CHECK-NEXT: vmov r0, s3
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; CHECK-NEXT: movs r1, #0
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; CHECK-NEXT: vmov r4, s0
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; CHECK-NEXT: rsbs.w r3, r12, #0
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; CHECK-NEXT: sbc.w lr, r2, r0
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: ite eq
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; CHECK-NEXT: moveq r6, r3
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; CHECK-NEXT: movne r1, r4
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; CHECK-NEXT: vmov.32 q0[0], r1
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; CHECK-NEXT: cmp r5, #0
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; CHECK-NEXT: vmov.32 q0[1], r6
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; CHECK-NEXT: it mi
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; CHECK-NEXT: movmi r1, #1
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: it eq
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; CHECK-NEXT: moveq lr, r12
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; CHECK-NEXT: vmov.32 q0[2], lr
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; CHECK-NEXT: vmov.32 q0[3], r2
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; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
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; CHECK-NEXT: moveq lr, r0
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; CHECK-NEXT: vmov r0, s1
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; CHECK-NEXT: rsbs r5, r4, #0
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; CHECK-NEXT: sbc.w r6, r2, r0
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: it mi
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; CHECK-NEXT: movmi r2, #1
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: itt eq
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; CHECK-NEXT: moveq r6, r0
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; CHECK-NEXT: moveq r5, r4
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; CHECK-NEXT: vmov.32 q0[0], r5
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; CHECK-NEXT: vmov.32 q0[1], r6
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: it eq
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; CHECK-NEXT: moveq r3, r12
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; CHECK-NEXT: vmov.32 q0[2], r3
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; CHECK-NEXT: vmov.32 q0[3], lr
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; CHECK-NEXT: pop {r4, r5, r6, pc}
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entry:
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%0 = icmp slt <2 x i64> %s1, zeroinitializer
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%1 = sub nsw <2 x i64> zeroinitializer, %s1
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@ -755,14 +755,12 @@ define arm_aapcs_vfpcc <2 x i64> @udiv_i64(<2 x i64> %in1, <2 x i64> %in2) {
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; CHECK-NEXT: vmov r2, s18
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; CHECK-NEXT: vmov r3, s19
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; CHECK-NEXT: vmov.32 q4[0], r0
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; CHECK-NEXT: lsrl r0, r1, #32
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; CHECK-NEXT: vmov.32 q4[1], r0
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; CHECK-NEXT: vmov.32 q4[1], r1
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; CHECK-NEXT: mov r0, r12
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; CHECK-NEXT: mov r1, lr
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; CHECK-NEXT: bl __aeabi_uldivmod
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; CHECK-NEXT: vmov.32 q4[2], r0
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; CHECK-NEXT: lsrl r0, r1, #32
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; CHECK-NEXT: vmov.32 q4[3], r0
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; CHECK-NEXT: vmov.32 q4[3], r1
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; CHECK-NEXT: vmov q0, q4
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; CHECK-NEXT: vpop {d8, d9, d10, d11}
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; CHECK-NEXT: pop {r7, pc}
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@ -790,14 +788,12 @@ define arm_aapcs_vfpcc <2 x i64> @sdiv_i64(<2 x i64> %in1, <2 x i64> %in2) {
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; CHECK-NEXT: vmov r2, s18
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; CHECK-NEXT: vmov r3, s19
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; CHECK-NEXT: vmov.32 q4[0], r0
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; CHECK-NEXT: lsrl r0, r1, #32
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; CHECK-NEXT: vmov.32 q4[1], r0
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; CHECK-NEXT: vmov.32 q4[1], r1
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; CHECK-NEXT: mov r0, r12
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; CHECK-NEXT: mov r1, lr
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; CHECK-NEXT: bl __aeabi_ldivmod
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; CHECK-NEXT: vmov.32 q4[2], r0
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; CHECK-NEXT: lsrl r0, r1, #32
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; CHECK-NEXT: vmov.32 q4[3], r0
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; CHECK-NEXT: vmov.32 q4[3], r1
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; CHECK-NEXT: vmov q0, q4
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; CHECK-NEXT: vpop {d8, d9, d10, d11}
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; CHECK-NEXT: pop {r7, pc}
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@ -382,14 +382,12 @@ define arm_aapcs_vfpcc <2 x i64> @foo_int64_float(<2 x double> %src) {
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; CHECK-NEXT: bl __aeabi_d2lz
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; CHECK-NEXT: vmov r2, r3, d9
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; CHECK-NEXT: vmov.32 q4[0], r0
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; CHECK-NEXT: lsrl r0, r1, #32
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; CHECK-NEXT: vmov.32 q4[1], r0
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; CHECK-NEXT: vmov.32 q4[1], r1
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: mov r1, r3
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; CHECK-NEXT: bl __aeabi_d2lz
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; CHECK-NEXT: vmov.32 q4[2], r0
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; CHECK-NEXT: lsrl r0, r1, #32
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; CHECK-NEXT: vmov.32 q4[3], r0
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; CHECK-NEXT: vmov.32 q4[3], r1
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; CHECK-NEXT: vmov q0, q4
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; CHECK-NEXT: vpop {d8, d9}
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; CHECK-NEXT: pop {r7, pc}
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@ -410,14 +408,12 @@ define arm_aapcs_vfpcc <2 x i64> @foo_uint64_float(<2 x double> %src) {
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; CHECK-NEXT: bl __aeabi_d2ulz
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; CHECK-NEXT: vmov r2, r3, d9
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; CHECK-NEXT: vmov.32 q4[0], r0
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; CHECK-NEXT: lsrl r0, r1, #32
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; CHECK-NEXT: vmov.32 q4[1], r0
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; CHECK-NEXT: vmov.32 q4[1], r1
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: mov r1, r3
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; CHECK-NEXT: bl __aeabi_d2ulz
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; CHECK-NEXT: vmov.32 q4[2], r0
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; CHECK-NEXT: lsrl r0, r1, #32
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; CHECK-NEXT: vmov.32 q4[3], r0
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; CHECK-NEXT: vmov.32 q4[3], r1
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; CHECK-NEXT: vmov q0, q4
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; CHECK-NEXT: vpop {d8, d9}
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; CHECK-NEXT: pop {r7, pc}
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