forked from OSchip/llvm-project
Revert "[LoopDeletion] Break backedge of loops when known not taken"
This reverts commit dd6bb367d1.
Multi-stage builders are showing an assertion failure w/LCSSA not being preserved on entry to IndVars. Reason isn't clear, reverting while investigating.
This commit is contained in:
Philip Reames
parent
dd6bb367d1
commit
7c63aac7bd
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@ -179,12 +179,6 @@ bool hoistRegion(DomTreeNode *, AAResults *, LoopInfo *, DominatorTree *,
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void deleteDeadLoop(Loop *L, DominatorTree *DT, ScalarEvolution *SE,
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LoopInfo *LI, MemorySSA *MSSA = nullptr);
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/// Remove the backedge of the specified loop. Handles loop nests and general
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/// loop structures subject to the precondition that the loop has a single
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/// latch block. Preserves all listed analyses.
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void breakLoopBackedge(Loop *L, DominatorTree &DT, ScalarEvolution &SE,
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LoopInfo &LI, MemorySSA *MSSA);
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/// Try to promote memory values to scalars by sinking stores out of
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/// the loop and moving loads to before the loop. We do this by looping over
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/// the stores in the loop, looking for stores to Must pointers which are
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@ -26,7 +26,6 @@
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/Transforms/Scalar/LoopPassManager.h"
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#include "llvm/Transforms/Utils/LoopUtils.h"
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using namespace llvm;
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#define DEBUG_TYPE "loop-delete"
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@ -39,14 +38,6 @@ enum class LoopDeletionResult {
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Deleted,
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};
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static LoopDeletionResult merge(LoopDeletionResult A, LoopDeletionResult B) {
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if (A == LoopDeletionResult::Deleted || B == LoopDeletionResult::Deleted)
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return LoopDeletionResult::Deleted;
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if (A == LoopDeletionResult::Modified || B == LoopDeletionResult::Modified)
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return LoopDeletionResult::Modified;
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return LoopDeletionResult::Unmodified;
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}
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/// Determines if a loop is dead.
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///
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/// This assumes that we've already checked for unique exit and exiting blocks,
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@ -135,26 +126,6 @@ static bool isLoopNeverExecuted(Loop *L) {
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return true;
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}
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/// If we can prove the backedge is untaken, remove it. This destroys the
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/// loop, but leaves the (now trivially loop invariant) control flow and
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/// side effects (if any) in place.
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static LoopDeletionResult
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breakBackedgeIfNotTaken(Loop *L, DominatorTree &DT, ScalarEvolution &SE,
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LoopInfo &LI, MemorySSA *MSSA,
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OptimizationRemarkEmitter &ORE) {
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assert(L->isLCSSAForm(DT) && "Expected LCSSA!");
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if (!L->getLoopLatch())
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return LoopDeletionResult::Unmodified;
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auto *BTC = SE.getBackedgeTakenCount(L);
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if (!BTC->isZero())
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return LoopDeletionResult::Unmodified;
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breakLoopBackedge(L, DT, SE, LI, MSSA);
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return LoopDeletionResult::Deleted;
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}
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/// Remove a loop if it is dead.
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///
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/// A loop is considered dead if it does not impact the observable behavior of
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@ -191,6 +162,7 @@ static LoopDeletionResult deleteLoopIfDead(Loop *L, DominatorTree &DT,
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return LoopDeletionResult::Unmodified;
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}
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BasicBlock *ExitBlock = L->getUniqueExitBlock();
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if (ExitBlock && isLoopNeverExecuted(L)) {
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@ -268,14 +240,6 @@ PreservedAnalyses LoopDeletionPass::run(Loop &L, LoopAnalysisManager &AM,
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// but ORE cannot be preserved (see comment before the pass definition).
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OptimizationRemarkEmitter ORE(L.getHeader()->getParent());
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auto Result = deleteLoopIfDead(&L, AR.DT, AR.SE, AR.LI, AR.MSSA, ORE);
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// If we can prove the backedge isn't taken, just break it and be done. This
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// leaves the loop structure in place which means it can handle dispatching
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// to the right exit based on whatever loop invariant structure remains.
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if (Result != LoopDeletionResult::Deleted)
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Result = merge(Result, breakBackedgeIfNotTaken(&L, AR.DT, AR.SE, AR.LI,
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AR.MSSA, ORE));
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if (Result == LoopDeletionResult::Unmodified)
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return PreservedAnalyses::all();
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@ -335,12 +299,6 @@ bool LoopDeletionLegacyPass::runOnLoop(Loop *L, LPPassManager &LPM) {
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LoopDeletionResult Result = deleteLoopIfDead(L, DT, SE, LI, MSSA, ORE);
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// If we can prove the backedge isn't taken, just break it and be done. This
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// leaves the loop structure in place which means it can handle dispatching
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// to the right exit based on whatever loop invariant structure remains.
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if (Result != LoopDeletionResult::Deleted)
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Result = merge(Result, breakBackedgeIfNotTaken(L, DT, SE, LI, MSSA, ORE));
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if (Result == LoopDeletionResult::Deleted)
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LPM.markLoopAsDeleted(*L);
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@ -756,37 +756,6 @@ void llvm::deleteDeadLoop(Loop *L, DominatorTree *DT, ScalarEvolution *SE,
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}
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}
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void llvm::breakLoopBackedge(Loop *L, DominatorTree &DT, ScalarEvolution &SE,
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LoopInfo &LI, MemorySSA *MSSA) {
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auto *Latch = L->getLoopLatch();
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assert(Latch);
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auto *Header = L->getHeader();
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SE.forgetLoop(L);
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// Note: By splitting the backedge, and then explicitly making it unreachable
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// we gracefully handle corner cases such as non-bottom tested loops and the
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// like. We also have the benefit of being able to reuse existing well tested
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// code. It might be worth special casing the common bottom tested case at
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// some point to avoid code churn.
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std::unique_ptr<MemorySSAUpdater> MSSAU;
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if (MSSA)
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MSSAU = std::make_unique<MemorySSAUpdater>(MSSA);
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auto *BackedgeBB = SplitEdge(Latch, Header, &DT, &LI, MSSAU.get());
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DomTreeUpdater DTU(&DT, DomTreeUpdater::UpdateStrategy::Eager);
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(void)changeToUnreachable(BackedgeBB->getTerminator(), /*UseTrap*/false,
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/*PreserveLCSSA*/true, &DTU, MSSAU.get());
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// Erase (and destroy) this loop instance. Handles relinking sub-loops
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// and blocks within the loop as needed.
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LI.erase(L);
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}
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/// Checks if \p L has single exit through latch block except possibly
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/// "deoptimizing" exits. Returns branch instruction terminating the loop
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/// latch if above check is successful, nullptr otherwise.
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@ -23,8 +23,8 @@ define dso_local i32 @main() {
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; CHECK-NEXT: [[I6:%.*]] = load i32, i32* @a, align 4
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; CHECK-NEXT: [[I24:%.*]] = load i32, i32* @b, align 4
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; CHECK-NEXT: [[D_PROMOTED9:%.*]] = load i32, i32* @d, align 4
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; CHECK-NEXT: br label [[BB13_PREHEADER:%.*]]
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; CHECK: bb13.preheader:
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; CHECK-NEXT: br label [[BB1:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: [[I8_LCSSA10:%.*]] = phi i32 [ [[D_PROMOTED9]], [[BB:%.*]] ], [ [[I8:%.*]], [[BB19_PREHEADER:%.*]] ]
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; CHECK-NEXT: [[I8]] = and i32 [[I8_LCSSA10]], [[I6]]
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; CHECK-NEXT: [[I21:%.*]] = icmp eq i32 [[I8]], 0
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@ -33,7 +33,7 @@ define dso_local i32 @main() {
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; CHECK-NEXT: [[I26:%.*]] = urem i32 [[I24]], [[I8]]
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; CHECK-NEXT: store i32 [[I26]], i32* @e, align 4
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; CHECK-NEXT: [[I30_NOT:%.*]] = icmp eq i32 [[I26]], 0
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; CHECK-NEXT: br i1 [[I30_NOT]], label [[BB32_LOOPEXIT:%.*]], label [[BB13_PREHEADER]]
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; CHECK-NEXT: br i1 [[I30_NOT]], label [[BB32_LOOPEXIT:%.*]], label [[BB1]]
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; CHECK: bb13.preheader.bb27.thread.split_crit_edge:
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; CHECK-NEXT: store i32 -1, i32* @f, align 4
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; CHECK-NEXT: store i32 0, i32* @d, align 4
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@ -89,10 +89,8 @@ define i32 @zero_backedge_count_test(i32 %unknown_init, i32* %unknown_mem) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[UNKNOWN_NEXT:%.*]] = load volatile i32, i32* [[UNKNOWN_MEM:%.*]], align 4
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; CHECK-NEXT: br i1 false, label [[LOOP_LOOP_CRIT_EDGE:%.*]], label [[LEAVE:%.*]]
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; CHECK: loop.loop_crit_edge:
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; CHECK-NEXT: unreachable
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; CHECK-NEXT: [[UNKNOWN_NEXT:%.*]] = load volatile i32, i32* [[UNKNOWN_MEM:%.*]]
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; CHECK-NEXT: br i1 false, label [[LOOP]], label [[LEAVE:%.*]]
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; CHECK: leave:
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; CHECK-NEXT: ret i32 [[UNKNOWN_INIT:%.*]]
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;
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@ -44,8 +44,7 @@ for.body6: ; preds = %for.body6, %for.bod
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%conv10 = zext i1 %cmp9 to i32
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%and = and i32 %conv10, %g.138
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%inc = add i32 %h.039, 1
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%exit = icmp eq i32 %inc, 20000
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br i1 %exit, label %for.inc11, label %for.body6
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br i1 undef, label %for.inc11, label %for.body6
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for.inc11: ; preds = %for.body6
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%and.lcssa = phi i32 [ %and, %for.body6 ]
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@ -1,335 +0,0 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -loop-deletion -S | FileCheck %s
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@G = external global i32
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define void @test_trivial() {
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; CHECK-LABEL: @test_trivial(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: store i32 0, i32* @G, align 4
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; CHECK-NEXT: br i1 false, label [[LOOP_LOOP_CRIT_EDGE:%.*]], label [[EXIT:%.*]]
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; CHECK: loop.loop_crit_edge:
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; CHECK-NEXT: unreachable
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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store i32 0, i32* @G
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br i1 false, label %loop, label %exit
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exit:
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ret void
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}
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define void @test_bottom_tested() {
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; CHECK-LABEL: @test_bottom_tested(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: store i32 0, i32* @G, align 4
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; CHECK-NEXT: [[IV_INC:%.*]] = add i32 [[IV]], 1
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; CHECK-NEXT: [[BE_TAKEN:%.*]] = icmp ne i32 [[IV_INC]], 1
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; CHECK-NEXT: br i1 [[BE_TAKEN]], label [[LOOP_LOOP_CRIT_EDGE:%.*]], label [[EXIT:%.*]]
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; CHECK: loop.loop_crit_edge:
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; CHECK-NEXT: unreachable
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry], [ %iv.inc, %loop ]
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store i32 0, i32* @G
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%iv.inc = add i32 %iv, 1
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%be_taken = icmp ne i32 %iv.inc, 1
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br i1 %be_taken, label %loop, label %exit
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exit:
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ret void
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}
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define void @test_early_exit() {
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; CHECK-LABEL: @test_early_exit(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: store i32 0, i32* @G, align 4
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; CHECK-NEXT: [[IV_INC:%.*]] = add i32 [[IV]], 1
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; CHECK-NEXT: [[BE_TAKEN:%.*]] = icmp ne i32 [[IV_INC]], 1
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; CHECK-NEXT: br i1 [[BE_TAKEN]], label [[LATCH:%.*]], label [[EXIT:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: br label [[LATCH_SPLIT:%.*]]
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; CHECK: latch.split:
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; CHECK-NEXT: unreachable
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry], [ %iv.inc, %latch ]
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store i32 0, i32* @G
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%iv.inc = add i32 %iv, 1
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%be_taken = icmp ne i32 %iv.inc, 1
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br i1 %be_taken, label %latch, label %exit
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latch:
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br label %loop
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exit:
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ret void
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}
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define void @test_multi_exit1() {
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; CHECK-LABEL: @test_multi_exit1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: store i32 0, i32* @G, align 4
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; CHECK-NEXT: [[IV_INC:%.*]] = add i32 [[IV]], 1
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; CHECK-NEXT: [[BE_TAKEN:%.*]] = icmp ne i32 [[IV_INC]], 1
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; CHECK-NEXT: br i1 [[BE_TAKEN]], label [[LATCH:%.*]], label [[EXIT:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: store i32 1, i32* @G, align 4
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; CHECK-NEXT: [[COND2:%.*]] = icmp ult i32 [[IV_INC]], 30
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; CHECK-NEXT: br i1 [[COND2]], label [[LATCH_LOOP_CRIT_EDGE:%.*]], label [[EXIT]]
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; CHECK: latch.loop_crit_edge:
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; CHECK-NEXT: unreachable
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry], [ %iv.inc, %latch ]
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store i32 0, i32* @G
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%iv.inc = add i32 %iv, 1
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%be_taken = icmp ne i32 %iv.inc, 1
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br i1 %be_taken, label %latch, label %exit
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latch:
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store i32 1, i32* @G
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%cond2 = icmp ult i32 %iv.inc, 30
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br i1 %cond2, label %loop, label %exit
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exit:
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ret void
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}
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define void @test_multi_exit2() {
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; CHECK-LABEL: @test_multi_exit2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: store i32 0, i32* @G, align 4
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; CHECK-NEXT: br i1 true, label [[LATCH:%.*]], label [[EXIT:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: store i32 1, i32* @G, align 4
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; CHECK-NEXT: br i1 false, label [[LATCH_LOOP_CRIT_EDGE:%.*]], label [[EXIT]]
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; CHECK: latch.loop_crit_edge:
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; CHECK-NEXT: unreachable
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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store i32 0, i32* @G
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br i1 true, label %latch, label %exit
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latch:
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store i32 1, i32* @G
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br i1 false, label %loop, label %exit
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exit:
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ret void
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}
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; TODO: SCEV seems not to recognize this as a zero btc loop
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define void @test_multi_exit3(i1 %cond1) {
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; CHECK-LABEL: @test_multi_exit3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_INC:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: store i32 0, i32* @G, align 4
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; CHECK-NEXT: br i1 [[COND1:%.*]], label [[LATCH]], label [[EXIT:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: store i32 1, i32* @G, align 4
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; CHECK-NEXT: [[IV_INC]] = add i32 [[IV]], 1
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; CHECK-NEXT: [[BE_TAKEN:%.*]] = icmp ne i32 [[IV_INC]], 1
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; CHECK-NEXT: br i1 [[BE_TAKEN]], label [[LOOP]], label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry], [ %iv.inc, %latch ]
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store i32 0, i32* @G
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br i1 %cond1, label %latch, label %exit
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latch:
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store i32 1, i32* @G
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%iv.inc = add i32 %iv, 1
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%be_taken = icmp ne i32 %iv.inc, 1
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br i1 %be_taken, label %loop, label %exit
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exit:
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ret void
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}
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; Subtle - This is either zero btc, or infinite, thus, can't break
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; backedge
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define void @test_multi_exit4(i1 %cond1, i1 %cond2) {
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; CHECK-LABEL: @test_multi_exit4(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: store i32 0, i32* @G, align 4
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; CHECK-NEXT: br i1 [[COND1:%.*]], label [[LATCH:%.*]], label [[EXIT:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: store i32 1, i32* @G, align 4
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; CHECK-NEXT: br i1 [[COND2:%.*]], label [[LOOP]], label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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store i32 0, i32* @G
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br i1 %cond1, label %latch, label %exit
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latch:
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store i32 1, i32* @G
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br i1 %cond2, label %loop, label %exit
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exit:
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ret void
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}
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; A simple case with multiple exit blocks
|
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define void @test_multi_exit5() {
|
||||
; CHECK-LABEL: @test_multi_exit5(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: br label [[LOOP:%.*]]
|
||||
; CHECK: loop:
|
||||
; CHECK-NEXT: store i32 0, i32* @G, align 4
|
||||
; CHECK-NEXT: br i1 true, label [[LATCH:%.*]], label [[EXIT1:%.*]]
|
||||
; CHECK: latch:
|
||||
; CHECK-NEXT: store i32 1, i32* @G, align 4
|
||||
; CHECK-NEXT: br i1 false, label [[LATCH_LOOP_CRIT_EDGE:%.*]], label [[EXIT2:%.*]]
|
||||
; CHECK: latch.loop_crit_edge:
|
||||
; CHECK-NEXT: unreachable
|
||||
; CHECK: exit1:
|
||||
; CHECK-NEXT: ret void
|
||||
; CHECK: exit2:
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
br label %loop
|
||||
|
||||
loop:
|
||||
store i32 0, i32* @G
|
||||
br i1 true, label %latch, label %exit1
|
||||
latch:
|
||||
store i32 1, i32* @G
|
||||
br i1 false, label %loop, label %exit2
|
||||
|
||||
exit1:
|
||||
ret void
|
||||
exit2:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_live_inner() {
|
||||
; CHECK-LABEL: @test_live_inner(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: br label [[LOOP:%.*]]
|
||||
; CHECK: loop:
|
||||
; CHECK-NEXT: store i32 0, i32* @G, align 4
|
||||
; CHECK-NEXT: br label [[INNER:%.*]]
|
||||
; CHECK: inner:
|
||||
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[IV_INC:%.*]], [[INNER]] ]
|
||||
; CHECK-NEXT: store i32 [[IV]], i32* @G, align 4
|
||||
; CHECK-NEXT: [[IV_INC]] = add i32 [[IV]], 1
|
||||
; CHECK-NEXT: [[CND:%.*]] = icmp ult i32 [[IV_INC]], 200
|
||||
; CHECK-NEXT: br i1 [[CND]], label [[INNER]], label [[LATCH:%.*]]
|
||||
; CHECK: latch:
|
||||
; CHECK-NEXT: br i1 false, label [[LATCH_LOOP_CRIT_EDGE:%.*]], label [[EXIT:%.*]]
|
||||
; CHECK: latch.loop_crit_edge:
|
||||
; CHECK-NEXT: unreachable
|
||||
; CHECK: exit:
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
br label %loop
|
||||
|
||||
loop:
|
||||
store i32 0, i32* @G
|
||||
br label %inner
|
||||
|
||||
inner:
|
||||
%iv = phi i32 [0, %loop], [%iv.inc, %inner]
|
||||
store i32 %iv, i32* @G
|
||||
%iv.inc = add i32 %iv, 1
|
||||
%cnd = icmp ult i32 %iv.inc, 200
|
||||
br i1 %cnd, label %inner, label %latch
|
||||
|
||||
latch:
|
||||
br i1 false, label %loop, label %exit
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_live_outer() {
|
||||
; CHECK-LABEL: @test_live_outer(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: br label [[LOOP:%.*]]
|
||||
; CHECK: loop:
|
||||
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_INC:%.*]], [[LATCH:%.*]] ]
|
||||
; CHECK-NEXT: br label [[INNER:%.*]]
|
||||
; CHECK: inner:
|
||||
; CHECK-NEXT: store i32 0, i32* @G, align 4
|
||||
; CHECK-NEXT: br i1 false, label [[INNER_INNER_CRIT_EDGE:%.*]], label [[LATCH]]
|
||||
; CHECK: inner.inner_crit_edge:
|
||||
; CHECK-NEXT: unreachable
|
||||
; CHECK: latch:
|
||||
; CHECK-NEXT: store i32 [[IV]], i32* @G, align 4
|
||||
; CHECK-NEXT: [[IV_INC]] = add i32 [[IV]], 1
|
||||
; CHECK-NEXT: [[CND:%.*]] = icmp ult i32 [[IV_INC]], 200
|
||||
; CHECK-NEXT: br i1 [[CND]], label [[LOOP]], label [[EXIT:%.*]]
|
||||
; CHECK: exit:
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
br label %loop
|
||||
|
||||
loop:
|
||||
%iv = phi i32 [0, %entry], [%iv.inc, %latch]
|
||||
br label %inner
|
||||
|
||||
inner:
|
||||
store i32 0, i32* @G
|
||||
br i1 false, label %inner, label %latch
|
||||
|
||||
latch:
|
||||
store i32 %iv, i32* @G
|
||||
%iv.inc = add i32 %iv, 1
|
||||
%cnd = icmp ult i32 %iv.inc, 200
|
||||
br i1 %cnd, label %loop, label %exit
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue