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[X86][AVX] Add support for 32/64 bits 256-bit vector horizontal op redundant shuffle removal 

llvm-svn: 337561
This commit is contained in:
Simon Pilgrim 2018-07-20 15:24:12 +00:00
parent 5a4e11ad9c
commit 7c56bce996
2 changed files with 11 additions and 11 deletions
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16
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -31144,8 +31144,8 @@ static SDValue foldShuffleOfHorizOp(SDNode *N) {
// lanes of each operand as:
// v4X32: A[0] + A[1] , A[2] + A[3] , B[0] + B[1] , B[2] + B[3]
// ...similarly for v2f64 and v8i16.
// TODO: 256-bit is not the same because...x86.
if (HOp.getOperand(0) != HOp.getOperand(1) || HOp.getValueSizeInBits() != 128)
// TODO: Handle UNDEF operands.
if (HOp.getOperand(0) != HOp.getOperand(1))
return SDValue();
// When the operands of a horizontal math op are identical, the low half of
@ -31156,9 +31156,15 @@ static SDValue foldShuffleOfHorizOp(SDNode *N) {
// TODO: Other mask possibilities like {1,1} and {1,0} could be added here,
// but this should be tied to whatever horizontal op matching and shuffle
// canonicalization are producing.
if (isTargetShuffleEquivalent(Mask, { 0, 0 }) ||
isTargetShuffleEquivalent(Mask, { 0, 1, 0, 1 }) ||
isTargetShuffleEquivalent(Mask, { 0, 1, 2, 3, 0, 1, 2, 3 }))
if (HOp.getValueSizeInBits() == 128 &&
(isTargetShuffleEquivalent(Mask, {0, 0}) ||
isTargetShuffleEquivalent(Mask, {0, 1, 0, 1}) ||
isTargetShuffleEquivalent(Mask, {0, 1, 2, 3, 0, 1, 2, 3})))
return HOp;
if (HOp.getValueSizeInBits() == 256 &&
(isTargetShuffleEquivalent(Mask, {0, 0, 2, 2}) ||
isTargetShuffleEquivalent(Mask, {0, 1, 0, 1, 4, 5, 4, 5})))
return HOp;
return SDValue();

6
llvm/test/CodeGen/X86/haddsub-shuf.ll
View File

@ -63,7 +63,6 @@ define <8 x float> @hadd_v8f32b(<8 x float> %a) {
; AVX-LABEL: hadd_v8f32b:
; AVX: # %bb.0:
; AVX-NEXT: vhaddps %ymm0, %ymm0, %ymm0
; AVX-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; AVX-NEXT: retq
%a0 = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 4, i32 6, i32 undef, i32 undef>
%a1 = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 1, i32 3, i32 undef, i32 undef, i32 5, i32 7, i32 undef, i32 undef>
@ -129,7 +128,6 @@ define <8 x float> @hsub_v8f32b(<8 x float> %a) {
; AVX-LABEL: hsub_v8f32b:
; AVX: # %bb.0:
; AVX-NEXT: vhsubps %ymm0, %ymm0, %ymm0
; AVX-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; AVX-NEXT: retq
%a0 = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 4, i32 6, i32 undef, i32 undef>
%a1 = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 1, i32 3, i32 undef, i32 undef, i32 5, i32 7, i32 undef, i32 undef>
@ -165,7 +163,6 @@ define <4 x double> @hadd_v4f64(<4 x double> %a) {
; AVX-LABEL: hadd_v4f64:
; AVX: # %bb.0:
; AVX-NEXT: vhaddpd %ymm0, %ymm0, %ymm0
; AVX-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; AVX-NEXT: retq
%a0 = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 0, i32 undef, i32 2, i32 undef>
%a1 = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 1, i32 undef, i32 3, i32 undef>
@ -201,7 +198,6 @@ define <4 x double> @hsub_v4f64(<4 x double> %a) {
; AVX-LABEL: hsub_v4f64:
; AVX: # %bb.0:
; AVX-NEXT: vhsubpd %ymm0, %ymm0, %ymm0
; AVX-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; AVX-NEXT: retq
%a0 = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 0, i32 undef, i32 2, i32 undef>
%a1 = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 1, i32 undef, i32 3, i32 undef>
@ -279,7 +275,6 @@ define <8 x i32> @hadd_v8i32b(<8 x i32> %a) {
; AVX2-LABEL: hadd_v8i32b:
; AVX2: # %bb.0:
; AVX2-NEXT: vphaddd %ymm0, %ymm0, %ymm0
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,1,0,1,4,5,4,5]
; AVX2-NEXT: retq
%a0 = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 4, i32 6, i32 undef, i32 undef>
%a1 = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> <i32 1, i32 3, i32 undef, i32 undef, i32 5, i32 7, i32 undef, i32 undef>
@ -357,7 +352,6 @@ define <8 x i32> @hsub_v8i32b(<8 x i32> %a) {
; AVX2-LABEL: hsub_v8i32b:
; AVX2: # %bb.0:
; AVX2-NEXT: vphsubd %ymm0, %ymm0, %ymm0
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,1,0,1,4,5,4,5]
; AVX2-NEXT: retq
%a0 = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 4, i32 6, i32 undef, i32 undef>
%a1 = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> <i32 1, i32 3, i32 undef, i32 undef, i32 5, i32 7, i32 undef, i32 undef>