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[X86] Use splitVector helper in truncateVectorWithPACK/splitVectorStore/combineHorizontalMinMaxResult/combineReductionToHorizontal. NFC. 

All these locations were performing the same type splitting/extractSubVector calls as the spltVector helper.
This commit is contained in:
Simon Pilgrim 2020-05-03 13:23:46 +01:00
parent f914b500df
commit 7c203163c7
1 changed files with 14 additions and 24 deletions
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38
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -20267,10 +20267,9 @@ static SDValue truncateVectorWithPACK(unsigned Opcode, EVT DstVT, SDValue In,
return DAG.getBitcast(DstVT, Res); return DAG.getBitcast(DstVT, Res);
} }
// Extract lower/upper subvectors. // Split lower/upper subvectors.
unsigned NumSubElts = NumElems / 2; SDValue Lo, Hi;
SDValue Lo = extractSubVector(In, 0 * NumSubElts, DAG, DL, SrcSizeInBits / 2); std::tie(Lo, Hi) = splitVector(In, DAG, DL);
SDValue Hi = extractSubVector(In, 1 * NumSubElts, DAG, DL, SrcSizeInBits / 2);
unsigned SubSizeInBits = SrcSizeInBits / 2; unsigned SubSizeInBits = SrcSizeInBits / 2;
InVT = EVT::getVectorVT(Ctx, InVT, SubSizeInBits / InVT.getSizeInBits()); InVT = EVT::getVectorVT(Ctx, InVT, SubSizeInBits / InVT.getSizeInBits());
@ -20310,7 +20309,7 @@ static SDValue truncateVectorWithPACK(unsigned Opcode, EVT DstVT, SDValue In,
// Recursively pack lower/upper subvectors, concat result and pack again. // Recursively pack lower/upper subvectors, concat result and pack again.
assert(SrcSizeInBits >= 256 && "Expected 256-bit vector or greater"); assert(SrcSizeInBits >= 256 && "Expected 256-bit vector or greater");
EVT PackedVT = EVT::getVectorVT(Ctx, PackedSVT, NumSubElts); EVT PackedVT = EVT::getVectorVT(Ctx, PackedSVT, NumElems / 2);
Lo = truncateVectorWithPACK(Opcode, PackedVT, Lo, DL, DAG, Subtarget); Lo = truncateVectorWithPACK(Opcode, PackedVT, Lo, DL, DAG, Subtarget);
Hi = truncateVectorWithPACK(Opcode, PackedVT, Hi, DL, DAG, Subtarget); Hi = truncateVectorWithPACK(Opcode, PackedVT, Hi, DL, DAG, Subtarget);
@ -23225,14 +23224,10 @@ static SDValue splitVectorStore(StoreSDNode *Store, SelectionDAG &DAG) {
if (!Store->isSimple()) if (!Store->isSimple())
return SDValue(); return SDValue();
EVT StoreVT = StoredVal.getValueType();
unsigned NumElems = StoreVT.getVectorNumElements();
unsigned HalfSize = StoredVal.getValueSizeInBits() / 2;
unsigned HalfAlign = (128 == HalfSize ? 16 : 32);
SDLoc DL(Store); SDLoc DL(Store);
SDValue Value0 = extractSubVector(StoredVal, 0, DAG, DL, HalfSize); SDValue Value0, Value1;
SDValue Value1 = extractSubVector(StoredVal, NumElems / 2, DAG, DL, HalfSize); std::tie(Value0, Value1) = splitVector(StoredVal, DAG, DL);
unsigned HalfAlign = (StoredVal.getValueType().is256BitVector() ? 16 : 32);
SDValue Ptr0 = Store->getBasePtr(); SDValue Ptr0 = Store->getBasePtr();
SDValue Ptr1 = DAG.getMemBasePlusOffset(Ptr0, HalfAlign, DL); SDValue Ptr1 = DAG.getMemBasePlusOffset(Ptr0, HalfAlign, DL);
unsigned Alignment = Store->getAlignment(); unsigned Alignment = Store->getAlignment();
@ -37997,12 +37992,9 @@ static SDValue combineHorizontalMinMaxResult(SDNode *Extract, SelectionDAG &DAG,
// First, reduce the source down to 128-bit, applying BinOp to lo/hi. // First, reduce the source down to 128-bit, applying BinOp to lo/hi.
while (SrcVT.getSizeInBits() > 128) { while (SrcVT.getSizeInBits() > 128) {
unsigned NumElts = SrcVT.getVectorNumElements(); SDValue Lo, Hi;
unsigned NumSubElts = NumElts / 2; std::tie(Lo, Hi) = splitVector(MinPos, DAG, DL);
SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcSVT, NumSubElts); SrcVT = Lo.getValueType();
unsigned SubSizeInBits = SrcVT.getSizeInBits();
SDValue Lo = extractSubVector(MinPos, 0, DAG, DL, SubSizeInBits);
SDValue Hi = extractSubVector(MinPos, NumSubElts, DAG, DL, SubSizeInBits);
MinPos = DAG.getNode(BinOp, DL, SrcVT, Lo, Hi); MinPos = DAG.getNode(BinOp, DL, SrcVT, Lo, Hi);
} }
assert(((SrcVT == MVT::v8i16 && ExtractVT == MVT::i16) || assert(((SrcVT == MVT::v8i16 && ExtractVT == MVT::i16) ||
@ -38583,12 +38575,10 @@ static SDValue combineReductionToHorizontal(SDNode *ExtElt, SelectionDAG &DAG,
// vXi8 reduction - sum lo/hi halves then use PSADBW. // vXi8 reduction - sum lo/hi halves then use PSADBW.
if (VT == MVT::i8) { if (VT == MVT::i8) {
while (Rdx.getValueSizeInBits() > 128) { while (Rdx.getValueSizeInBits() > 128) {
unsigned HalfSize = VecVT.getSizeInBits() / 2; SDValue Lo, Hi;
unsigned HalfElts = VecVT.getVectorNumElements() / 2; std::tie(Lo, Hi) = splitVector(Rdx, DAG, DL);
SDValue Lo = extractSubVector(Rdx, 0, DAG, DL, HalfSize); VecVT = Lo.getValueType();
SDValue Hi = extractSubVector(Rdx, HalfElts, DAG, DL, HalfSize); Rdx = DAG.getNode(ISD::ADD, DL, VecVT, Lo, Hi);
Rdx = DAG.getNode(ISD::ADD, DL, Lo.getValueType(), Lo, Hi);
VecVT = Rdx.getValueType();
} }
assert(VecVT == MVT::v16i8 && "v16i8 reduction expected"); assert(VecVT == MVT::v16i8 && "v16i8 reduction expected");