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[mips][microMIPS] Implement CACHEE and PREFE instructions for microMIPS32r6 

Differential Revision: http://reviews.llvm.org/D11632

llvm-svn: 247670
This commit is contained in:
Zoran Jovanovic 2015-09-15 10:05:10 +00:00
parent e4e83a7bc1
commit 7beb737b46
5 changed files with 37 additions and 1 deletions
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2
llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
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@ -777,7 +777,7 @@ getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
assert(MI.getOperand(OpNo).isReg());
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
STI) << 16;
unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI);
return (OffBits & 0x1FF) | RegBits;
}

16
llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td
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@ -97,6 +97,22 @@ class ADDI_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
let Inst{15-0} = imm16;
}
class POOL32C_ST_EVA_FM_MMR6<bits<6> op, bits<3> funct> : MipsR6Inst {
bits<21> addr;
bits<5> hint;
bits<5> base = addr{20-16};
bits<9> offset = addr{8-0};
bits<32> Inst;
let Inst{31-26} = op;
let Inst{25-21} = hint;
let Inst{20-16} = base;
let Inst{15-12} = 0b1010;
let Inst{11-9} = funct;
let Inst{8-0} = offset;
}
class SIGN_EXTEND_FM_MMR6<string instr_asm, bits<10> funct>
: MMR6Arch<instr_asm> {
bits<5> rd;

14
llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
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@ -71,6 +71,8 @@ class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
class PREFE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b010>;
class CACHEE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b011>;
class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
@ -262,6 +264,16 @@ class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
class PREFE_CACHEE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
RegisterOperand GPROpnd> :
CACHE_HINT_MMR6_DESC<instr_asm, MemOpnd,
GPROpnd> {
string DecoderMethod = "DecodePrefeOpMM";
}
class PREFE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"prefe", mem_mm_9, GPR32Opnd>;
class CACHEE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"cachee", mem_mm_9, GPR32Opnd>;
class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
: MMR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rt);
@ -741,6 +753,8 @@ def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
def PREFE_MMR6 : R6MMR6Rel, PREFE_MMR6_ENC, PREFE_MMR6_DESC, ISA_MICROMIPS32R6;
def CACHEE_MMR6 : R6MMR6Rel, CACHEE_MMR6_ENC, CACHEE_MMR6_DESC, ISA_MICROMIPS32R6;
def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
let DecoderMethod = "DecodeMemMMImm16" in {

4
llvm/test/MC/Disassembler/Mips/micromips32r6.txt
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@ -351,3 +351,7 @@
0x25 0xe0 # CHECK: sll16 $3, $6, 8
0x25 0xe1 # CHECK: srl16 $3, $6, 8
0x60 0x25 0xa6 0x08 # CHECK: cachee 1, 8($5)
0x60 0x25 0xa4 0x08 # CHECK: prefe 1, 8($5)

2
llvm/test/MC/Mips/micromips32r6/valid.s
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@ -179,4 +179,6 @@
or16 $3, $7 # CHECK: or16 $3, $7 # encoding: [0x45,0xf9]
sll16 $3, $6, 8 # CHECK: sll16 $3, $6, 8 # encoding: [0x25,0xe0]
srl16 $3, $6, 8 # CHECK: srl16 $3, $6, 8 # encoding: [0x25,0xe1]
prefe 1, 8($5) # CHECK: prefe 1, 8($5) # encoding: [0x60,0x25,0xa4,0x08]
cachee 1, 8($5) # CHECK: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08]