diff --git a/llvm/test/CodeGen/AArch64/const-shift-of-constmasked.ll b/llvm/test/CodeGen/AArch64/const-shift-of-constmasked.ll
new file mode 100644
index 000000000000..66a6745cda8f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/const-shift-of-constmasked.ll
@@ -0,0 +1,1104 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
+
+; The mask is all-ones, potentially shifted.
+
+;------------------------------------------------------------------------------;
+; 8-bit
+;------------------------------------------------------------------------------;
+
+; lshr
+
+define i8 @test_i8_7_mask_lshr_1(i8 %a0) {
+; CHECK-LABEL: test_i8_7_mask_lshr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #1, #2
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 7
+  %t1 = lshr i8 %t0, 1
+  ret i8 %t1
+}
+
+define i8 @test_i8_28_mask_lshr_1(i8 %a0) {
+; CHECK-LABEL: test_i8_28_mask_lshr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x1c
+; CHECK-NEXT:    lsr w0, w8, #1
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 28
+  %t1 = lshr i8 %t0, 1
+  ret i8 %t1
+}
+define i8 @test_i8_28_mask_lshr_2(i8 %a0) {
+; CHECK-LABEL: test_i8_28_mask_lshr_2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #2, #3
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 28
+  %t1 = lshr i8 %t0, 2
+  ret i8 %t1
+}
+define i8 @test_i8_28_mask_lshr_3(i8 %a0) {
+; CHECK-LABEL: test_i8_28_mask_lshr_3:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #3, #2
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 28
+  %t1 = lshr i8 %t0, 3
+  ret i8 %t1
+}
+define i8 @test_i8_28_mask_lshr_4(i8 %a0) {
+; CHECK-LABEL: test_i8_28_mask_lshr_4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #4, #1
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 28
+  %t1 = lshr i8 %t0, 4
+  ret i8 %t1
+}
+
+define i8 @test_i8_224_mask_lshr_1(i8 %a0) {
+; CHECK-LABEL: test_i8_224_mask_lshr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0xe0
+; CHECK-NEXT:    lsr w0, w8, #1
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 224
+  %t1 = lshr i8 %t0, 1
+  ret i8 %t1
+}
+define i8 @test_i8_224_mask_lshr_4(i8 %a0) {
+; CHECK-LABEL: test_i8_224_mask_lshr_4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0xe0
+; CHECK-NEXT:    lsr w0, w8, #4
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 224
+  %t1 = lshr i8 %t0, 4
+  ret i8 %t1
+}
+define i8 @test_i8_224_mask_lshr_5(i8 %a0) {
+; CHECK-LABEL: test_i8_224_mask_lshr_5:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #5, #3
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 224
+  %t1 = lshr i8 %t0, 5
+  ret i8 %t1
+}
+define i8 @test_i8_224_mask_lshr_6(i8 %a0) {
+; CHECK-LABEL: test_i8_224_mask_lshr_6:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #6, #2
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 224
+  %t1 = lshr i8 %t0, 6
+  ret i8 %t1
+}
+
+; ashr
+
+define i8 @test_i8_7_mask_ashr_1(i8 %a0) {
+; CHECK-LABEL: test_i8_7_mask_ashr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #1, #2
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 7
+  %t1 = ashr i8 %t0, 1
+  ret i8 %t1
+}
+
+define i8 @test_i8_28_mask_ashr_1(i8 %a0) {
+; CHECK-LABEL: test_i8_28_mask_ashr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x1c
+; CHECK-NEXT:    lsr w0, w8, #1
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 28
+  %t1 = ashr i8 %t0, 1
+  ret i8 %t1
+}
+define i8 @test_i8_28_mask_ashr_2(i8 %a0) {
+; CHECK-LABEL: test_i8_28_mask_ashr_2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #2, #3
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 28
+  %t1 = ashr i8 %t0, 2
+  ret i8 %t1
+}
+define i8 @test_i8_28_mask_ashr_3(i8 %a0) {
+; CHECK-LABEL: test_i8_28_mask_ashr_3:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #3, #2
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 28
+  %t1 = ashr i8 %t0, 3
+  ret i8 %t1
+}
+define i8 @test_i8_28_mask_ashr_4(i8 %a0) {
+; CHECK-LABEL: test_i8_28_mask_ashr_4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #4, #1
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 28
+  %t1 = ashr i8 %t0, 4
+  ret i8 %t1
+}
+
+define i8 @test_i8_224_mask_ashr_1(i8 %a0) {
+; CHECK-LABEL: test_i8_224_mask_ashr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0xe0
+; CHECK-NEXT:    sbfx w0, w8, #1, #7
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 224
+  %t1 = ashr i8 %t0, 1
+  ret i8 %t1
+}
+define i8 @test_i8_224_mask_ashr_4(i8 %a0) {
+; CHECK-LABEL: test_i8_224_mask_ashr_4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0xe0
+; CHECK-NEXT:    sbfx w0, w8, #4, #4
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 224
+  %t1 = ashr i8 %t0, 4
+  ret i8 %t1
+}
+define i8 @test_i8_224_mask_ashr_5(i8 %a0) {
+; CHECK-LABEL: test_i8_224_mask_ashr_5:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sbfx w0, w0, #5, #3
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 224
+  %t1 = ashr i8 %t0, 5
+  ret i8 %t1
+}
+define i8 @test_i8_224_mask_ashr_6(i8 %a0) {
+; CHECK-LABEL: test_i8_224_mask_ashr_6:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sbfx w0, w0, #6, #2
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 224
+  %t1 = ashr i8 %t0, 6
+  ret i8 %t1
+}
+
+; shl
+
+define i8 @test_i8_7_mask_shl_1(i8 %a0) {
+; CHECK-LABEL: test_i8_7_mask_shl_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x7
+; CHECK-NEXT:    lsl w0, w8, #1
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 7
+  %t1 = shl i8 %t0, 1
+  ret i8 %t1
+}
+define i8 @test_i8_7_mask_shl_4(i8 %a0) {
+; CHECK-LABEL: test_i8_7_mask_shl_4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x7
+; CHECK-NEXT:    lsl w0, w8, #4
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 7
+  %t1 = shl i8 %t0, 4
+  ret i8 %t1
+}
+define i8 @test_i8_7_mask_shl_5(i8 %a0) {
+; CHECK-LABEL: test_i8_7_mask_shl_5:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl w0, w0, #5
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 7
+  %t1 = shl i8 %t0, 5
+  ret i8 %t1
+}
+define i8 @test_i8_7_mask_shl_6(i8 %a0) {
+; CHECK-LABEL: test_i8_7_mask_shl_6:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl w0, w0, #6
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 7
+  %t1 = shl i8 %t0, 6
+  ret i8 %t1
+}
+
+define i8 @test_i8_28_mask_shl_1(i8 %a0) {
+; CHECK-LABEL: test_i8_28_mask_shl_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x1c
+; CHECK-NEXT:    lsl w0, w8, #1
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 28
+  %t1 = shl i8 %t0, 1
+  ret i8 %t1
+}
+define i8 @test_i8_28_mask_shl_2(i8 %a0) {
+; CHECK-LABEL: test_i8_28_mask_shl_2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x1c
+; CHECK-NEXT:    lsl w0, w8, #2
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 28
+  %t1 = shl i8 %t0, 2
+  ret i8 %t1
+}
+define i8 @test_i8_28_mask_shl_3(i8 %a0) {
+; CHECK-LABEL: test_i8_28_mask_shl_3:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x1c
+; CHECK-NEXT:    lsl w0, w8, #3
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 28
+  %t1 = shl i8 %t0, 3
+  ret i8 %t1
+}
+define i8 @test_i8_28_mask_shl_4(i8 %a0) {
+; CHECK-LABEL: test_i8_28_mask_shl_4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0xc
+; CHECK-NEXT:    lsl w0, w8, #4
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 28
+  %t1 = shl i8 %t0, 4
+  ret i8 %t1
+}
+
+define i8 @test_i8_224_mask_shl_1(i8 %a0) {
+; CHECK-LABEL: test_i8_224_mask_shl_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x60
+; CHECK-NEXT:    lsl w0, w8, #1
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, 224
+  %t1 = shl i8 %t0, 1
+  ret i8 %t1
+}
+
+;------------------------------------------------------------------------------;
+; 16-bit
+;------------------------------------------------------------------------------;
+
+; lshr
+
+define i16 @test_i16_127_mask_lshr_1(i16 %a0) {
+; CHECK-LABEL: test_i16_127_mask_lshr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #1, #6
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 127
+  %t1 = lshr i16 %t0, 1
+  ret i16 %t1
+}
+
+define i16 @test_i16_2032_mask_lshr_3(i16 %a0) {
+; CHECK-LABEL: test_i16_2032_mask_lshr_3:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x7f0
+; CHECK-NEXT:    lsr w0, w8, #3
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 2032
+  %t1 = lshr i16 %t0, 3
+  ret i16 %t1
+}
+define i16 @test_i16_2032_mask_lshr_4(i16 %a0) {
+; CHECK-LABEL: test_i16_2032_mask_lshr_4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #4, #7
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 2032
+  %t1 = lshr i16 %t0, 4
+  ret i16 %t1
+}
+define i16 @test_i16_2032_mask_lshr_5(i16 %a0) {
+; CHECK-LABEL: test_i16_2032_mask_lshr_5:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #5, #6
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 2032
+  %t1 = lshr i16 %t0, 5
+  ret i16 %t1
+}
+define i16 @test_i16_2032_mask_lshr_6(i16 %a0) {
+; CHECK-LABEL: test_i16_2032_mask_lshr_6:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #6, #5
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 2032
+  %t1 = lshr i16 %t0, 6
+  ret i16 %t1
+}
+
+define i16 @test_i16_65024_mask_lshr_1(i16 %a0) {
+; CHECK-LABEL: test_i16_65024_mask_lshr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0xfe00
+; CHECK-NEXT:    lsr w0, w8, #1
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 65024
+  %t1 = lshr i16 %t0, 1
+  ret i16 %t1
+}
+define i16 @test_i16_65024_mask_lshr_8(i16 %a0) {
+; CHECK-LABEL: test_i16_65024_mask_lshr_8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0xfe00
+; CHECK-NEXT:    lsr w0, w8, #8
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 65024
+  %t1 = lshr i16 %t0, 8
+  ret i16 %t1
+}
+define i16 @test_i16_65024_mask_lshr_9(i16 %a0) {
+; CHECK-LABEL: test_i16_65024_mask_lshr_9:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #9, #7
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 65024
+  %t1 = lshr i16 %t0, 9
+  ret i16 %t1
+}
+define i16 @test_i16_65024_mask_lshr_10(i16 %a0) {
+; CHECK-LABEL: test_i16_65024_mask_lshr_10:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #10, #6
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 65024
+  %t1 = lshr i16 %t0, 10
+  ret i16 %t1
+}
+
+; ashr
+
+define i16 @test_i16_127_mask_ashr_1(i16 %a0) {
+; CHECK-LABEL: test_i16_127_mask_ashr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #1, #6
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 127
+  %t1 = ashr i16 %t0, 1
+  ret i16 %t1
+}
+
+define i16 @test_i16_2032_mask_ashr_3(i16 %a0) {
+; CHECK-LABEL: test_i16_2032_mask_ashr_3:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x7f0
+; CHECK-NEXT:    lsr w0, w8, #3
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 2032
+  %t1 = ashr i16 %t0, 3
+  ret i16 %t1
+}
+define i16 @test_i16_2032_mask_ashr_4(i16 %a0) {
+; CHECK-LABEL: test_i16_2032_mask_ashr_4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #4, #7
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 2032
+  %t1 = ashr i16 %t0, 4
+  ret i16 %t1
+}
+define i16 @test_i16_2032_mask_ashr_5(i16 %a0) {
+; CHECK-LABEL: test_i16_2032_mask_ashr_5:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #5, #6
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 2032
+  %t1 = ashr i16 %t0, 5
+  ret i16 %t1
+}
+define i16 @test_i16_2032_mask_ashr_6(i16 %a0) {
+; CHECK-LABEL: test_i16_2032_mask_ashr_6:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #6, #5
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 2032
+  %t1 = ashr i16 %t0, 6
+  ret i16 %t1
+}
+
+define i16 @test_i16_65024_mask_ashr_1(i16 %a0) {
+; CHECK-LABEL: test_i16_65024_mask_ashr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0xfe00
+; CHECK-NEXT:    sbfx w0, w8, #1, #15
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 65024
+  %t1 = ashr i16 %t0, 1
+  ret i16 %t1
+}
+define i16 @test_i16_65024_mask_ashr_8(i16 %a0) {
+; CHECK-LABEL: test_i16_65024_mask_ashr_8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0xfe00
+; CHECK-NEXT:    sbfx w0, w8, #8, #8
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 65024
+  %t1 = ashr i16 %t0, 8
+  ret i16 %t1
+}
+define i16 @test_i16_65024_mask_ashr_9(i16 %a0) {
+; CHECK-LABEL: test_i16_65024_mask_ashr_9:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sbfx w0, w0, #9, #7
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 65024
+  %t1 = ashr i16 %t0, 9
+  ret i16 %t1
+}
+define i16 @test_i16_65024_mask_ashr_10(i16 %a0) {
+; CHECK-LABEL: test_i16_65024_mask_ashr_10:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sbfx w0, w0, #10, #6
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 65024
+  %t1 = ashr i16 %t0, 10
+  ret i16 %t1
+}
+
+; shl
+
+define i16 @test_i16_127_mask_shl_1(i16 %a0) {
+; CHECK-LABEL: test_i16_127_mask_shl_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x7f
+; CHECK-NEXT:    lsl w0, w8, #1
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 127
+  %t1 = shl i16 %t0, 1
+  ret i16 %t1
+}
+define i16 @test_i16_127_mask_shl_8(i16 %a0) {
+; CHECK-LABEL: test_i16_127_mask_shl_8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x7f
+; CHECK-NEXT:    lsl w0, w8, #8
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 127
+  %t1 = shl i16 %t0, 8
+  ret i16 %t1
+}
+define i16 @test_i16_127_mask_shl_9(i16 %a0) {
+; CHECK-LABEL: test_i16_127_mask_shl_9:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl w0, w0, #9
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 127
+  %t1 = shl i16 %t0, 9
+  ret i16 %t1
+}
+define i16 @test_i16_127_mask_shl_10(i16 %a0) {
+; CHECK-LABEL: test_i16_127_mask_shl_10:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl w0, w0, #10
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 127
+  %t1 = shl i16 %t0, 10
+  ret i16 %t1
+}
+
+define i16 @test_i16_2032_mask_shl_3(i16 %a0) {
+; CHECK-LABEL: test_i16_2032_mask_shl_3:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x7f0
+; CHECK-NEXT:    lsl w0, w8, #3
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 2032
+  %t1 = shl i16 %t0, 3
+  ret i16 %t1
+}
+define i16 @test_i16_2032_mask_shl_4(i16 %a0) {
+; CHECK-LABEL: test_i16_2032_mask_shl_4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x7f0
+; CHECK-NEXT:    lsl w0, w8, #4
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 2032
+  %t1 = shl i16 %t0, 4
+  ret i16 %t1
+}
+define i16 @test_i16_2032_mask_shl_5(i16 %a0) {
+; CHECK-LABEL: test_i16_2032_mask_shl_5:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x7f0
+; CHECK-NEXT:    lsl w0, w8, #5
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 2032
+  %t1 = shl i16 %t0, 5
+  ret i16 %t1
+}
+define i16 @test_i16_2032_mask_shl_6(i16 %a0) {
+; CHECK-LABEL: test_i16_2032_mask_shl_6:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x3f0
+; CHECK-NEXT:    lsl w0, w8, #6
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 2032
+  %t1 = shl i16 %t0, 6
+  ret i16 %t1
+}
+
+define i16 @test_i16_65024_mask_shl_1(i16 %a0) {
+; CHECK-LABEL: test_i16_65024_mask_shl_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x7e00
+; CHECK-NEXT:    lsl w0, w8, #1
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, 65024
+  %t1 = shl i16 %t0, 1
+  ret i16 %t1
+}
+
+;------------------------------------------------------------------------------;
+; 32-bit
+;------------------------------------------------------------------------------;
+
+; lshr
+
+define i32 @test_i32_32767_mask_lshr_1(i32 %a0) {
+; CHECK-LABEL: test_i32_32767_mask_lshr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #1, #14
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 32767
+  %t1 = lshr i32 %t0, 1
+  ret i32 %t1
+}
+
+define i32 @test_i32_8388352_mask_lshr_7(i32 %a0) {
+; CHECK-LABEL: test_i32_8388352_mask_lshr_7:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x7fff00
+; CHECK-NEXT:    lsr w0, w8, #7
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 8388352
+  %t1 = lshr i32 %t0, 7
+  ret i32 %t1
+}
+define i32 @test_i32_8388352_mask_lshr_8(i32 %a0) {
+; CHECK-LABEL: test_i32_8388352_mask_lshr_8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #8, #15
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 8388352
+  %t1 = lshr i32 %t0, 8
+  ret i32 %t1
+}
+define i32 @test_i32_8388352_mask_lshr_9(i32 %a0) {
+; CHECK-LABEL: test_i32_8388352_mask_lshr_9:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #9, #14
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 8388352
+  %t1 = lshr i32 %t0, 9
+  ret i32 %t1
+}
+define i32 @test_i32_8388352_mask_lshr_10(i32 %a0) {
+; CHECK-LABEL: test_i32_8388352_mask_lshr_10:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #10, #13
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 8388352
+  %t1 = lshr i32 %t0, 10
+  ret i32 %t1
+}
+
+define i32 @test_i32_4294836224_mask_lshr_1(i32 %a0) {
+; CHECK-LABEL: test_i32_4294836224_mask_lshr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0xfffe0000
+; CHECK-NEXT:    lsr w0, w8, #1
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 4294836224
+  %t1 = lshr i32 %t0, 1
+  ret i32 %t1
+}
+define i32 @test_i32_4294836224_mask_lshr_16(i32 %a0) {
+; CHECK-LABEL: test_i32_4294836224_mask_lshr_16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0xfffe0000
+; CHECK-NEXT:    lsr w0, w8, #16
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 4294836224
+  %t1 = lshr i32 %t0, 16
+  ret i32 %t1
+}
+define i32 @test_i32_4294836224_mask_lshr_17(i32 %a0) {
+; CHECK-LABEL: test_i32_4294836224_mask_lshr_17:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsr w0, w0, #17
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 4294836224
+  %t1 = lshr i32 %t0, 17
+  ret i32 %t1
+}
+define i32 @test_i32_4294836224_mask_lshr_18(i32 %a0) {
+; CHECK-LABEL: test_i32_4294836224_mask_lshr_18:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsr w0, w0, #18
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 4294836224
+  %t1 = lshr i32 %t0, 18
+  ret i32 %t1
+}
+
+; ashr
+
+define i32 @test_i32_32767_mask_ashr_1(i32 %a0) {
+; CHECK-LABEL: test_i32_32767_mask_ashr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #1, #14
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 32767
+  %t1 = ashr i32 %t0, 1
+  ret i32 %t1
+}
+
+define i32 @test_i32_8388352_mask_ashr_7(i32 %a0) {
+; CHECK-LABEL: test_i32_8388352_mask_ashr_7:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x7fff00
+; CHECK-NEXT:    lsr w0, w8, #7
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 8388352
+  %t1 = ashr i32 %t0, 7
+  ret i32 %t1
+}
+define i32 @test_i32_8388352_mask_ashr_8(i32 %a0) {
+; CHECK-LABEL: test_i32_8388352_mask_ashr_8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #8, #15
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 8388352
+  %t1 = ashr i32 %t0, 8
+  ret i32 %t1
+}
+define i32 @test_i32_8388352_mask_ashr_9(i32 %a0) {
+; CHECK-LABEL: test_i32_8388352_mask_ashr_9:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #9, #14
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 8388352
+  %t1 = ashr i32 %t0, 9
+  ret i32 %t1
+}
+define i32 @test_i32_8388352_mask_ashr_10(i32 %a0) {
+; CHECK-LABEL: test_i32_8388352_mask_ashr_10:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx w0, w0, #10, #13
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 8388352
+  %t1 = ashr i32 %t0, 10
+  ret i32 %t1
+}
+
+define i32 @test_i32_4294836224_mask_ashr_1(i32 %a0) {
+; CHECK-LABEL: test_i32_4294836224_mask_ashr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0xfffe0000
+; CHECK-NEXT:    asr w0, w8, #1
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 4294836224
+  %t1 = ashr i32 %t0, 1
+  ret i32 %t1
+}
+define i32 @test_i32_4294836224_mask_ashr_16(i32 %a0) {
+; CHECK-LABEL: test_i32_4294836224_mask_ashr_16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0xfffe0000
+; CHECK-NEXT:    asr w0, w8, #16
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 4294836224
+  %t1 = ashr i32 %t0, 16
+  ret i32 %t1
+}
+define i32 @test_i32_4294836224_mask_ashr_17(i32 %a0) {
+; CHECK-LABEL: test_i32_4294836224_mask_ashr_17:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    asr w0, w0, #17
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 4294836224
+  %t1 = ashr i32 %t0, 17
+  ret i32 %t1
+}
+define i32 @test_i32_4294836224_mask_ashr_18(i32 %a0) {
+; CHECK-LABEL: test_i32_4294836224_mask_ashr_18:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    asr w0, w0, #18
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 4294836224
+  %t1 = ashr i32 %t0, 18
+  ret i32 %t1
+}
+
+; shl
+
+define i32 @test_i32_32767_mask_shl_1(i32 %a0) {
+; CHECK-LABEL: test_i32_32767_mask_shl_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x7fff
+; CHECK-NEXT:    lsl w0, w8, #1
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 32767
+  %t1 = shl i32 %t0, 1
+  ret i32 %t1
+}
+define i32 @test_i32_32767_mask_shl_16(i32 %a0) {
+; CHECK-LABEL: test_i32_32767_mask_shl_16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x7fff
+; CHECK-NEXT:    lsl w0, w8, #16
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 32767
+  %t1 = shl i32 %t0, 16
+  ret i32 %t1
+}
+define i32 @test_i32_32767_mask_shl_17(i32 %a0) {
+; CHECK-LABEL: test_i32_32767_mask_shl_17:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl w0, w0, #17
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 32767
+  %t1 = shl i32 %t0, 17
+  ret i32 %t1
+}
+define i32 @test_i32_32767_mask_shl_18(i32 %a0) {
+; CHECK-LABEL: test_i32_32767_mask_shl_18:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl w0, w0, #18
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 32767
+  %t1 = shl i32 %t0, 18
+  ret i32 %t1
+}
+
+define i32 @test_i32_8388352_mask_shl_7(i32 %a0) {
+; CHECK-LABEL: test_i32_8388352_mask_shl_7:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x7fff00
+; CHECK-NEXT:    lsl w0, w8, #7
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 8388352
+  %t1 = shl i32 %t0, 7
+  ret i32 %t1
+}
+define i32 @test_i32_8388352_mask_shl_8(i32 %a0) {
+; CHECK-LABEL: test_i32_8388352_mask_shl_8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x7fff00
+; CHECK-NEXT:    lsl w0, w8, #8
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 8388352
+  %t1 = shl i32 %t0, 8
+  ret i32 %t1
+}
+define i32 @test_i32_8388352_mask_shl_9(i32 %a0) {
+; CHECK-LABEL: test_i32_8388352_mask_shl_9:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x7fff00
+; CHECK-NEXT:    lsl w0, w8, #9
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 8388352
+  %t1 = shl i32 %t0, 9
+  ret i32 %t1
+}
+define i32 @test_i32_8388352_mask_shl_10(i32 %a0) {
+; CHECK-LABEL: test_i32_8388352_mask_shl_10:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x3fff00
+; CHECK-NEXT:    lsl w0, w8, #10
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 8388352
+  %t1 = shl i32 %t0, 10
+  ret i32 %t1
+}
+
+define i32 @test_i32_4294836224_mask_shl_1(i32 %a0) {
+; CHECK-LABEL: test_i32_4294836224_mask_shl_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x7ffe0000
+; CHECK-NEXT:    lsl w0, w8, #1
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, 4294836224
+  %t1 = shl i32 %t0, 1
+  ret i32 %t1
+}
+
+;------------------------------------------------------------------------------;
+; 64-bit
+;------------------------------------------------------------------------------;
+
+; lshr
+
+define i64 @test_i64_2147483647_mask_lshr_1(i64 %a0) {
+; CHECK-LABEL: test_i64_2147483647_mask_lshr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx x0, x0, #1, #30
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 2147483647
+  %t1 = lshr i64 %t0, 1
+  ret i64 %t1
+}
+
+define i64 @test_i64_140737488289792_mask_lshr_15(i64 %a0) {
+; CHECK-LABEL: test_i64_140737488289792_mask_lshr_15:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and x8, x0, #0x7fffffff0000
+; CHECK-NEXT:    lsr x0, x8, #15
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = lshr i64 %t0, 15
+  ret i64 %t1
+}
+define i64 @test_i64_140737488289792_mask_lshr_16(i64 %a0) {
+; CHECK-LABEL: test_i64_140737488289792_mask_lshr_16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx x0, x0, #16, #31
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = lshr i64 %t0, 16
+  ret i64 %t1
+}
+define i64 @test_i64_140737488289792_mask_lshr_17(i64 %a0) {
+; CHECK-LABEL: test_i64_140737488289792_mask_lshr_17:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx x0, x0, #17, #30
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = lshr i64 %t0, 17
+  ret i64 %t1
+}
+define i64 @test_i64_140737488289792_mask_lshr_18(i64 %a0) {
+; CHECK-LABEL: test_i64_140737488289792_mask_lshr_18:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx x0, x0, #18, #29
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = lshr i64 %t0, 18
+  ret i64 %t1
+}
+
+define i64 @test_i64_18446744065119617024_mask_lshr_1(i64 %a0) {
+; CHECK-LABEL: test_i64_18446744065119617024_mask_lshr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and x8, x0, #0xfffffffe00000000
+; CHECK-NEXT:    lsr x0, x8, #1
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 18446744065119617024
+  %t1 = lshr i64 %t0, 1
+  ret i64 %t1
+}
+define i64 @test_i64_18446744065119617024_mask_lshr_32(i64 %a0) {
+; CHECK-LABEL: test_i64_18446744065119617024_mask_lshr_32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and x8, x0, #0xfffffffe00000000
+; CHECK-NEXT:    lsr x0, x8, #32
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 18446744065119617024
+  %t1 = lshr i64 %t0, 32
+  ret i64 %t1
+}
+define i64 @test_i64_18446744065119617024_mask_lshr_33(i64 %a0) {
+; CHECK-LABEL: test_i64_18446744065119617024_mask_lshr_33:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsr x0, x0, #33
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 18446744065119617024
+  %t1 = lshr i64 %t0, 33
+  ret i64 %t1
+}
+define i64 @test_i64_18446744065119617024_mask_lshr_34(i64 %a0) {
+; CHECK-LABEL: test_i64_18446744065119617024_mask_lshr_34:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsr x0, x0, #34
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 18446744065119617024
+  %t1 = lshr i64 %t0, 34
+  ret i64 %t1
+}
+
+; ashr
+
+define i64 @test_i64_2147483647_mask_ashr_1(i64 %a0) {
+; CHECK-LABEL: test_i64_2147483647_mask_ashr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx x0, x0, #1, #30
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 2147483647
+  %t1 = ashr i64 %t0, 1
+  ret i64 %t1
+}
+
+define i64 @test_i64_140737488289792_mask_ashr_15(i64 %a0) {
+; CHECK-LABEL: test_i64_140737488289792_mask_ashr_15:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and x8, x0, #0x7fffffff0000
+; CHECK-NEXT:    lsr x0, x8, #15
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = ashr i64 %t0, 15
+  ret i64 %t1
+}
+define i64 @test_i64_140737488289792_mask_ashr_16(i64 %a0) {
+; CHECK-LABEL: test_i64_140737488289792_mask_ashr_16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx x0, x0, #16, #31
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = ashr i64 %t0, 16
+  ret i64 %t1
+}
+define i64 @test_i64_140737488289792_mask_ashr_17(i64 %a0) {
+; CHECK-LABEL: test_i64_140737488289792_mask_ashr_17:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx x0, x0, #17, #30
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = ashr i64 %t0, 17
+  ret i64 %t1
+}
+define i64 @test_i64_140737488289792_mask_ashr_18(i64 %a0) {
+; CHECK-LABEL: test_i64_140737488289792_mask_ashr_18:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ubfx x0, x0, #18, #29
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = ashr i64 %t0, 18
+  ret i64 %t1
+}
+
+define i64 @test_i64_18446744065119617024_mask_ashr_1(i64 %a0) {
+; CHECK-LABEL: test_i64_18446744065119617024_mask_ashr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and x8, x0, #0xfffffffe00000000
+; CHECK-NEXT:    asr x0, x8, #1
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 18446744065119617024
+  %t1 = ashr i64 %t0, 1
+  ret i64 %t1
+}
+define i64 @test_i64_18446744065119617024_mask_ashr_32(i64 %a0) {
+; CHECK-LABEL: test_i64_18446744065119617024_mask_ashr_32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and x8, x0, #0xfffffffe00000000
+; CHECK-NEXT:    asr x0, x8, #32
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 18446744065119617024
+  %t1 = ashr i64 %t0, 32
+  ret i64 %t1
+}
+define i64 @test_i64_18446744065119617024_mask_ashr_33(i64 %a0) {
+; CHECK-LABEL: test_i64_18446744065119617024_mask_ashr_33:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    asr x0, x0, #33
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 18446744065119617024
+  %t1 = ashr i64 %t0, 33
+  ret i64 %t1
+}
+define i64 @test_i64_18446744065119617024_mask_ashr_34(i64 %a0) {
+; CHECK-LABEL: test_i64_18446744065119617024_mask_ashr_34:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    asr x0, x0, #34
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 18446744065119617024
+  %t1 = ashr i64 %t0, 34
+  ret i64 %t1
+}
+
+; shl
+
+define i64 @test_i64_2147483647_mask_shl_1(i64 %a0) {
+; CHECK-LABEL: test_i64_2147483647_mask_shl_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and x8, x0, #0x7fffffff
+; CHECK-NEXT:    lsl x0, x8, #1
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 2147483647
+  %t1 = shl i64 %t0, 1
+  ret i64 %t1
+}
+define i64 @test_i64_2147483647_mask_shl_32(i64 %a0) {
+; CHECK-LABEL: test_i64_2147483647_mask_shl_32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x7fffffff
+; CHECK-NEXT:    lsl x0, x8, #32
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 2147483647
+  %t1 = shl i64 %t0, 32
+  ret i64 %t1
+}
+define i64 @test_i64_2147483647_mask_shl_33(i64 %a0) {
+; CHECK-LABEL: test_i64_2147483647_mask_shl_33:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl x0, x0, #33
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 2147483647
+  %t1 = shl i64 %t0, 33
+  ret i64 %t1
+}
+define i64 @test_i64_2147483647_mask_shl_34(i64 %a0) {
+; CHECK-LABEL: test_i64_2147483647_mask_shl_34:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl x0, x0, #34
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 2147483647
+  %t1 = shl i64 %t0, 34
+  ret i64 %t1
+}
+
+define i64 @test_i64_140737488289792_mask_shl_15(i64 %a0) {
+; CHECK-LABEL: test_i64_140737488289792_mask_shl_15:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and x8, x0, #0x7fffffff0000
+; CHECK-NEXT:    lsl x0, x8, #15
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = shl i64 %t0, 15
+  ret i64 %t1
+}
+define i64 @test_i64_140737488289792_mask_shl_16(i64 %a0) {
+; CHECK-LABEL: test_i64_140737488289792_mask_shl_16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and x8, x0, #0x7fffffff0000
+; CHECK-NEXT:    lsl x0, x8, #16
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = shl i64 %t0, 16
+  ret i64 %t1
+}
+define i64 @test_i64_140737488289792_mask_shl_17(i64 %a0) {
+; CHECK-LABEL: test_i64_140737488289792_mask_shl_17:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and x8, x0, #0x7fffffff0000
+; CHECK-NEXT:    lsl x0, x8, #17
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = shl i64 %t0, 17
+  ret i64 %t1
+}
+define i64 @test_i64_140737488289792_mask_shl_18(i64 %a0) {
+; CHECK-LABEL: test_i64_140737488289792_mask_shl_18:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and x8, x0, #0x3fffffff0000
+; CHECK-NEXT:    lsl x0, x8, #18
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = shl i64 %t0, 18
+  ret i64 %t1
+}
+
+define i64 @test_i64_18446744065119617024_mask_shl_1(i64 %a0) {
+; CHECK-LABEL: test_i64_18446744065119617024_mask_shl_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and x8, x0, #0x7ffffffe00000000
+; CHECK-NEXT:    lsl x0, x8, #1
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, 18446744065119617024
+  %t1 = shl i64 %t0, 1
+  ret i64 %t1
+}
diff --git a/llvm/test/CodeGen/AArch64/vector_splat-const-shift-of-constmasked.ll b/llvm/test/CodeGen/AArch64/vector_splat-const-shift-of-constmasked.ll
new file mode 100644
index 000000000000..d286c32d2712
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/vector_splat-const-shift-of-constmasked.ll
@@ -0,0 +1,1265 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
+
+; The mask is all-ones, potentially shifted.
+
+;------------------------------------------------------------------------------;
+; 128-bit vector; 8-bit elements = 16 elements
+;------------------------------------------------------------------------------;
+
+; lshr
+
+define <16 x i8> @test_128_i8_x_16_7_mask_lshr_1(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_7_mask_lshr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.16b, #7
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.16b, v0.16b, #1
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  %t1 = lshr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %t1
+}
+
+define <16 x i8> @test_128_i8_x_16_28_mask_lshr_1(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_28_mask_lshr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.16b, #28
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.16b, v0.16b, #1
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = lshr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_28_mask_lshr_2(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_28_mask_lshr_2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.16b, #28
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.16b, v0.16b, #2
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = lshr <16 x i8> %t0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_28_mask_lshr_3(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_28_mask_lshr_3:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.16b, #28
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.16b, v0.16b, #3
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = lshr <16 x i8> %t0, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_28_mask_lshr_4(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_28_mask_lshr_4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.16b, #28
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.16b, v0.16b, #4
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = lshr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
+  ret <16 x i8> %t1
+}
+
+define <16 x i8> @test_128_i8_x_16_224_mask_lshr_1(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_224_mask_lshr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.16b, #224
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.16b, v0.16b, #1
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
+  %t1 = lshr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_224_mask_lshr_4(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_224_mask_lshr_4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.16b, #224
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.16b, v0.16b, #4
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
+  %t1 = lshr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_224_mask_lshr_5(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_224_mask_lshr_5:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushr v0.16b, v0.16b, #5
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
+  %t1 = lshr <16 x i8> %t0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_224_mask_lshr_6(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_224_mask_lshr_6:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushr v0.16b, v0.16b, #6
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
+  %t1 = lshr <16 x i8> %t0, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
+  ret <16 x i8> %t1
+}
+
+; ashr
+
+define <16 x i8> @test_128_i8_x_16_7_mask_ashr_1(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_7_mask_ashr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.16b, #7
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.16b, v0.16b, #1
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  %t1 = ashr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %t1
+}
+
+define <16 x i8> @test_128_i8_x_16_28_mask_ashr_1(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_28_mask_ashr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.16b, #28
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.16b, v0.16b, #1
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = ashr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_28_mask_ashr_2(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_28_mask_ashr_2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.16b, #28
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.16b, v0.16b, #2
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = ashr <16 x i8> %t0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_28_mask_ashr_3(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_28_mask_ashr_3:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.16b, #28
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.16b, v0.16b, #3
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = ashr <16 x i8> %t0, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_28_mask_ashr_4(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_28_mask_ashr_4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.16b, #28
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.16b, v0.16b, #4
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = ashr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
+  ret <16 x i8> %t1
+}
+
+define <16 x i8> @test_128_i8_x_16_224_mask_ashr_1(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_224_mask_ashr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.16b, #224
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    sshr v0.16b, v0.16b, #1
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
+  %t1 = ashr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_224_mask_ashr_4(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_224_mask_ashr_4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.16b, #224
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    sshr v0.16b, v0.16b, #4
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
+  %t1 = ashr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_224_mask_ashr_5(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_224_mask_ashr_5:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sshr v0.16b, v0.16b, #5
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
+  %t1 = ashr <16 x i8> %t0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_224_mask_ashr_6(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_224_mask_ashr_6:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sshr v0.16b, v0.16b, #6
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
+  %t1 = ashr <16 x i8> %t0, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
+  ret <16 x i8> %t1
+}
+
+; shl
+
+define <16 x i8> @test_128_i8_x_16_7_mask_shl_1(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_7_mask_shl_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.16b, #7
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.16b, v0.16b, #1
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  %t1 = shl <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_7_mask_shl_4(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_7_mask_shl_4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.16b, #7
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.16b, v0.16b, #4
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  %t1 = shl <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_7_mask_shl_5(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_7_mask_shl_5:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    shl v0.16b, v0.16b, #5
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  %t1 = shl <16 x i8> %t0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_7_mask_shl_6(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_7_mask_shl_6:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    shl v0.16b, v0.16b, #6
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  %t1 = shl <16 x i8> %t0, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
+  ret <16 x i8> %t1
+}
+
+define <16 x i8> @test_128_i8_x_16_28_mask_shl_1(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_28_mask_shl_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.16b, #28
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.16b, v0.16b, #1
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = shl <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_28_mask_shl_2(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_28_mask_shl_2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.16b, #28
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.16b, v0.16b, #2
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = shl <16 x i8> %t0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_28_mask_shl_3(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_28_mask_shl_3:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.16b, #28
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.16b, v0.16b, #3
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = shl <16 x i8> %t0, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_28_mask_shl_4(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_28_mask_shl_4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.16b, #28
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.16b, v0.16b, #4
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = shl <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
+  ret <16 x i8> %t1
+}
+
+define <16 x i8> @test_128_i8_x_16_224_mask_shl_1(<16 x i8> %a0) {
+; CHECK-LABEL: test_128_i8_x_16_224_mask_shl_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.16b, #224
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.16b, v0.16b, #1
+; CHECK-NEXT:    ret
+  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
+  %t1 = shl <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %t1
+}
+
+;------------------------------------------------------------------------------;
+; 128-bit vector; 16-bit elements = 8 elements
+;------------------------------------------------------------------------------;
+
+; lshr
+
+define <8 x i16> @test_128_i16_x_8_127_mask_lshr_1(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_127_mask_lshr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.8h, #127
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.8h, v0.8h, #1
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
+  %t1 = lshr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %t1
+}
+
+define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_3(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_2032_mask_lshr_3:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #2032
+; CHECK-NEXT:    dup v1.8h, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.8h, v0.8h, #3
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = lshr <8 x i16> %t0, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_4(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_2032_mask_lshr_4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #2032
+; CHECK-NEXT:    dup v1.8h, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.8h, v0.8h, #4
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = lshr <8 x i16> %t0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_5(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_2032_mask_lshr_5:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #2032
+; CHECK-NEXT:    dup v1.8h, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.8h, v0.8h, #5
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = lshr <8 x i16> %t0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_6(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_2032_mask_lshr_6:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #2032
+; CHECK-NEXT:    dup v1.8h, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.8h, v0.8h, #6
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = lshr <8 x i16> %t0, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
+  ret <8 x i16> %t1
+}
+
+define <8 x i16> @test_128_i16_x_8_65024_mask_lshr_1(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_65024_mask_lshr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.8h, #254, lsl #8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.8h, v0.8h, #1
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
+  %t1 = lshr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_65024_mask_lshr_8(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_65024_mask_lshr_8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.8h, #254, lsl #8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.8h, v0.8h, #8
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
+  %t1 = lshr <8 x i16> %t0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_65024_mask_lshr_9(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_65024_mask_lshr_9:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushr v0.8h, v0.8h, #9
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
+  %t1 = lshr <8 x i16> %t0, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_65024_mask_lshr_10(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_65024_mask_lshr_10:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushr v0.8h, v0.8h, #10
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
+  %t1 = lshr <8 x i16> %t0, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
+  ret <8 x i16> %t1
+}
+
+; ashr
+
+define <8 x i16> @test_128_i16_x_8_127_mask_ashr_1(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_127_mask_ashr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.8h, #127
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.8h, v0.8h, #1
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
+  %t1 = ashr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %t1
+}
+
+define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_3(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_2032_mask_ashr_3:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #2032
+; CHECK-NEXT:    dup v1.8h, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.8h, v0.8h, #3
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = ashr <8 x i16> %t0, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_4(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_2032_mask_ashr_4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #2032
+; CHECK-NEXT:    dup v1.8h, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.8h, v0.8h, #4
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = ashr <8 x i16> %t0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_5(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_2032_mask_ashr_5:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #2032
+; CHECK-NEXT:    dup v1.8h, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.8h, v0.8h, #5
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = ashr <8 x i16> %t0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_6(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_2032_mask_ashr_6:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #2032
+; CHECK-NEXT:    dup v1.8h, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.8h, v0.8h, #6
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = ashr <8 x i16> %t0, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
+  ret <8 x i16> %t1
+}
+
+define <8 x i16> @test_128_i16_x_8_65024_mask_ashr_1(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_65024_mask_ashr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.8h, #254, lsl #8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    sshr v0.8h, v0.8h, #1
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
+  %t1 = ashr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_65024_mask_ashr_8(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_65024_mask_ashr_8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.8h, #254, lsl #8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    sshr v0.8h, v0.8h, #8
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
+  %t1 = ashr <8 x i16> %t0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_65024_mask_ashr_9(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_65024_mask_ashr_9:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sshr v0.8h, v0.8h, #9
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
+  %t1 = ashr <8 x i16> %t0, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_65024_mask_ashr_10(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_65024_mask_ashr_10:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sshr v0.8h, v0.8h, #10
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
+  %t1 = ashr <8 x i16> %t0, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
+  ret <8 x i16> %t1
+}
+
+; shl
+
+define <8 x i16> @test_128_i16_x_8_127_mask_shl_1(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_127_mask_shl_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.8h, #127
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.8h, v0.8h, #1
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
+  %t1 = shl <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_127_mask_shl_8(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_127_mask_shl_8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.8h, #127
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.8h, v0.8h, #8
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
+  %t1 = shl <8 x i16> %t0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_127_mask_shl_9(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_127_mask_shl_9:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    shl v0.8h, v0.8h, #9
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
+  %t1 = shl <8 x i16> %t0, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_127_mask_shl_10(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_127_mask_shl_10:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    shl v0.8h, v0.8h, #10
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
+  %t1 = shl <8 x i16> %t0, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
+  ret <8 x i16> %t1
+}
+
+define <8 x i16> @test_128_i16_x_8_2032_mask_shl_3(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_2032_mask_shl_3:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #2032
+; CHECK-NEXT:    dup v1.8h, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.8h, v0.8h, #3
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = shl <8 x i16> %t0, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_2032_mask_shl_4(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_2032_mask_shl_4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #2032
+; CHECK-NEXT:    dup v1.8h, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.8h, v0.8h, #4
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = shl <8 x i16> %t0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_2032_mask_shl_5(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_2032_mask_shl_5:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #2032
+; CHECK-NEXT:    dup v1.8h, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.8h, v0.8h, #5
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = shl <8 x i16> %t0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_2032_mask_shl_6(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_2032_mask_shl_6:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #2032
+; CHECK-NEXT:    dup v1.8h, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.8h, v0.8h, #6
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = shl <8 x i16> %t0, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
+  ret <8 x i16> %t1
+}
+
+define <8 x i16> @test_128_i16_x_8_65024_mask_shl_1(<8 x i16> %a0) {
+; CHECK-LABEL: test_128_i16_x_8_65024_mask_shl_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.8h, #254, lsl #8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.8h, v0.8h, #1
+; CHECK-NEXT:    ret
+  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
+  %t1 = shl <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %t1
+}
+
+;------------------------------------------------------------------------------;
+; 128-bit vector; 32-bit elements = 4 elements
+;------------------------------------------------------------------------------;
+
+; lshr
+
+define <4 x i32> @test_128_i32_x_4_32767_mask_lshr_1(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_32767_mask_lshr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.4s, #127, msl #8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.4s, v0.4s, #1
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
+  %t1 = lshr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %t1
+}
+
+define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_7(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_8388352_mask_lshr_7:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #8388352
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.4s, v0.4s, #7
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = lshr <4 x i32> %t0, <i32 7, i32 7, i32 7, i32 7>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_8(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_8388352_mask_lshr_8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #8388352
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.4s, v0.4s, #8
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = lshr <4 x i32> %t0, <i32 8, i32 8, i32 8, i32 8>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_9(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_8388352_mask_lshr_9:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #8388352
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.4s, v0.4s, #9
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = lshr <4 x i32> %t0, <i32 9, i32 9, i32 9, i32 9>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_10(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_8388352_mask_lshr_10:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #8388352
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.4s, v0.4s, #10
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = lshr <4 x i32> %t0, <i32 10, i32 10, i32 10, i32 10>
+  ret <4 x i32> %t1
+}
+
+define <4 x i32> @test_128_i32_x_4_4294836224_mask_lshr_1(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_lshr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mvni v1.4s, #1, msl #16
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.4s, v0.4s, #1
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
+  %t1 = lshr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_4294836224_mask_lshr_16(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_lshr_16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mvni v1.4s, #1, msl #16
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.4s, v0.4s, #16
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
+  %t1 = lshr <4 x i32> %t0, <i32 16, i32 16, i32 16, i32 16>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_4294836224_mask_lshr_17(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_lshr_17:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushr v0.4s, v0.4s, #17
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
+  %t1 = lshr <4 x i32> %t0, <i32 17, i32 17, i32 17, i32 17>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_4294836224_mask_lshr_18(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_lshr_18:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushr v0.4s, v0.4s, #18
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
+  %t1 = lshr <4 x i32> %t0, <i32 18, i32 18, i32 18, i32 18>
+  ret <4 x i32> %t1
+}
+
+; ashr
+
+define <4 x i32> @test_128_i32_x_4_32767_mask_ashr_1(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_32767_mask_ashr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.4s, #127, msl #8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.4s, v0.4s, #1
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
+  %t1 = ashr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %t1
+}
+
+define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_7(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_8388352_mask_ashr_7:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #8388352
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.4s, v0.4s, #7
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = ashr <4 x i32> %t0, <i32 7, i32 7, i32 7, i32 7>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_8(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_8388352_mask_ashr_8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #8388352
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.4s, v0.4s, #8
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = ashr <4 x i32> %t0, <i32 8, i32 8, i32 8, i32 8>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_9(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_8388352_mask_ashr_9:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #8388352
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.4s, v0.4s, #9
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = ashr <4 x i32> %t0, <i32 9, i32 9, i32 9, i32 9>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_10(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_8388352_mask_ashr_10:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #8388352
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.4s, v0.4s, #10
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = ashr <4 x i32> %t0, <i32 10, i32 10, i32 10, i32 10>
+  ret <4 x i32> %t1
+}
+
+define <4 x i32> @test_128_i32_x_4_4294836224_mask_ashr_1(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_ashr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mvni v1.4s, #1, msl #16
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    sshr v0.4s, v0.4s, #1
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
+  %t1 = ashr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_4294836224_mask_ashr_16(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_ashr_16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mvni v1.4s, #1, msl #16
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    sshr v0.4s, v0.4s, #16
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
+  %t1 = ashr <4 x i32> %t0, <i32 16, i32 16, i32 16, i32 16>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_4294836224_mask_ashr_17(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_ashr_17:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sshr v0.4s, v0.4s, #17
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
+  %t1 = ashr <4 x i32> %t0, <i32 17, i32 17, i32 17, i32 17>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_4294836224_mask_ashr_18(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_ashr_18:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sshr v0.4s, v0.4s, #18
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
+  %t1 = ashr <4 x i32> %t0, <i32 18, i32 18, i32 18, i32 18>
+  ret <4 x i32> %t1
+}
+
+; shl
+
+define <4 x i32> @test_128_i32_x_4_32767_mask_shl_1(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_32767_mask_shl_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.4s, #127, msl #8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.4s, v0.4s, #1
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
+  %t1 = shl <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_32767_mask_shl_16(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_32767_mask_shl_16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.4s, #127, msl #8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.4s, v0.4s, #16
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
+  %t1 = shl <4 x i32> %t0, <i32 16, i32 16, i32 16, i32 16>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_32767_mask_shl_17(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_32767_mask_shl_17:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    shl v0.4s, v0.4s, #17
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
+  %t1 = shl <4 x i32> %t0, <i32 17, i32 17, i32 17, i32 17>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_32767_mask_shl_18(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_32767_mask_shl_18:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    shl v0.4s, v0.4s, #18
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
+  %t1 = shl <4 x i32> %t0, <i32 18, i32 18, i32 18, i32 18>
+  ret <4 x i32> %t1
+}
+
+define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_7(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_8388352_mask_shl_7:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #8388352
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.4s, v0.4s, #7
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = shl <4 x i32> %t0, <i32 7, i32 7, i32 7, i32 7>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_8(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_8388352_mask_shl_8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #8388352
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.4s, v0.4s, #8
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = shl <4 x i32> %t0, <i32 8, i32 8, i32 8, i32 8>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_9(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_8388352_mask_shl_9:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #8388352
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.4s, v0.4s, #9
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = shl <4 x i32> %t0, <i32 9, i32 9, i32 9, i32 9>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_10(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_8388352_mask_shl_10:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #8388352
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.4s, v0.4s, #10
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = shl <4 x i32> %t0, <i32 10, i32 10, i32 10, i32 10>
+  ret <4 x i32> %t1
+}
+
+define <4 x i32> @test_128_i32_x_4_4294836224_mask_shl_1(<4 x i32> %a0) {
+; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_shl_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mvni v1.4s, #1, msl #16
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.4s, v0.4s, #1
+; CHECK-NEXT:    ret
+  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
+  %t1 = shl <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %t1
+}
+
+;------------------------------------------------------------------------------;
+; 128-bit vector; 64-bit elements = 2 elements
+;------------------------------------------------------------------------------;
+
+; lshr
+
+define <2 x i64> @test_128_i64_x_2_2147483647_mask_lshr_1(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_2147483647_mask_lshr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #2147483647
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.2d, v0.2d, #1
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
+  %t1 = lshr <2 x i64> %t0, <i64 1, i64 1>
+  ret <2 x i64> %t1
+}
+
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_15(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_15:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #140737488289792
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.2d, v0.2d, #15
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = lshr <2 x i64> %t0, <i64 15, i64 15>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_16(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #140737488289792
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.2d, v0.2d, #16
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = lshr <2 x i64> %t0, <i64 16, i64 16>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_17(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_17:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #140737488289792
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.2d, v0.2d, #17
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = lshr <2 x i64> %t0, <i64 17, i64 17>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_18(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_18:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #140737488289792
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.2d, v0.2d, #18
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = lshr <2 x i64> %t0, <i64 18, i64 18>
+  ret <2 x i64> %t1
+}
+
+define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_lshr_1(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #-8589934592
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.2d, v0.2d, #1
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
+  %t1 = lshr <2 x i64> %t0, <i64 1, i64 1>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_lshr_32(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #-8589934592
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.2d, v0.2d, #32
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
+  %t1 = lshr <2 x i64> %t0, <i64 32, i64 32>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_lshr_33(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_33:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushr v0.2d, v0.2d, #33
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
+  %t1 = lshr <2 x i64> %t0, <i64 33, i64 33>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_lshr_34(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_34:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushr v0.2d, v0.2d, #34
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
+  %t1 = lshr <2 x i64> %t0, <i64 34, i64 34>
+  ret <2 x i64> %t1
+}
+
+; ashr
+
+define <2 x i64> @test_128_i64_x_2_2147483647_mask_ashr_1(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_2147483647_mask_ashr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #2147483647
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.2d, v0.2d, #1
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
+  %t1 = ashr <2 x i64> %t0, <i64 1, i64 1>
+  ret <2 x i64> %t1
+}
+
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_15(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_15:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #140737488289792
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.2d, v0.2d, #15
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = ashr <2 x i64> %t0, <i64 15, i64 15>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_16(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #140737488289792
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.2d, v0.2d, #16
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = ashr <2 x i64> %t0, <i64 16, i64 16>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_17(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_17:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #140737488289792
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.2d, v0.2d, #17
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = ashr <2 x i64> %t0, <i64 17, i64 17>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_18(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_18:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #140737488289792
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ushr v0.2d, v0.2d, #18
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = ashr <2 x i64> %t0, <i64 18, i64 18>
+  ret <2 x i64> %t1
+}
+
+define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_1(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #-8589934592
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    sshr v0.2d, v0.2d, #1
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
+  %t1 = ashr <2 x i64> %t0, <i64 1, i64 1>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_32(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #-8589934592
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    sshr v0.2d, v0.2d, #32
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
+  %t1 = ashr <2 x i64> %t0, <i64 32, i64 32>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_33(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_33:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sshr v0.2d, v0.2d, #33
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
+  %t1 = ashr <2 x i64> %t0, <i64 33, i64 33>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_34(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_34:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sshr v0.2d, v0.2d, #34
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
+  %t1 = ashr <2 x i64> %t0, <i64 34, i64 34>
+  ret <2 x i64> %t1
+}
+
+; shl
+
+define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_1(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_2147483647_mask_shl_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #2147483647
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.2d, v0.2d, #1
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
+  %t1 = shl <2 x i64> %t0, <i64 1, i64 1>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_32(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_2147483647_mask_shl_32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #2147483647
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.2d, v0.2d, #32
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
+  %t1 = shl <2 x i64> %t0, <i64 32, i64 32>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_33(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_2147483647_mask_shl_33:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    shl v0.2d, v0.2d, #33
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
+  %t1 = shl <2 x i64> %t0, <i64 33, i64 33>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_34(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_2147483647_mask_shl_34:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    shl v0.2d, v0.2d, #34
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
+  %t1 = shl <2 x i64> %t0, <i64 34, i64 34>
+  ret <2 x i64> %t1
+}
+
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_15(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_shl_15:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #140737488289792
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.2d, v0.2d, #15
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = shl <2 x i64> %t0, <i64 15, i64 15>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_16(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_shl_16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #140737488289792
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.2d, v0.2d, #16
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = shl <2 x i64> %t0, <i64 16, i64 16>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_17(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_shl_17:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #140737488289792
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.2d, v0.2d, #17
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = shl <2 x i64> %t0, <i64 17, i64 17>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_18(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_shl_18:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #140737488289792
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.2d, v0.2d, #18
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = shl <2 x i64> %t0, <i64 18, i64 18>
+  ret <2 x i64> %t1
+}
+
+define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_shl_1(<2 x i64> %a0) {
+; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_shl_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #-8589934592
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.2d, v0.2d, #1
+; CHECK-NEXT:    ret
+  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
+  %t1 = shl <2 x i64> %t0, <i64 1, i64 1>
+  ret <2 x i64> %t1
+}
diff --git a/llvm/test/CodeGen/X86/const-shift-of-constmasked.ll b/llvm/test/CodeGen/X86/const-shift-of-constmasked.ll
new file mode 100644
index 000000000000..08ef7403af8a
--- /dev/null
+++ b/llvm/test/CodeGen/X86/const-shift-of-constmasked.ll
@@ -0,0 +1,2100 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefixes=ALL,X32
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=ALL,X64
+
+; The mask is all-ones, potentially shifted.
+
+;------------------------------------------------------------------------------;
+; 8-bit
+;------------------------------------------------------------------------------;
+
+; lshr
+
+define i8 @test_i8_7_mask_lshr_1(i8 %a0) {
+; X32-LABEL: test_i8_7_mask_lshr_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $6, %al
+; X32-NEXT:    shrb %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_7_mask_lshr_1:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andb $6, %al
+; X64-NEXT:    shrb %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 7
+  %t1 = lshr i8 %t0, 1
+  ret i8 %t1
+}
+
+define i8 @test_i8_28_mask_lshr_1(i8 %a0) {
+; X32-LABEL: test_i8_28_mask_lshr_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $28, %al
+; X32-NEXT:    shrb %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_28_mask_lshr_1:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andb $28, %al
+; X64-NEXT:    shrb %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 28
+  %t1 = lshr i8 %t0, 1
+  ret i8 %t1
+}
+define i8 @test_i8_28_mask_lshr_2(i8 %a0) {
+; X32-LABEL: test_i8_28_mask_lshr_2:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $28, %al
+; X32-NEXT:    shrb $2, %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_28_mask_lshr_2:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andb $28, %al
+; X64-NEXT:    shrb $2, %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 28
+  %t1 = lshr i8 %t0, 2
+  ret i8 %t1
+}
+define i8 @test_i8_28_mask_lshr_3(i8 %a0) {
+; X32-LABEL: test_i8_28_mask_lshr_3:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $24, %al
+; X32-NEXT:    shrb $3, %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_28_mask_lshr_3:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andb $24, %al
+; X64-NEXT:    shrb $3, %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 28
+  %t1 = lshr i8 %t0, 3
+  ret i8 %t1
+}
+define i8 @test_i8_28_mask_lshr_4(i8 %a0) {
+; X32-LABEL: test_i8_28_mask_lshr_4:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $16, %al
+; X32-NEXT:    shrb $4, %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_28_mask_lshr_4:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andb $16, %al
+; X64-NEXT:    shrb $4, %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 28
+  %t1 = lshr i8 %t0, 4
+  ret i8 %t1
+}
+
+define i8 @test_i8_224_mask_lshr_1(i8 %a0) {
+; X32-LABEL: test_i8_224_mask_lshr_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $-32, %al
+; X32-NEXT:    shrb %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_224_mask_lshr_1:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andb $-32, %al
+; X64-NEXT:    shrb %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 224
+  %t1 = lshr i8 %t0, 1
+  ret i8 %t1
+}
+define i8 @test_i8_224_mask_lshr_4(i8 %a0) {
+; X32-LABEL: test_i8_224_mask_lshr_4:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $-32, %al
+; X32-NEXT:    shrb $4, %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_224_mask_lshr_4:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andb $-32, %al
+; X64-NEXT:    shrb $4, %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 224
+  %t1 = lshr i8 %t0, 4
+  ret i8 %t1
+}
+define i8 @test_i8_224_mask_lshr_5(i8 %a0) {
+; X32-LABEL: test_i8_224_mask_lshr_5:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    shrb $5, %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_224_mask_lshr_5:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    shrb $5, %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 224
+  %t1 = lshr i8 %t0, 5
+  ret i8 %t1
+}
+define i8 @test_i8_224_mask_lshr_6(i8 %a0) {
+; X32-LABEL: test_i8_224_mask_lshr_6:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    shrb $6, %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_224_mask_lshr_6:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    shrb $6, %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 224
+  %t1 = lshr i8 %t0, 6
+  ret i8 %t1
+}
+
+; ashr
+
+define i8 @test_i8_7_mask_ashr_1(i8 %a0) {
+; X32-LABEL: test_i8_7_mask_ashr_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $6, %al
+; X32-NEXT:    shrb %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_7_mask_ashr_1:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andb $6, %al
+; X64-NEXT:    shrb %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 7
+  %t1 = ashr i8 %t0, 1
+  ret i8 %t1
+}
+
+define i8 @test_i8_28_mask_ashr_1(i8 %a0) {
+; X32-LABEL: test_i8_28_mask_ashr_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $28, %al
+; X32-NEXT:    shrb %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_28_mask_ashr_1:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andb $28, %al
+; X64-NEXT:    shrb %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 28
+  %t1 = ashr i8 %t0, 1
+  ret i8 %t1
+}
+define i8 @test_i8_28_mask_ashr_2(i8 %a0) {
+; X32-LABEL: test_i8_28_mask_ashr_2:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $28, %al
+; X32-NEXT:    shrb $2, %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_28_mask_ashr_2:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andb $28, %al
+; X64-NEXT:    shrb $2, %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 28
+  %t1 = ashr i8 %t0, 2
+  ret i8 %t1
+}
+define i8 @test_i8_28_mask_ashr_3(i8 %a0) {
+; X32-LABEL: test_i8_28_mask_ashr_3:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $24, %al
+; X32-NEXT:    shrb $3, %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_28_mask_ashr_3:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andb $24, %al
+; X64-NEXT:    shrb $3, %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 28
+  %t1 = ashr i8 %t0, 3
+  ret i8 %t1
+}
+define i8 @test_i8_28_mask_ashr_4(i8 %a0) {
+; X32-LABEL: test_i8_28_mask_ashr_4:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $16, %al
+; X32-NEXT:    shrb $4, %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_28_mask_ashr_4:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andb $16, %al
+; X64-NEXT:    shrb $4, %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 28
+  %t1 = ashr i8 %t0, 4
+  ret i8 %t1
+}
+
+define i8 @test_i8_224_mask_ashr_1(i8 %a0) {
+; X32-LABEL: test_i8_224_mask_ashr_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $-32, %al
+; X32-NEXT:    sarb %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_224_mask_ashr_1:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andb $-32, %al
+; X64-NEXT:    sarb %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 224
+  %t1 = ashr i8 %t0, 1
+  ret i8 %t1
+}
+define i8 @test_i8_224_mask_ashr_4(i8 %a0) {
+; X32-LABEL: test_i8_224_mask_ashr_4:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $-32, %al
+; X32-NEXT:    sarb $4, %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_224_mask_ashr_4:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andb $-32, %al
+; X64-NEXT:    sarb $4, %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 224
+  %t1 = ashr i8 %t0, 4
+  ret i8 %t1
+}
+define i8 @test_i8_224_mask_ashr_5(i8 %a0) {
+; X32-LABEL: test_i8_224_mask_ashr_5:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    sarb $5, %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_224_mask_ashr_5:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    sarb $5, %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 224
+  %t1 = ashr i8 %t0, 5
+  ret i8 %t1
+}
+define i8 @test_i8_224_mask_ashr_6(i8 %a0) {
+; X32-LABEL: test_i8_224_mask_ashr_6:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    sarb $6, %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_224_mask_ashr_6:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    sarb $6, %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 224
+  %t1 = ashr i8 %t0, 6
+  ret i8 %t1
+}
+
+; shl
+
+define i8 @test_i8_7_mask_shl_1(i8 %a0) {
+; X32-LABEL: test_i8_7_mask_shl_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $7, %al
+; X32-NEXT:    addb %al, %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_7_mask_shl_1:
+; X64:       # %bb.0:
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    andb $7, %dil
+; X64-NEXT:    leal (%rdi,%rdi), %eax
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 7
+  %t1 = shl i8 %t0, 1
+  ret i8 %t1
+}
+define i8 @test_i8_7_mask_shl_4(i8 %a0) {
+; X32-LABEL: test_i8_7_mask_shl_4:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $7, %al
+; X32-NEXT:    shlb $4, %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_7_mask_shl_4:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andb $7, %al
+; X64-NEXT:    shlb $4, %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 7
+  %t1 = shl i8 %t0, 4
+  ret i8 %t1
+}
+define i8 @test_i8_7_mask_shl_5(i8 %a0) {
+; X32-LABEL: test_i8_7_mask_shl_5:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    shlb $5, %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_7_mask_shl_5:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    shlb $5, %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 7
+  %t1 = shl i8 %t0, 5
+  ret i8 %t1
+}
+define i8 @test_i8_7_mask_shl_6(i8 %a0) {
+; X32-LABEL: test_i8_7_mask_shl_6:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    shlb $6, %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_7_mask_shl_6:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    shlb $6, %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 7
+  %t1 = shl i8 %t0, 6
+  ret i8 %t1
+}
+
+define i8 @test_i8_28_mask_shl_1(i8 %a0) {
+; X32-LABEL: test_i8_28_mask_shl_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $28, %al
+; X32-NEXT:    addb %al, %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_28_mask_shl_1:
+; X64:       # %bb.0:
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    andb $28, %dil
+; X64-NEXT:    leal (%rdi,%rdi), %eax
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 28
+  %t1 = shl i8 %t0, 1
+  ret i8 %t1
+}
+define i8 @test_i8_28_mask_shl_2(i8 %a0) {
+; X32-LABEL: test_i8_28_mask_shl_2:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $28, %al
+; X32-NEXT:    shlb $2, %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_28_mask_shl_2:
+; X64:       # %bb.0:
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    andb $28, %dil
+; X64-NEXT:    leal (,%rdi,4), %eax
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 28
+  %t1 = shl i8 %t0, 2
+  ret i8 %t1
+}
+define i8 @test_i8_28_mask_shl_3(i8 %a0) {
+; X32-LABEL: test_i8_28_mask_shl_3:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $28, %al
+; X32-NEXT:    shlb $3, %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_28_mask_shl_3:
+; X64:       # %bb.0:
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    andb $28, %dil
+; X64-NEXT:    leal (,%rdi,8), %eax
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 28
+  %t1 = shl i8 %t0, 3
+  ret i8 %t1
+}
+define i8 @test_i8_28_mask_shl_4(i8 %a0) {
+; X32-LABEL: test_i8_28_mask_shl_4:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $12, %al
+; X32-NEXT:    shlb $4, %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_28_mask_shl_4:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andb $12, %al
+; X64-NEXT:    shlb $4, %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 28
+  %t1 = shl i8 %t0, 4
+  ret i8 %t1
+}
+
+define i8 @test_i8_224_mask_shl_1(i8 %a0) {
+; X32-LABEL: test_i8_224_mask_shl_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $96, %al
+; X32-NEXT:    addb %al, %al
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i8_224_mask_shl_1:
+; X64:       # %bb.0:
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    andb $96, %dil
+; X64-NEXT:    leal (%rdi,%rdi), %eax
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+  %t0 = and i8 %a0, 224
+  %t1 = shl i8 %t0, 1
+  ret i8 %t1
+}
+
+;------------------------------------------------------------------------------;
+; 16-bit
+;------------------------------------------------------------------------------;
+
+; lshr
+
+define i16 @test_i16_127_mask_lshr_1(i16 %a0) {
+; X32-LABEL: test_i16_127_mask_lshr_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    andl $126, %eax
+; X32-NEXT:    shrl %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_127_mask_lshr_1:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $126, %eax
+; X64-NEXT:    shrl %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 127
+  %t1 = lshr i16 %t0, 1
+  ret i16 %t1
+}
+
+define i16 @test_i16_2032_mask_lshr_3(i16 %a0) {
+; X32-LABEL: test_i16_2032_mask_lshr_3:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    andl $2032, %eax # imm = 0x7F0
+; X32-NEXT:    shrl $3, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_2032_mask_lshr_3:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $2032, %eax # imm = 0x7F0
+; X64-NEXT:    shrl $3, %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 2032
+  %t1 = lshr i16 %t0, 3
+  ret i16 %t1
+}
+define i16 @test_i16_2032_mask_lshr_4(i16 %a0) {
+; X32-LABEL: test_i16_2032_mask_lshr_4:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $4, %eax
+; X32-NEXT:    andl $127, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_2032_mask_lshr_4:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    shrl $4, %eax
+; X64-NEXT:    andl $127, %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 2032
+  %t1 = lshr i16 %t0, 4
+  ret i16 %t1
+}
+define i16 @test_i16_2032_mask_lshr_5(i16 %a0) {
+; X32-LABEL: test_i16_2032_mask_lshr_5:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $5, %eax
+; X32-NEXT:    andl $63, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_2032_mask_lshr_5:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    shrl $5, %eax
+; X64-NEXT:    andl $63, %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 2032
+  %t1 = lshr i16 %t0, 5
+  ret i16 %t1
+}
+define i16 @test_i16_2032_mask_lshr_6(i16 %a0) {
+; X32-LABEL: test_i16_2032_mask_lshr_6:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $6, %eax
+; X32-NEXT:    andl $31, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_2032_mask_lshr_6:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    shrl $6, %eax
+; X64-NEXT:    andl $31, %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 2032
+  %t1 = lshr i16 %t0, 6
+  ret i16 %t1
+}
+
+define i16 @test_i16_65024_mask_lshr_1(i16 %a0) {
+; X32-LABEL: test_i16_65024_mask_lshr_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    andl $65024, %eax # imm = 0xFE00
+; X32-NEXT:    shrl %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_65024_mask_lshr_1:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $65024, %eax # imm = 0xFE00
+; X64-NEXT:    shrl %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 65024
+  %t1 = lshr i16 %t0, 1
+  ret i16 %t1
+}
+define i16 @test_i16_65024_mask_lshr_8(i16 %a0) {
+; X32-LABEL: test_i16_65024_mask_lshr_8:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    andl $65024, %eax # imm = 0xFE00
+; X32-NEXT:    shrl $8, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_65024_mask_lshr_8:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $65024, %eax # imm = 0xFE00
+; X64-NEXT:    shrl $8, %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 65024
+  %t1 = lshr i16 %t0, 8
+  ret i16 %t1
+}
+define i16 @test_i16_65024_mask_lshr_9(i16 %a0) {
+; X32-LABEL: test_i16_65024_mask_lshr_9:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $9, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_65024_mask_lshr_9:
+; X64:       # %bb.0:
+; X64-NEXT:    movzwl %di, %eax
+; X64-NEXT:    shrl $9, %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 65024
+  %t1 = lshr i16 %t0, 9
+  ret i16 %t1
+}
+define i16 @test_i16_65024_mask_lshr_10(i16 %a0) {
+; X32-LABEL: test_i16_65024_mask_lshr_10:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $10, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_65024_mask_lshr_10:
+; X64:       # %bb.0:
+; X64-NEXT:    movzwl %di, %eax
+; X64-NEXT:    shrl $10, %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 65024
+  %t1 = lshr i16 %t0, 10
+  ret i16 %t1
+}
+
+; ashr
+
+define i16 @test_i16_127_mask_ashr_1(i16 %a0) {
+; X32-LABEL: test_i16_127_mask_ashr_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    andl $126, %eax
+; X32-NEXT:    shrl %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_127_mask_ashr_1:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $126, %eax
+; X64-NEXT:    shrl %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 127
+  %t1 = ashr i16 %t0, 1
+  ret i16 %t1
+}
+
+define i16 @test_i16_2032_mask_ashr_3(i16 %a0) {
+; X32-LABEL: test_i16_2032_mask_ashr_3:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    andl $2032, %eax # imm = 0x7F0
+; X32-NEXT:    shrl $3, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_2032_mask_ashr_3:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $2032, %eax # imm = 0x7F0
+; X64-NEXT:    shrl $3, %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 2032
+  %t1 = ashr i16 %t0, 3
+  ret i16 %t1
+}
+define i16 @test_i16_2032_mask_ashr_4(i16 %a0) {
+; X32-LABEL: test_i16_2032_mask_ashr_4:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $4, %eax
+; X32-NEXT:    andl $127, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_2032_mask_ashr_4:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    shrl $4, %eax
+; X64-NEXT:    andl $127, %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 2032
+  %t1 = ashr i16 %t0, 4
+  ret i16 %t1
+}
+define i16 @test_i16_2032_mask_ashr_5(i16 %a0) {
+; X32-LABEL: test_i16_2032_mask_ashr_5:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $5, %eax
+; X32-NEXT:    andl $63, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_2032_mask_ashr_5:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    shrl $5, %eax
+; X64-NEXT:    andl $63, %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 2032
+  %t1 = ashr i16 %t0, 5
+  ret i16 %t1
+}
+define i16 @test_i16_2032_mask_ashr_6(i16 %a0) {
+; X32-LABEL: test_i16_2032_mask_ashr_6:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $6, %eax
+; X32-NEXT:    andl $31, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_2032_mask_ashr_6:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    shrl $6, %eax
+; X64-NEXT:    andl $31, %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 2032
+  %t1 = ashr i16 %t0, 6
+  ret i16 %t1
+}
+
+define i16 @test_i16_65024_mask_ashr_1(i16 %a0) {
+; X32-LABEL: test_i16_65024_mask_ashr_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    andl $65024, %eax # imm = 0xFE00
+; X32-NEXT:    cwtl
+; X32-NEXT:    shrl %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_65024_mask_ashr_1:
+; X64:       # %bb.0:
+; X64-NEXT:    andl $65024, %edi # imm = 0xFE00
+; X64-NEXT:    movswl %di, %eax
+; X64-NEXT:    shrl %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 65024
+  %t1 = ashr i16 %t0, 1
+  ret i16 %t1
+}
+define i16 @test_i16_65024_mask_ashr_8(i16 %a0) {
+; X32-LABEL: test_i16_65024_mask_ashr_8:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    andl $65024, %eax # imm = 0xFE00
+; X32-NEXT:    cwtl
+; X32-NEXT:    shrl $8, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_65024_mask_ashr_8:
+; X64:       # %bb.0:
+; X64-NEXT:    andl $65024, %edi # imm = 0xFE00
+; X64-NEXT:    movswl %di, %eax
+; X64-NEXT:    shrl $8, %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 65024
+  %t1 = ashr i16 %t0, 8
+  ret i16 %t1
+}
+define i16 @test_i16_65024_mask_ashr_9(i16 %a0) {
+; X32-LABEL: test_i16_65024_mask_ashr_9:
+; X32:       # %bb.0:
+; X32-NEXT:    movswl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $9, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_65024_mask_ashr_9:
+; X64:       # %bb.0:
+; X64-NEXT:    movswl %di, %eax
+; X64-NEXT:    shrl $9, %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 65024
+  %t1 = ashr i16 %t0, 9
+  ret i16 %t1
+}
+define i16 @test_i16_65024_mask_ashr_10(i16 %a0) {
+; X32-LABEL: test_i16_65024_mask_ashr_10:
+; X32:       # %bb.0:
+; X32-NEXT:    movswl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $10, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_65024_mask_ashr_10:
+; X64:       # %bb.0:
+; X64-NEXT:    movswl %di, %eax
+; X64-NEXT:    shrl $10, %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 65024
+  %t1 = ashr i16 %t0, 10
+  ret i16 %t1
+}
+
+; shl
+
+define i16 @test_i16_127_mask_shl_1(i16 %a0) {
+; X32-LABEL: test_i16_127_mask_shl_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    andl $127, %eax
+; X32-NEXT:    addl %eax, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_127_mask_shl_1:
+; X64:       # %bb.0:
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    andl $127, %edi
+; X64-NEXT:    leal (%rdi,%rdi), %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 127
+  %t1 = shl i16 %t0, 1
+  ret i16 %t1
+}
+define i16 @test_i16_127_mask_shl_8(i16 %a0) {
+; X32-LABEL: test_i16_127_mask_shl_8:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    andl $127, %eax
+; X32-NEXT:    shll $8, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_127_mask_shl_8:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $127, %eax
+; X64-NEXT:    shll $8, %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 127
+  %t1 = shl i16 %t0, 8
+  ret i16 %t1
+}
+define i16 @test_i16_127_mask_shl_9(i16 %a0) {
+; X32-LABEL: test_i16_127_mask_shl_9:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shll $9, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_127_mask_shl_9:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    shll $9, %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 127
+  %t1 = shl i16 %t0, 9
+  ret i16 %t1
+}
+define i16 @test_i16_127_mask_shl_10(i16 %a0) {
+; X32-LABEL: test_i16_127_mask_shl_10:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shll $10, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_127_mask_shl_10:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    shll $10, %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 127
+  %t1 = shl i16 %t0, 10
+  ret i16 %t1
+}
+
+define i16 @test_i16_2032_mask_shl_3(i16 %a0) {
+; X32-LABEL: test_i16_2032_mask_shl_3:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    andl $2032, %eax # imm = 0x7F0
+; X32-NEXT:    shll $3, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_2032_mask_shl_3:
+; X64:       # %bb.0:
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    andl $2032, %edi # imm = 0x7F0
+; X64-NEXT:    leal (,%rdi,8), %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 2032
+  %t1 = shl i16 %t0, 3
+  ret i16 %t1
+}
+define i16 @test_i16_2032_mask_shl_4(i16 %a0) {
+; X32-LABEL: test_i16_2032_mask_shl_4:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    andl $2032, %eax # imm = 0x7F0
+; X32-NEXT:    shll $4, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_2032_mask_shl_4:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $2032, %eax # imm = 0x7F0
+; X64-NEXT:    shll $4, %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 2032
+  %t1 = shl i16 %t0, 4
+  ret i16 %t1
+}
+define i16 @test_i16_2032_mask_shl_5(i16 %a0) {
+; X32-LABEL: test_i16_2032_mask_shl_5:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    andl $2032, %eax # imm = 0x7F0
+; X32-NEXT:    shll $5, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_2032_mask_shl_5:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $2032, %eax # imm = 0x7F0
+; X64-NEXT:    shll $5, %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 2032
+  %t1 = shl i16 %t0, 5
+  ret i16 %t1
+}
+define i16 @test_i16_2032_mask_shl_6(i16 %a0) {
+; X32-LABEL: test_i16_2032_mask_shl_6:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    andl $1008, %eax # imm = 0x3F0
+; X32-NEXT:    shll $6, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_2032_mask_shl_6:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $1008, %eax # imm = 0x3F0
+; X64-NEXT:    shll $6, %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 2032
+  %t1 = shl i16 %t0, 6
+  ret i16 %t1
+}
+
+define i16 @test_i16_65024_mask_shl_1(i16 %a0) {
+; X32-LABEL: test_i16_65024_mask_shl_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    andl $32256, %eax # imm = 0x7E00
+; X32-NEXT:    addl %eax, %eax
+; X32-NEXT:    # kill: def $ax killed $ax killed $eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i16_65024_mask_shl_1:
+; X64:       # %bb.0:
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    andl $32256, %edi # imm = 0x7E00
+; X64-NEXT:    leal (%rdi,%rdi), %eax
+; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    retq
+  %t0 = and i16 %a0, 65024
+  %t1 = shl i16 %t0, 1
+  ret i16 %t1
+}
+
+;------------------------------------------------------------------------------;
+; 32-bit
+;------------------------------------------------------------------------------;
+
+; lshr
+
+define i32 @test_i32_32767_mask_lshr_1(i32 %a0) {
+; X32-LABEL: test_i32_32767_mask_lshr_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $32766, %eax # imm = 0x7FFE
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_32767_mask_lshr_1:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $32766, %eax # imm = 0x7FFE
+; X64-NEXT:    shrl %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 32767
+  %t1 = lshr i32 %t0, 1
+  ret i32 %t1
+}
+
+define i32 @test_i32_8388352_mask_lshr_7(i32 %a0) {
+; X32-LABEL: test_i32_8388352_mask_lshr_7:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $8388352, %eax # imm = 0x7FFF00
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $7, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_8388352_mask_lshr_7:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $8388352, %eax # imm = 0x7FFF00
+; X64-NEXT:    shrl $7, %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 8388352
+  %t1 = lshr i32 %t0, 7
+  ret i32 %t1
+}
+define i32 @test_i32_8388352_mask_lshr_8(i32 %a0) {
+; X32-LABEL: test_i32_8388352_mask_lshr_8:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $8388352, %eax # imm = 0x7FFF00
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $8, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_8388352_mask_lshr_8:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $8388352, %eax # imm = 0x7FFF00
+; X64-NEXT:    shrl $8, %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 8388352
+  %t1 = lshr i32 %t0, 8
+  ret i32 %t1
+}
+define i32 @test_i32_8388352_mask_lshr_9(i32 %a0) {
+; X32-LABEL: test_i32_8388352_mask_lshr_9:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $8388096, %eax # imm = 0x7FFE00
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $9, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_8388352_mask_lshr_9:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $8388096, %eax # imm = 0x7FFE00
+; X64-NEXT:    shrl $9, %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 8388352
+  %t1 = lshr i32 %t0, 9
+  ret i32 %t1
+}
+define i32 @test_i32_8388352_mask_lshr_10(i32 %a0) {
+; X32-LABEL: test_i32_8388352_mask_lshr_10:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $8387584, %eax # imm = 0x7FFC00
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $10, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_8388352_mask_lshr_10:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $8387584, %eax # imm = 0x7FFC00
+; X64-NEXT:    shrl $10, %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 8388352
+  %t1 = lshr i32 %t0, 10
+  ret i32 %t1
+}
+
+define i32 @test_i32_4294836224_mask_lshr_1(i32 %a0) {
+; X32-LABEL: test_i32_4294836224_mask_lshr_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $-131072, %eax # imm = 0xFFFE0000
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_4294836224_mask_lshr_1:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $-131072, %eax # imm = 0xFFFE0000
+; X64-NEXT:    shrl %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 4294836224
+  %t1 = lshr i32 %t0, 1
+  ret i32 %t1
+}
+define i32 @test_i32_4294836224_mask_lshr_16(i32 %a0) {
+; X32-LABEL: test_i32_4294836224_mask_lshr_16:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $-131072, %eax # imm = 0xFFFE0000
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $16, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_4294836224_mask_lshr_16:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $-131072, %eax # imm = 0xFFFE0000
+; X64-NEXT:    shrl $16, %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 4294836224
+  %t1 = lshr i32 %t0, 16
+  ret i32 %t1
+}
+define i32 @test_i32_4294836224_mask_lshr_17(i32 %a0) {
+; X32-LABEL: test_i32_4294836224_mask_lshr_17:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $17, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_4294836224_mask_lshr_17:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    shrl $17, %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 4294836224
+  %t1 = lshr i32 %t0, 17
+  ret i32 %t1
+}
+define i32 @test_i32_4294836224_mask_lshr_18(i32 %a0) {
+; X32-LABEL: test_i32_4294836224_mask_lshr_18:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $18, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_4294836224_mask_lshr_18:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    shrl $18, %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 4294836224
+  %t1 = lshr i32 %t0, 18
+  ret i32 %t1
+}
+
+; ashr
+
+define i32 @test_i32_32767_mask_ashr_1(i32 %a0) {
+; X32-LABEL: test_i32_32767_mask_ashr_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $32766, %eax # imm = 0x7FFE
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_32767_mask_ashr_1:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $32766, %eax # imm = 0x7FFE
+; X64-NEXT:    shrl %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 32767
+  %t1 = ashr i32 %t0, 1
+  ret i32 %t1
+}
+
+define i32 @test_i32_8388352_mask_ashr_7(i32 %a0) {
+; X32-LABEL: test_i32_8388352_mask_ashr_7:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $8388352, %eax # imm = 0x7FFF00
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $7, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_8388352_mask_ashr_7:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $8388352, %eax # imm = 0x7FFF00
+; X64-NEXT:    shrl $7, %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 8388352
+  %t1 = ashr i32 %t0, 7
+  ret i32 %t1
+}
+define i32 @test_i32_8388352_mask_ashr_8(i32 %a0) {
+; X32-LABEL: test_i32_8388352_mask_ashr_8:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $8388352, %eax # imm = 0x7FFF00
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $8, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_8388352_mask_ashr_8:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $8388352, %eax # imm = 0x7FFF00
+; X64-NEXT:    shrl $8, %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 8388352
+  %t1 = ashr i32 %t0, 8
+  ret i32 %t1
+}
+define i32 @test_i32_8388352_mask_ashr_9(i32 %a0) {
+; X32-LABEL: test_i32_8388352_mask_ashr_9:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $8388096, %eax # imm = 0x7FFE00
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $9, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_8388352_mask_ashr_9:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $8388096, %eax # imm = 0x7FFE00
+; X64-NEXT:    shrl $9, %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 8388352
+  %t1 = ashr i32 %t0, 9
+  ret i32 %t1
+}
+define i32 @test_i32_8388352_mask_ashr_10(i32 %a0) {
+; X32-LABEL: test_i32_8388352_mask_ashr_10:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $8387584, %eax # imm = 0x7FFC00
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $10, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_8388352_mask_ashr_10:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $8387584, %eax # imm = 0x7FFC00
+; X64-NEXT:    shrl $10, %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 8388352
+  %t1 = ashr i32 %t0, 10
+  ret i32 %t1
+}
+
+define i32 @test_i32_4294836224_mask_ashr_1(i32 %a0) {
+; X32-LABEL: test_i32_4294836224_mask_ashr_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $-131072, %eax # imm = 0xFFFE0000
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    sarl %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_4294836224_mask_ashr_1:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $-131072, %eax # imm = 0xFFFE0000
+; X64-NEXT:    sarl %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 4294836224
+  %t1 = ashr i32 %t0, 1
+  ret i32 %t1
+}
+define i32 @test_i32_4294836224_mask_ashr_16(i32 %a0) {
+; X32-LABEL: test_i32_4294836224_mask_ashr_16:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $-131072, %eax # imm = 0xFFFE0000
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    sarl $16, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_4294836224_mask_ashr_16:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $-131072, %eax # imm = 0xFFFE0000
+; X64-NEXT:    sarl $16, %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 4294836224
+  %t1 = ashr i32 %t0, 16
+  ret i32 %t1
+}
+define i32 @test_i32_4294836224_mask_ashr_17(i32 %a0) {
+; X32-LABEL: test_i32_4294836224_mask_ashr_17:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    sarl $17, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_4294836224_mask_ashr_17:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    sarl $17, %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 4294836224
+  %t1 = ashr i32 %t0, 17
+  ret i32 %t1
+}
+define i32 @test_i32_4294836224_mask_ashr_18(i32 %a0) {
+; X32-LABEL: test_i32_4294836224_mask_ashr_18:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    sarl $18, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_4294836224_mask_ashr_18:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    sarl $18, %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 4294836224
+  %t1 = ashr i32 %t0, 18
+  ret i32 %t1
+}
+
+; shl
+
+define i32 @test_i32_32767_mask_shl_1(i32 %a0) {
+; X32-LABEL: test_i32_32767_mask_shl_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $32767, %eax # imm = 0x7FFF
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    addl %eax, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_32767_mask_shl_1:
+; X64:       # %bb.0:
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    andl $32767, %edi # imm = 0x7FFF
+; X64-NEXT:    leal (%rdi,%rdi), %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 32767
+  %t1 = shl i32 %t0, 1
+  ret i32 %t1
+}
+define i32 @test_i32_32767_mask_shl_16(i32 %a0) {
+; X32-LABEL: test_i32_32767_mask_shl_16:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $32767, %eax # imm = 0x7FFF
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shll $16, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_32767_mask_shl_16:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $32767, %eax # imm = 0x7FFF
+; X64-NEXT:    shll $16, %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 32767
+  %t1 = shl i32 %t0, 16
+  ret i32 %t1
+}
+define i32 @test_i32_32767_mask_shl_17(i32 %a0) {
+; X32-LABEL: test_i32_32767_mask_shl_17:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shll $17, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_32767_mask_shl_17:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    shll $17, %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 32767
+  %t1 = shl i32 %t0, 17
+  ret i32 %t1
+}
+define i32 @test_i32_32767_mask_shl_18(i32 %a0) {
+; X32-LABEL: test_i32_32767_mask_shl_18:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shll $18, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_32767_mask_shl_18:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    shll $18, %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 32767
+  %t1 = shl i32 %t0, 18
+  ret i32 %t1
+}
+
+define i32 @test_i32_8388352_mask_shl_7(i32 %a0) {
+; X32-LABEL: test_i32_8388352_mask_shl_7:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $8388352, %eax # imm = 0x7FFF00
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shll $7, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_8388352_mask_shl_7:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $8388352, %eax # imm = 0x7FFF00
+; X64-NEXT:    shll $7, %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 8388352
+  %t1 = shl i32 %t0, 7
+  ret i32 %t1
+}
+define i32 @test_i32_8388352_mask_shl_8(i32 %a0) {
+; X32-LABEL: test_i32_8388352_mask_shl_8:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $8388352, %eax # imm = 0x7FFF00
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shll $8, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_8388352_mask_shl_8:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $8388352, %eax # imm = 0x7FFF00
+; X64-NEXT:    shll $8, %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 8388352
+  %t1 = shl i32 %t0, 8
+  ret i32 %t1
+}
+define i32 @test_i32_8388352_mask_shl_9(i32 %a0) {
+; X32-LABEL: test_i32_8388352_mask_shl_9:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $8388352, %eax # imm = 0x7FFF00
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shll $9, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_8388352_mask_shl_9:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $8388352, %eax # imm = 0x7FFF00
+; X64-NEXT:    shll $9, %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 8388352
+  %t1 = shl i32 %t0, 9
+  ret i32 %t1
+}
+define i32 @test_i32_8388352_mask_shl_10(i32 %a0) {
+; X32-LABEL: test_i32_8388352_mask_shl_10:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $4194048, %eax # imm = 0x3FFF00
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shll $10, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_8388352_mask_shl_10:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl $4194048, %eax # imm = 0x3FFF00
+; X64-NEXT:    shll $10, %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 8388352
+  %t1 = shl i32 %t0, 10
+  ret i32 %t1
+}
+
+define i32 @test_i32_4294836224_mask_shl_1(i32 %a0) {
+; X32-LABEL: test_i32_4294836224_mask_shl_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $2147352576, %eax # imm = 0x7FFE0000
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    addl %eax, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i32_4294836224_mask_shl_1:
+; X64:       # %bb.0:
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    andl $2147352576, %edi # imm = 0x7FFE0000
+; X64-NEXT:    leal (%rdi,%rdi), %eax
+; X64-NEXT:    retq
+  %t0 = and i32 %a0, 4294836224
+  %t1 = shl i32 %t0, 1
+  ret i32 %t1
+}
+
+;------------------------------------------------------------------------------;
+; 64-bit
+;------------------------------------------------------------------------------;
+
+; lshr
+
+define i64 @test_i64_2147483647_mask_lshr_1(i64 %a0) {
+; X32-LABEL: test_i64_2147483647_mask_lshr_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $2147483646, %eax # imm = 0x7FFFFFFE
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl %eax
+; X32-NEXT:    xorl %edx, %edx
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_2147483647_mask_lshr_1:
+; X64:       # %bb.0:
+; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    andl $2147483646, %eax # imm = 0x7FFFFFFE
+; X64-NEXT:    shrq %rax
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 2147483647
+  %t1 = lshr i64 %t0, 1
+  ret i64 %t1
+}
+
+define i64 @test_i64_140737488289792_mask_lshr_15(i64 %a0) {
+; X32-LABEL: test_i64_140737488289792_mask_lshr_15:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    shll $16, %ecx
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shldl $17, %ecx, %eax
+; X32-NEXT:    xorl %edx, %edx
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_140737488289792_mask_lshr_15:
+; X64:       # %bb.0:
+; X64-NEXT:    movabsq $140737488289792, %rax # imm = 0x7FFFFFFF0000
+; X64-NEXT:    andq %rdi, %rax
+; X64-NEXT:    shrq $15, %rax
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = lshr i64 %t0, 15
+  ret i64 %t1
+}
+define i64 @test_i64_140737488289792_mask_lshr_16(i64 %a0) {
+; X32-LABEL: test_i64_140737488289792_mask_lshr_16:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    movl $32767, %eax # imm = 0x7FFF
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shll $16, %eax
+; X32-NEXT:    orl %ecx, %eax
+; X32-NEXT:    xorl %edx, %edx
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_140737488289792_mask_lshr_16:
+; X64:       # %bb.0:
+; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    shrq $16, %rax
+; X64-NEXT:    andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = lshr i64 %t0, 16
+  ret i64 %t1
+}
+define i64 @test_i64_140737488289792_mask_lshr_17(i64 %a0) {
+; X32-LABEL: test_i64_140737488289792_mask_lshr_17:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    movl $32767, %eax # imm = 0x7FFF
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shldl $15, %ecx, %eax
+; X32-NEXT:    xorl %edx, %edx
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_140737488289792_mask_lshr_17:
+; X64:       # %bb.0:
+; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    shrq $17, %rax
+; X64-NEXT:    andl $1073741823, %eax # imm = 0x3FFFFFFF
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = lshr i64 %t0, 17
+  ret i64 %t1
+}
+define i64 @test_i64_140737488289792_mask_lshr_18(i64 %a0) {
+; X32-LABEL: test_i64_140737488289792_mask_lshr_18:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    movl $32767, %eax # imm = 0x7FFF
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shldl $14, %ecx, %eax
+; X32-NEXT:    xorl %edx, %edx
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_140737488289792_mask_lshr_18:
+; X64:       # %bb.0:
+; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    shrq $18, %rax
+; X64-NEXT:    andl $536870911, %eax # imm = 0x1FFFFFFF
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = lshr i64 %t0, 18
+  ret i64 %t1
+}
+
+define i64 @test_i64_18446744065119617024_mask_lshr_1(i64 %a0) {
+; X32-LABEL: test_i64_18446744065119617024_mask_lshr_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    shrl %edx
+; X32-NEXT:    xorl %eax, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_18446744065119617024_mask_lshr_1:
+; X64:       # %bb.0:
+; X64-NEXT:    movabsq $-8589934592, %rax # imm = 0xFFFFFFFE00000000
+; X64-NEXT:    andq %rdi, %rax
+; X64-NEXT:    shrq %rax
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 18446744065119617024
+  %t1 = lshr i64 %t0, 1
+  ret i64 %t1
+}
+define i64 @test_i64_18446744065119617024_mask_lshr_32(i64 %a0) {
+; X32-LABEL: test_i64_18446744065119617024_mask_lshr_32:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    andl $-2, %eax
+; X32-NEXT:    xorl %edx, %edx
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_18446744065119617024_mask_lshr_32:
+; X64:       # %bb.0:
+; X64-NEXT:    movabsq $-8589934592, %rax # imm = 0xFFFFFFFE00000000
+; X64-NEXT:    andq %rdi, %rax
+; X64-NEXT:    shrq $32, %rax
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 18446744065119617024
+  %t1 = lshr i64 %t0, 32
+  ret i64 %t1
+}
+define i64 @test_i64_18446744065119617024_mask_lshr_33(i64 %a0) {
+; X32-LABEL: test_i64_18446744065119617024_mask_lshr_33:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl %eax
+; X32-NEXT:    xorl %edx, %edx
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_18446744065119617024_mask_lshr_33:
+; X64:       # %bb.0:
+; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    shrq $33, %rax
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 18446744065119617024
+  %t1 = lshr i64 %t0, 33
+  ret i64 %t1
+}
+define i64 @test_i64_18446744065119617024_mask_lshr_34(i64 %a0) {
+; X32-LABEL: test_i64_18446744065119617024_mask_lshr_34:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl $2, %eax
+; X32-NEXT:    xorl %edx, %edx
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_18446744065119617024_mask_lshr_34:
+; X64:       # %bb.0:
+; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    shrq $34, %rax
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 18446744065119617024
+  %t1 = lshr i64 %t0, 34
+  ret i64 %t1
+}
+
+; ashr
+
+define i64 @test_i64_2147483647_mask_ashr_1(i64 %a0) {
+; X32-LABEL: test_i64_2147483647_mask_ashr_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $2147483646, %eax # imm = 0x7FFFFFFE
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shrl %eax
+; X32-NEXT:    xorl %edx, %edx
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_2147483647_mask_ashr_1:
+; X64:       # %bb.0:
+; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    andl $2147483646, %eax # imm = 0x7FFFFFFE
+; X64-NEXT:    shrq %rax
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 2147483647
+  %t1 = ashr i64 %t0, 1
+  ret i64 %t1
+}
+
+define i64 @test_i64_140737488289792_mask_ashr_15(i64 %a0) {
+; X32-LABEL: test_i64_140737488289792_mask_ashr_15:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    shll $16, %ecx
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shldl $17, %ecx, %eax
+; X32-NEXT:    xorl %edx, %edx
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_140737488289792_mask_ashr_15:
+; X64:       # %bb.0:
+; X64-NEXT:    movabsq $140737488289792, %rax # imm = 0x7FFFFFFF0000
+; X64-NEXT:    andq %rdi, %rax
+; X64-NEXT:    shrq $15, %rax
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = ashr i64 %t0, 15
+  ret i64 %t1
+}
+define i64 @test_i64_140737488289792_mask_ashr_16(i64 %a0) {
+; X32-LABEL: test_i64_140737488289792_mask_ashr_16:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    movl $32767, %eax # imm = 0x7FFF
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shll $16, %eax
+; X32-NEXT:    orl %ecx, %eax
+; X32-NEXT:    xorl %edx, %edx
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_140737488289792_mask_ashr_16:
+; X64:       # %bb.0:
+; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    shrq $16, %rax
+; X64-NEXT:    andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = ashr i64 %t0, 16
+  ret i64 %t1
+}
+define i64 @test_i64_140737488289792_mask_ashr_17(i64 %a0) {
+; X32-LABEL: test_i64_140737488289792_mask_ashr_17:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    movl $32767, %eax # imm = 0x7FFF
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shldl $15, %ecx, %eax
+; X32-NEXT:    xorl %edx, %edx
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_140737488289792_mask_ashr_17:
+; X64:       # %bb.0:
+; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    shrq $17, %rax
+; X64-NEXT:    andl $1073741823, %eax # imm = 0x3FFFFFFF
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = ashr i64 %t0, 17
+  ret i64 %t1
+}
+define i64 @test_i64_140737488289792_mask_ashr_18(i64 %a0) {
+; X32-LABEL: test_i64_140737488289792_mask_ashr_18:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    movl $32767, %eax # imm = 0x7FFF
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shldl $14, %ecx, %eax
+; X32-NEXT:    xorl %edx, %edx
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_140737488289792_mask_ashr_18:
+; X64:       # %bb.0:
+; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    shrq $18, %rax
+; X64-NEXT:    andl $536870911, %eax # imm = 0x1FFFFFFF
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = ashr i64 %t0, 18
+  ret i64 %t1
+}
+
+define i64 @test_i64_18446744065119617024_mask_ashr_1(i64 %a0) {
+; X32-LABEL: test_i64_18446744065119617024_mask_ashr_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    sarl %edx
+; X32-NEXT:    xorl %eax, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_18446744065119617024_mask_ashr_1:
+; X64:       # %bb.0:
+; X64-NEXT:    movabsq $-8589934592, %rax # imm = 0xFFFFFFFE00000000
+; X64-NEXT:    andq %rdi, %rax
+; X64-NEXT:    sarq %rax
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 18446744065119617024
+  %t1 = ashr i64 %t0, 1
+  ret i64 %t1
+}
+define i64 @test_i64_18446744065119617024_mask_ashr_32(i64 %a0) {
+; X32-LABEL: test_i64_18446744065119617024_mask_ashr_32:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    andl $-2, %eax
+; X32-NEXT:    movl %eax, %edx
+; X32-NEXT:    sarl $31, %edx
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_18446744065119617024_mask_ashr_32:
+; X64:       # %bb.0:
+; X64-NEXT:    movabsq $-8589934592, %rax # imm = 0xFFFFFFFE00000000
+; X64-NEXT:    andq %rdi, %rax
+; X64-NEXT:    sarq $32, %rax
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 18446744065119617024
+  %t1 = ashr i64 %t0, 32
+  ret i64 %t1
+}
+define i64 @test_i64_18446744065119617024_mask_ashr_33(i64 %a0) {
+; X32-LABEL: test_i64_18446744065119617024_mask_ashr_33:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    movl %edx, %eax
+; X32-NEXT:    sarl %eax
+; X32-NEXT:    sarl $31, %edx
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_18446744065119617024_mask_ashr_33:
+; X64:       # %bb.0:
+; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    sarq $33, %rax
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 18446744065119617024
+  %t1 = ashr i64 %t0, 33
+  ret i64 %t1
+}
+define i64 @test_i64_18446744065119617024_mask_ashr_34(i64 %a0) {
+; X32-LABEL: test_i64_18446744065119617024_mask_ashr_34:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    movl %edx, %eax
+; X32-NEXT:    sarl $2, %eax
+; X32-NEXT:    sarl $31, %edx
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_18446744065119617024_mask_ashr_34:
+; X64:       # %bb.0:
+; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    sarq $34, %rax
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 18446744065119617024
+  %t1 = ashr i64 %t0, 34
+  ret i64 %t1
+}
+
+; shl
+
+define i64 @test_i64_2147483647_mask_shl_1(i64 %a0) {
+; X32-LABEL: test_i64_2147483647_mask_shl_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    addl %eax, %eax
+; X32-NEXT:    xorl %edx, %edx
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_2147483647_mask_shl_1:
+; X64:       # %bb.0:
+; X64-NEXT:    andl $2147483647, %edi # imm = 0x7FFFFFFF
+; X64-NEXT:    leaq (%rdi,%rdi), %rax
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 2147483647
+  %t1 = shl i64 %t0, 1
+  ret i64 %t1
+}
+define i64 @test_i64_2147483647_mask_shl_32(i64 %a0) {
+; X32-LABEL: test_i64_2147483647_mask_shl_32:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $2147483647, %edx # imm = 0x7FFFFFFF
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    xorl %eax, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_2147483647_mask_shl_32:
+; X64:       # %bb.0:
+; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT:    shlq $32, %rax
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 2147483647
+  %t1 = shl i64 %t0, 32
+  ret i64 %t1
+}
+define i64 @test_i64_2147483647_mask_shl_33(i64 %a0) {
+; X32-LABEL: test_i64_2147483647_mask_shl_33:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    addl %edx, %edx
+; X32-NEXT:    xorl %eax, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_2147483647_mask_shl_33:
+; X64:       # %bb.0:
+; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    shlq $33, %rax
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 2147483647
+  %t1 = shl i64 %t0, 33
+  ret i64 %t1
+}
+define i64 @test_i64_2147483647_mask_shl_34(i64 %a0) {
+; X32-LABEL: test_i64_2147483647_mask_shl_34:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    shll $2, %edx
+; X32-NEXT:    xorl %eax, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_2147483647_mask_shl_34:
+; X64:       # %bb.0:
+; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    shlq $34, %rax
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 2147483647
+  %t1 = shl i64 %t0, 34
+  ret i64 %t1
+}
+
+define i64 @test_i64_140737488289792_mask_shl_15(i64 %a0) {
+; X32-LABEL: test_i64_140737488289792_mask_shl_15:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movl %eax, %ecx
+; X32-NEXT:    shll $16, %ecx
+; X32-NEXT:    movl $32767, %edx # imm = 0x7FFF
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    shldl $15, %ecx, %edx
+; X32-NEXT:    shll $31, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_140737488289792_mask_shl_15:
+; X64:       # %bb.0:
+; X64-NEXT:    movabsq $140737488289792, %rax # imm = 0x7FFFFFFF0000
+; X64-NEXT:    andq %rdi, %rax
+; X64-NEXT:    shlq $15, %rax
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = shl i64 %t0, 15
+  ret i64 %t1
+}
+define i64 @test_i64_140737488289792_mask_shl_16(i64 %a0) {
+; X32-LABEL: test_i64_140737488289792_mask_shl_16:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shll $16, %eax
+; X32-NEXT:    movl $32767, %edx # imm = 0x7FFF
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    shldl $16, %eax, %edx
+; X32-NEXT:    xorl %eax, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_140737488289792_mask_shl_16:
+; X64:       # %bb.0:
+; X64-NEXT:    movabsq $140737488289792, %rax # imm = 0x7FFFFFFF0000
+; X64-NEXT:    andq %rdi, %rax
+; X64-NEXT:    shlq $16, %rax
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = shl i64 %t0, 16
+  ret i64 %t1
+}
+define i64 @test_i64_140737488289792_mask_shl_17(i64 %a0) {
+; X32-LABEL: test_i64_140737488289792_mask_shl_17:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shll $16, %eax
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    shldl $17, %eax, %edx
+; X32-NEXT:    xorl %eax, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_140737488289792_mask_shl_17:
+; X64:       # %bb.0:
+; X64-NEXT:    movabsq $140737488289792, %rax # imm = 0x7FFFFFFF0000
+; X64-NEXT:    andq %rdi, %rax
+; X64-NEXT:    shlq $17, %rax
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = shl i64 %t0, 17
+  ret i64 %t1
+}
+define i64 @test_i64_140737488289792_mask_shl_18(i64 %a0) {
+; X32-LABEL: test_i64_140737488289792_mask_shl_18:
+; X32:       # %bb.0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shll $16, %eax
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    shldl $18, %eax, %edx
+; X32-NEXT:    xorl %eax, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_140737488289792_mask_shl_18:
+; X64:       # %bb.0:
+; X64-NEXT:    movabsq $70368744112128, %rax # imm = 0x3FFFFFFF0000
+; X64-NEXT:    andq %rdi, %rax
+; X64-NEXT:    shlq $18, %rax
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 140737488289792
+  %t1 = shl i64 %t0, 18
+  ret i64 %t1
+}
+
+define i64 @test_i64_18446744065119617024_mask_shl_1(i64 %a0) {
+; X32-LABEL: test_i64_18446744065119617024_mask_shl_1:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $2147483646, %edx # imm = 0x7FFFFFFE
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    addl %edx, %edx
+; X32-NEXT:    xorl %eax, %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: test_i64_18446744065119617024_mask_shl_1:
+; X64:       # %bb.0:
+; X64-NEXT:    movabsq $9223372028264841216, %rax # imm = 0x7FFFFFFE00000000
+; X64-NEXT:    andq %rdi, %rax
+; X64-NEXT:    addq %rax, %rax
+; X64-NEXT:    retq
+  %t0 = and i64 %a0, 18446744065119617024
+  %t1 = shl i64 %t0, 1
+  ret i64 %t1
+}
diff --git a/llvm/test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll b/llvm/test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll
new file mode 100644
index 000000000000..ce9ed0d21baf
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll
@@ -0,0 +1,3536 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2              | FileCheck %s --check-prefixes=ALL,X32,X32-SSE2,X32-SSE2ONLY
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2,+avx         | FileCheck %s --check-prefixes=ALL,X32,X32-SSE2,X32-SSE2AVX,X32-SSE2AVX1
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2,+avx,+avx2   | FileCheck %s --check-prefixes=ALL,X32,X32-SSE2,X32-SSE2AVX,X32-SSE2AVX1AVX2
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2            | FileCheck %s --check-prefixes=ALL,X64,X64-SSE2,X64-SSE2ONLY
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,+avx       | FileCheck %s --check-prefixes=ALL,X64,X64-SSE2,X64-SSE2AVX,X64-SSE2AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,+avx,+avx2 | FileCheck %s --check-prefixes=ALL,X64,X64-SSE2,X64-SSE2AVX,X64-SSE2AVX1AVX2
+
+; The mask is all-ones, potentially shifted.
+
+;------------------------------------------------------------------------------;
+; 128-bit vector; 8-bit elements = 16 elements
+;------------------------------------------------------------------------------;
+
+; lshr
+
+define <16 x i8> @test_128_i8_x_16_7_mask_lshr_1(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_7_mask_lshr_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $1, %xmm0
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_7_mask_lshr_1:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $1, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_7_mask_lshr_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $1, %xmm0
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_7_mask_lshr_1:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $1, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  %t1 = lshr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %t1
+}
+
+define <16 x i8> @test_128_i8_x_16_28_mask_lshr_1(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_lshr_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $1, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_lshr_1:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $1, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_lshr_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $1, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_lshr_1:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $1, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = lshr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_28_mask_lshr_2(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_lshr_2:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $2, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_lshr_2:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $2, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_lshr_2:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $2, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_lshr_2:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $2, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = lshr <16 x i8> %t0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_28_mask_lshr_3(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_lshr_3:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $3, %xmm0
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_lshr_3:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $3, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_lshr_3:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $3, %xmm0
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_lshr_3:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $3, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = lshr <16 x i8> %t0, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_28_mask_lshr_4(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_lshr_4:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $4, %xmm0
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_lshr_4:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $4, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_lshr_4:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $4, %xmm0
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_lshr_4:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $4, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = lshr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
+  ret <16 x i8> %t1
+}
+
+define <16 x i8> @test_128_i8_x_16_224_mask_lshr_1(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_224_mask_lshr_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $1, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_224_mask_lshr_1:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $1, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_224_mask_lshr_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $1, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_224_mask_lshr_1:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $1, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
+  %t1 = lshr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_224_mask_lshr_4(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_224_mask_lshr_4:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $4, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_224_mask_lshr_4:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $4, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_224_mask_lshr_4:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $4, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_224_mask_lshr_4:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $4, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
+  %t1 = lshr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_224_mask_lshr_5(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_224_mask_lshr_5:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    psrlw $5, %xmm0
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_224_mask_lshr_5:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpsrlw $5, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_224_mask_lshr_5:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    psrlw $5, %xmm0
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_224_mask_lshr_5:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpsrlw $5, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
+  %t1 = lshr <16 x i8> %t0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_224_mask_lshr_6(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_224_mask_lshr_6:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    psrlw $6, %xmm0
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_224_mask_lshr_6:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpsrlw $6, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_224_mask_lshr_6:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    psrlw $6, %xmm0
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_224_mask_lshr_6:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpsrlw $6, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
+  %t1 = lshr <16 x i8> %t0, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
+  ret <16 x i8> %t1
+}
+
+; ashr
+
+define <16 x i8> @test_128_i8_x_16_7_mask_ashr_1(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_7_mask_ashr_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $1, %xmm0
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_7_mask_ashr_1:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $1, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_7_mask_ashr_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $1, %xmm0
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_7_mask_ashr_1:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $1, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  %t1 = ashr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %t1
+}
+
+define <16 x i8> @test_128_i8_x_16_28_mask_ashr_1(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_ashr_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $1, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_ashr_1:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $1, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_ashr_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $1, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_ashr_1:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $1, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = ashr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_28_mask_ashr_2(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_ashr_2:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $2, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_ashr_2:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $2, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_ashr_2:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $2, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_ashr_2:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $2, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = ashr <16 x i8> %t0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_28_mask_ashr_3(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_ashr_3:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $3, %xmm0
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_ashr_3:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $3, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_ashr_3:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $3, %xmm0
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_ashr_3:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $3, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = ashr <16 x i8> %t0, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_28_mask_ashr_4(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_ashr_4:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $4, %xmm0
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_ashr_4:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $4, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_ashr_4:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $4, %xmm0
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_ashr_4:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $4, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = ashr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
+  ret <16 x i8> %t1
+}
+
+define <16 x i8> @test_128_i8_x_16_224_mask_ashr_1(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_224_mask_ashr_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $1, %xmm0
+; X32-SSE2ONLY-NEXT:    movdqa {{.*#+}} xmm1 = [64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64]
+; X32-SSE2ONLY-NEXT:    pxor %xmm1, %xmm0
+; X32-SSE2ONLY-NEXT:    psubb %xmm1, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_224_mask_ashr_1:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $1, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vmovdqa {{.*#+}} xmm1 = [64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64]
+; X32-SSE2AVX-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_224_mask_ashr_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $1, %xmm0
+; X64-SSE2ONLY-NEXT:    movdqa {{.*#+}} xmm1 = [64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64]
+; X64-SSE2ONLY-NEXT:    pxor %xmm1, %xmm0
+; X64-SSE2ONLY-NEXT:    psubb %xmm1, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_224_mask_ashr_1:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $1, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vmovdqa {{.*#+}} xmm1 = [64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64]
+; X64-SSE2AVX-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
+  %t1 = ashr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_224_mask_ashr_4(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_224_mask_ashr_4:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $4, %xmm0
+; X32-SSE2ONLY-NEXT:    movdqa {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
+; X32-SSE2ONLY-NEXT:    pxor %xmm1, %xmm0
+; X32-SSE2ONLY-NEXT:    psubb %xmm1, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_224_mask_ashr_4:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $4, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vmovdqa {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
+; X32-SSE2AVX-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_224_mask_ashr_4:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $4, %xmm0
+; X64-SSE2ONLY-NEXT:    movdqa {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
+; X64-SSE2ONLY-NEXT:    pxor %xmm1, %xmm0
+; X64-SSE2ONLY-NEXT:    psubb %xmm1, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_224_mask_ashr_4:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $4, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vmovdqa {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
+; X64-SSE2AVX-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
+  %t1 = ashr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_224_mask_ashr_5(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_224_mask_ashr_5:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    psrlw $5, %xmm0
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    movdqa {{.*#+}} xmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4]
+; X32-SSE2ONLY-NEXT:    pxor %xmm1, %xmm0
+; X32-SSE2ONLY-NEXT:    psubb %xmm1, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_224_mask_ashr_5:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpsrlw $5, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vmovdqa {{.*#+}} xmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4]
+; X32-SSE2AVX-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_224_mask_ashr_5:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    psrlw $5, %xmm0
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    movdqa {{.*#+}} xmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4]
+; X64-SSE2ONLY-NEXT:    pxor %xmm1, %xmm0
+; X64-SSE2ONLY-NEXT:    psubb %xmm1, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_224_mask_ashr_5:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpsrlw $5, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vmovdqa {{.*#+}} xmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4]
+; X64-SSE2AVX-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
+  %t1 = ashr <16 x i8> %t0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_224_mask_ashr_6(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_224_mask_ashr_6:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    psrlw $6, %xmm0
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    movdqa {{.*#+}} xmm1 = [2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2]
+; X32-SSE2ONLY-NEXT:    pxor %xmm1, %xmm0
+; X32-SSE2ONLY-NEXT:    psubb %xmm1, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_224_mask_ashr_6:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpsrlw $6, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vmovdqa {{.*#+}} xmm1 = [2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2]
+; X32-SSE2AVX-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_224_mask_ashr_6:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    psrlw $6, %xmm0
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    movdqa {{.*#+}} xmm1 = [2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2]
+; X64-SSE2ONLY-NEXT:    pxor %xmm1, %xmm0
+; X64-SSE2ONLY-NEXT:    psubb %xmm1, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_224_mask_ashr_6:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpsrlw $6, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vmovdqa {{.*#+}} xmm1 = [2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2]
+; X64-SSE2AVX-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
+  %t1 = ashr <16 x i8> %t0, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
+  ret <16 x i8> %t1
+}
+
+; shl
+
+define <16 x i8> @test_128_i8_x_16_7_mask_shl_1(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_7_mask_shl_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    paddb %xmm0, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_7_mask_shl_1:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpaddb %xmm0, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_7_mask_shl_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    paddb %xmm0, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_7_mask_shl_1:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpaddb %xmm0, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  %t1 = shl <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_7_mask_shl_4(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_7_mask_shl_4:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psllw $4, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_7_mask_shl_4:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsllw $4, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_7_mask_shl_4:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psllw $4, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_7_mask_shl_4:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsllw $4, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  %t1 = shl <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_7_mask_shl_5(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_7_mask_shl_5:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    psllw $5, %xmm0
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_7_mask_shl_5:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpsllw $5, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_7_mask_shl_5:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    psllw $5, %xmm0
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_7_mask_shl_5:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpsllw $5, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  %t1 = shl <16 x i8> %t0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_7_mask_shl_6(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_7_mask_shl_6:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    psllw $6, %xmm0
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_7_mask_shl_6:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpsllw $6, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_7_mask_shl_6:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    psllw $6, %xmm0
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_7_mask_shl_6:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpsllw $6, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  %t1 = shl <16 x i8> %t0, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
+  ret <16 x i8> %t1
+}
+
+define <16 x i8> @test_128_i8_x_16_28_mask_shl_1(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_shl_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    paddb %xmm0, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_shl_1:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpaddb %xmm0, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_shl_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    paddb %xmm0, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_shl_1:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpaddb %xmm0, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = shl <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_28_mask_shl_2(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_shl_2:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psllw $2, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_shl_2:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsllw $2, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_shl_2:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psllw $2, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_shl_2:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsllw $2, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = shl <16 x i8> %t0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_28_mask_shl_3(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_shl_3:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psllw $3, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_shl_3:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsllw $3, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_shl_3:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psllw $3, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_shl_3:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsllw $3, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = shl <16 x i8> %t0, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <16 x i8> %t1
+}
+define <16 x i8> @test_128_i8_x_16_28_mask_shl_4(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_shl_4:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psllw $4, %xmm0
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_shl_4:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsllw $4, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_28_mask_shl_4:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psllw $4, %xmm0
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_28_mask_shl_4:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsllw $4, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
+  %t1 = shl <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
+  ret <16 x i8> %t1
+}
+
+define <16 x i8> @test_128_i8_x_16_224_mask_shl_1(<16 x i8> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i8_x_16_224_mask_shl_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    paddb %xmm0, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i8_x_16_224_mask_shl_1:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpaddb %xmm0, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i8_x_16_224_mask_shl_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    paddb %xmm0, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i8_x_16_224_mask_shl_1:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpaddb %xmm0, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
+  %t1 = shl <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %t1
+}
+
+;------------------------------------------------------------------------------;
+; 128-bit vector; 16-bit elements = 8 elements
+;------------------------------------------------------------------------------;
+
+; lshr
+
+define <8 x i16> @test_128_i16_x_8_127_mask_lshr_1(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_127_mask_lshr_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $1, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_127_mask_lshr_1:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $1, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_127_mask_lshr_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $1, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_127_mask_lshr_1:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $1, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
+  %t1 = lshr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %t1
+}
+
+define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_3(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_lshr_3:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $3, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_3:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $3, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_lshr_3:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $3, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_3:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $3, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = lshr <8 x i16> %t0, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_4(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_lshr_4:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $4, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_4:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $4, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_lshr_4:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $4, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_4:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $4, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = lshr <8 x i16> %t0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_5(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_lshr_5:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $5, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_5:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $5, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_lshr_5:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $5, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_5:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $5, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = lshr <8 x i16> %t0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_6(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_lshr_6:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $6, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_6:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $6, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_lshr_6:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $6, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_6:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $6, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = lshr <8 x i16> %t0, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
+  ret <8 x i16> %t1
+}
+
+define <8 x i16> @test_128_i16_x_8_65024_mask_lshr_1(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_65024_mask_lshr_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $1, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_65024_mask_lshr_1:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $1, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_65024_mask_lshr_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $1, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_65024_mask_lshr_1:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $1, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
+  %t1 = lshr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_65024_mask_lshr_8(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_65024_mask_lshr_8:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $8, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_65024_mask_lshr_8:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $8, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_65024_mask_lshr_8:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $8, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_65024_mask_lshr_8:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $8, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
+  %t1 = lshr <8 x i16> %t0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_65024_mask_lshr_9(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_65024_mask_lshr_9:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    psrlw $9, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_65024_mask_lshr_9:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpsrlw $9, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_65024_mask_lshr_9:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    psrlw $9, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_65024_mask_lshr_9:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpsrlw $9, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
+  %t1 = lshr <8 x i16> %t0, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_65024_mask_lshr_10(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_65024_mask_lshr_10:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    psrlw $10, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_65024_mask_lshr_10:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpsrlw $10, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_65024_mask_lshr_10:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    psrlw $10, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_65024_mask_lshr_10:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpsrlw $10, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
+  %t1 = lshr <8 x i16> %t0, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
+  ret <8 x i16> %t1
+}
+
+; ashr
+
+define <8 x i16> @test_128_i16_x_8_127_mask_ashr_1(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_127_mask_ashr_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $1, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_127_mask_ashr_1:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $1, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_127_mask_ashr_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $1, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_127_mask_ashr_1:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $1, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
+  %t1 = ashr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %t1
+}
+
+define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_3(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_ashr_3:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $3, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_3:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $3, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_ashr_3:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $3, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_3:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $3, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = ashr <8 x i16> %t0, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_4(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_ashr_4:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $4, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_4:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $4, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_ashr_4:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $4, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_4:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $4, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = ashr <8 x i16> %t0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_5(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_ashr_5:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $5, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_5:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $5, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_ashr_5:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $5, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_5:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $5, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = ashr <8 x i16> %t0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_6(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_ashr_6:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlw $6, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_6:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlw $6, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_ashr_6:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlw $6, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_6:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlw $6, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = ashr <8 x i16> %t0, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
+  ret <8 x i16> %t1
+}
+
+define <8 x i16> @test_128_i16_x_8_65024_mask_ashr_1(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_65024_mask_ashr_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psraw $1, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_65024_mask_ashr_1:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsraw $1, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_65024_mask_ashr_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psraw $1, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_65024_mask_ashr_1:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsraw $1, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
+  %t1 = ashr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_65024_mask_ashr_8(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_65024_mask_ashr_8:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psraw $8, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_65024_mask_ashr_8:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsraw $8, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_65024_mask_ashr_8:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psraw $8, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_65024_mask_ashr_8:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsraw $8, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
+  %t1 = ashr <8 x i16> %t0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_65024_mask_ashr_9(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_65024_mask_ashr_9:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    psraw $9, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_65024_mask_ashr_9:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpsraw $9, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_65024_mask_ashr_9:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    psraw $9, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_65024_mask_ashr_9:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpsraw $9, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
+  %t1 = ashr <8 x i16> %t0, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_65024_mask_ashr_10(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_65024_mask_ashr_10:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    psraw $10, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_65024_mask_ashr_10:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpsraw $10, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_65024_mask_ashr_10:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    psraw $10, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_65024_mask_ashr_10:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpsraw $10, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
+  %t1 = ashr <8 x i16> %t0, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
+  ret <8 x i16> %t1
+}
+
+; shl
+
+define <8 x i16> @test_128_i16_x_8_127_mask_shl_1(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_127_mask_shl_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    paddw %xmm0, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_127_mask_shl_1:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpaddw %xmm0, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_127_mask_shl_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    paddw %xmm0, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_127_mask_shl_1:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpaddw %xmm0, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
+  %t1 = shl <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_127_mask_shl_8(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_127_mask_shl_8:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psllw $8, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_127_mask_shl_8:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsllw $8, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_127_mask_shl_8:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psllw $8, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_127_mask_shl_8:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsllw $8, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
+  %t1 = shl <8 x i16> %t0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_127_mask_shl_9(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_127_mask_shl_9:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    psllw $9, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_127_mask_shl_9:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpsllw $9, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_127_mask_shl_9:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    psllw $9, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_127_mask_shl_9:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpsllw $9, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
+  %t1 = shl <8 x i16> %t0, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_127_mask_shl_10(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_127_mask_shl_10:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    psllw $10, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_127_mask_shl_10:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpsllw $10, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_127_mask_shl_10:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    psllw $10, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_127_mask_shl_10:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpsllw $10, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
+  %t1 = shl <8 x i16> %t0, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
+  ret <8 x i16> %t1
+}
+
+define <8 x i16> @test_128_i16_x_8_2032_mask_shl_3(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_shl_3:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psllw $3, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_shl_3:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsllw $3, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_shl_3:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psllw $3, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_shl_3:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsllw $3, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = shl <8 x i16> %t0, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_2032_mask_shl_4(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_shl_4:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psllw $4, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_shl_4:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsllw $4, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_shl_4:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psllw $4, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_shl_4:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsllw $4, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = shl <8 x i16> %t0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_2032_mask_shl_5(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_shl_5:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psllw $5, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_shl_5:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsllw $5, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_shl_5:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psllw $5, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_shl_5:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsllw $5, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = shl <8 x i16> %t0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
+  ret <8 x i16> %t1
+}
+define <8 x i16> @test_128_i16_x_8_2032_mask_shl_6(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_shl_6:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psllw $6, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_shl_6:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsllw $6, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_2032_mask_shl_6:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psllw $6, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_2032_mask_shl_6:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsllw $6, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
+  %t1 = shl <8 x i16> %t0, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
+  ret <8 x i16> %t1
+}
+
+define <8 x i16> @test_128_i16_x_8_65024_mask_shl_1(<8 x i16> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i16_x_8_65024_mask_shl_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    paddw %xmm0, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i16_x_8_65024_mask_shl_1:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpaddw %xmm0, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i16_x_8_65024_mask_shl_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    paddw %xmm0, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i16_x_8_65024_mask_shl_1:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpaddw %xmm0, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
+  %t1 = shl <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %t1
+}
+
+;------------------------------------------------------------------------------;
+; 128-bit vector; 32-bit elements = 4 elements
+;------------------------------------------------------------------------------;
+
+; lshr
+
+define <4 x i32> @test_128_i32_x_4_32767_mask_lshr_1(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_32767_mask_lshr_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrld $1, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i32_x_4_32767_mask_lshr_1:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpsrld $1, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_32767_mask_lshr_1:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [32767,32767,32767,32767]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpsrld $1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_32767_mask_lshr_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrld $1, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i32_x_4_32767_mask_lshr_1:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpsrld $1, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_32767_mask_lshr_1:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [32767,32767,32767,32767]
+; X64-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpsrld $1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
+  %t1 = lshr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %t1
+}
+
+define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_7(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_lshr_7:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrld $7, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_lshr_7:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpsrld $7, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_lshr_7:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpsrld $7, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_lshr_7:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrld $7, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_lshr_7:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpsrld $7, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_lshr_7:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X64-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpsrld $7, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = lshr <4 x i32> %t0, <i32 7, i32 7, i32 7, i32 7>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_8(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_lshr_8:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrld $8, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_lshr_8:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpsrld $8, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_lshr_8:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpsrld $8, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_lshr_8:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrld $8, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_lshr_8:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpsrld $8, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_lshr_8:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X64-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpsrld $8, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = lshr <4 x i32> %t0, <i32 8, i32 8, i32 8, i32 8>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_9(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_lshr_9:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrld $9, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_lshr_9:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpsrld $9, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_lshr_9:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpsrld $9, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_lshr_9:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrld $9, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_lshr_9:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpsrld $9, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_lshr_9:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X64-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpsrld $9, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = lshr <4 x i32> %t0, <i32 9, i32 9, i32 9, i32 9>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_10(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_lshr_10:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrld $10, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_lshr_10:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpsrld $10, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_lshr_10:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpsrld $10, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_lshr_10:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrld $10, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_lshr_10:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpsrld $10, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_lshr_10:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X64-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpsrld $10, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = lshr <4 x i32> %t0, <i32 10, i32 10, i32 10, i32 10>
+  ret <4 x i32> %t1
+}
+
+define <4 x i32> @test_128_i32_x_4_4294836224_mask_lshr_1(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_4294836224_mask_lshr_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrld $1, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i32_x_4_4294836224_mask_lshr_1:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpsrld $1, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_4294836224_mask_lshr_1:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [4294836224,4294836224,4294836224,4294836224]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpsrld $1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_4294836224_mask_lshr_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrld $1, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i32_x_4_4294836224_mask_lshr_1:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpsrld $1, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_4294836224_mask_lshr_1:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [4294836224,4294836224,4294836224,4294836224]
+; X64-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpsrld $1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
+  %t1 = lshr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_4294836224_mask_lshr_16(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_4294836224_mask_lshr_16:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrld $16, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i32_x_4_4294836224_mask_lshr_16:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpsrld $16, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_4294836224_mask_lshr_16:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [4294836224,4294836224,4294836224,4294836224]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpsrld $16, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_4294836224_mask_lshr_16:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrld $16, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i32_x_4_4294836224_mask_lshr_16:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpsrld $16, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_4294836224_mask_lshr_16:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [4294836224,4294836224,4294836224,4294836224]
+; X64-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpsrld $16, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
+  %t1 = lshr <4 x i32> %t0, <i32 16, i32 16, i32 16, i32 16>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_4294836224_mask_lshr_17(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_4294836224_mask_lshr_17:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    psrld $17, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i32_x_4_4294836224_mask_lshr_17:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpsrld $17, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_4294836224_mask_lshr_17:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    psrld $17, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i32_x_4_4294836224_mask_lshr_17:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpsrld $17, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
+  %t1 = lshr <4 x i32> %t0, <i32 17, i32 17, i32 17, i32 17>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_4294836224_mask_lshr_18(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_4294836224_mask_lshr_18:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    psrld $18, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i32_x_4_4294836224_mask_lshr_18:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpsrld $18, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_4294836224_mask_lshr_18:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    psrld $18, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i32_x_4_4294836224_mask_lshr_18:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpsrld $18, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
+  %t1 = lshr <4 x i32> %t0, <i32 18, i32 18, i32 18, i32 18>
+  ret <4 x i32> %t1
+}
+
+; ashr
+
+define <4 x i32> @test_128_i32_x_4_32767_mask_ashr_1(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_32767_mask_ashr_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrld $1, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i32_x_4_32767_mask_ashr_1:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpsrld $1, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_32767_mask_ashr_1:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [32767,32767,32767,32767]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpsrld $1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_32767_mask_ashr_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrld $1, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i32_x_4_32767_mask_ashr_1:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpsrld $1, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_32767_mask_ashr_1:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [32767,32767,32767,32767]
+; X64-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpsrld $1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
+  %t1 = ashr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %t1
+}
+
+define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_7(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_ashr_7:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrld $7, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_ashr_7:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpsrld $7, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_ashr_7:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpsrld $7, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_ashr_7:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrld $7, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_ashr_7:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpsrld $7, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_ashr_7:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X64-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpsrld $7, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = ashr <4 x i32> %t0, <i32 7, i32 7, i32 7, i32 7>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_8(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_ashr_8:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrld $8, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_ashr_8:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpsrld $8, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_ashr_8:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpsrld $8, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_ashr_8:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrld $8, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_ashr_8:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpsrld $8, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_ashr_8:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X64-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpsrld $8, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = ashr <4 x i32> %t0, <i32 8, i32 8, i32 8, i32 8>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_9(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_ashr_9:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrld $9, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_ashr_9:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpsrld $9, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_ashr_9:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpsrld $9, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_ashr_9:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrld $9, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_ashr_9:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpsrld $9, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_ashr_9:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X64-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpsrld $9, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = ashr <4 x i32> %t0, <i32 9, i32 9, i32 9, i32 9>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_10(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_ashr_10:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrld $10, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_ashr_10:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpsrld $10, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_ashr_10:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpsrld $10, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_ashr_10:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrld $10, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_ashr_10:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpsrld $10, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_ashr_10:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X64-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpsrld $10, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = ashr <4 x i32> %t0, <i32 10, i32 10, i32 10, i32 10>
+  ret <4 x i32> %t1
+}
+
+define <4 x i32> @test_128_i32_x_4_4294836224_mask_ashr_1(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_4294836224_mask_ashr_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrad $1, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i32_x_4_4294836224_mask_ashr_1:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpsrad $1, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_4294836224_mask_ashr_1:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [4294836224,4294836224,4294836224,4294836224]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpsrad $1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_4294836224_mask_ashr_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrad $1, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i32_x_4_4294836224_mask_ashr_1:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpsrad $1, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_4294836224_mask_ashr_1:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [4294836224,4294836224,4294836224,4294836224]
+; X64-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpsrad $1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
+  %t1 = ashr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_4294836224_mask_ashr_16(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_4294836224_mask_ashr_16:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrad $16, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i32_x_4_4294836224_mask_ashr_16:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpsrad $16, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_4294836224_mask_ashr_16:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [4294836224,4294836224,4294836224,4294836224]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpsrad $16, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_4294836224_mask_ashr_16:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrad $16, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i32_x_4_4294836224_mask_ashr_16:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpsrad $16, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_4294836224_mask_ashr_16:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [4294836224,4294836224,4294836224,4294836224]
+; X64-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpsrad $16, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
+  %t1 = ashr <4 x i32> %t0, <i32 16, i32 16, i32 16, i32 16>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_4294836224_mask_ashr_17(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_4294836224_mask_ashr_17:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    psrad $17, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i32_x_4_4294836224_mask_ashr_17:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpsrad $17, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_4294836224_mask_ashr_17:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    psrad $17, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i32_x_4_4294836224_mask_ashr_17:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpsrad $17, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
+  %t1 = ashr <4 x i32> %t0, <i32 17, i32 17, i32 17, i32 17>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_4294836224_mask_ashr_18(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_4294836224_mask_ashr_18:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    psrad $18, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i32_x_4_4294836224_mask_ashr_18:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpsrad $18, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_4294836224_mask_ashr_18:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    psrad $18, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i32_x_4_4294836224_mask_ashr_18:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpsrad $18, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
+  %t1 = ashr <4 x i32> %t0, <i32 18, i32 18, i32 18, i32 18>
+  ret <4 x i32> %t1
+}
+
+; shl
+
+define <4 x i32> @test_128_i32_x_4_32767_mask_shl_1(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_32767_mask_shl_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    paddd %xmm0, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i32_x_4_32767_mask_shl_1:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpaddd %xmm0, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_32767_mask_shl_1:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [32767,32767,32767,32767]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpaddd %xmm0, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_32767_mask_shl_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    paddd %xmm0, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i32_x_4_32767_mask_shl_1:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpaddd %xmm0, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_32767_mask_shl_1:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [32767,32767,32767,32767]
+; X64-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpaddd %xmm0, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
+  %t1 = shl <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_32767_mask_shl_16(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_32767_mask_shl_16:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    pslld $16, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i32_x_4_32767_mask_shl_16:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpslld $16, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_32767_mask_shl_16:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [32767,32767,32767,32767]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpslld $16, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_32767_mask_shl_16:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    pslld $16, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i32_x_4_32767_mask_shl_16:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpslld $16, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_32767_mask_shl_16:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [32767,32767,32767,32767]
+; X64-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpslld $16, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
+  %t1 = shl <4 x i32> %t0, <i32 16, i32 16, i32 16, i32 16>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_32767_mask_shl_17(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_32767_mask_shl_17:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pslld $17, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i32_x_4_32767_mask_shl_17:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpslld $17, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_32767_mask_shl_17:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pslld $17, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i32_x_4_32767_mask_shl_17:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpslld $17, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
+  %t1 = shl <4 x i32> %t0, <i32 17, i32 17, i32 17, i32 17>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_32767_mask_shl_18(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_32767_mask_shl_18:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pslld $18, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i32_x_4_32767_mask_shl_18:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpslld $18, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_32767_mask_shl_18:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pslld $18, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i32_x_4_32767_mask_shl_18:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpslld $18, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
+  %t1 = shl <4 x i32> %t0, <i32 18, i32 18, i32 18, i32 18>
+  ret <4 x i32> %t1
+}
+
+define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_7(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_shl_7:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    pslld $7, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_shl_7:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpslld $7, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_shl_7:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpslld $7, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_shl_7:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    pslld $7, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_shl_7:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpslld $7, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_shl_7:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X64-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpslld $7, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = shl <4 x i32> %t0, <i32 7, i32 7, i32 7, i32 7>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_8(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_shl_8:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    pslld $8, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_shl_8:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpslld $8, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_shl_8:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpslld $8, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_shl_8:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    pslld $8, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_shl_8:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpslld $8, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_shl_8:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X64-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpslld $8, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = shl <4 x i32> %t0, <i32 8, i32 8, i32 8, i32 8>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_9(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_shl_9:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    pslld $9, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_shl_9:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpslld $9, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_shl_9:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpslld $9, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_shl_9:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    pslld $9, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_shl_9:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpslld $9, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_shl_9:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X64-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpslld $9, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = shl <4 x i32> %t0, <i32 9, i32 9, i32 9, i32 9>
+  ret <4 x i32> %t1
+}
+define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_10(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_shl_10:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    pslld $10, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_shl_10:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpslld $10, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_shl_10:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpslld $10, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_8388352_mask_shl_10:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    pslld $10, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i32_x_4_8388352_mask_shl_10:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpslld $10, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_8388352_mask_shl_10:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
+; X64-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpslld $10, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
+  %t1 = shl <4 x i32> %t0, <i32 10, i32 10, i32 10, i32 10>
+  ret <4 x i32> %t1
+}
+
+define <4 x i32> @test_128_i32_x_4_4294836224_mask_shl_1(<4 x i32> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i32_x_4_4294836224_mask_shl_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    paddd %xmm0, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i32_x_4_4294836224_mask_shl_1:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpaddd %xmm0, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_4294836224_mask_shl_1:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [4294836224,4294836224,4294836224,4294836224]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpaddd %xmm0, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i32_x_4_4294836224_mask_shl_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    paddd %xmm0, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i32_x_4_4294836224_mask_shl_1:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpaddd %xmm0, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i32_x_4_4294836224_mask_shl_1:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [4294836224,4294836224,4294836224,4294836224]
+; X64-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpaddd %xmm0, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
+  %t1 = shl <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %t1
+}
+
+;------------------------------------------------------------------------------;
+; 128-bit vector; 64-bit elements = 2 elements
+;------------------------------------------------------------------------------;
+
+; lshr
+
+define <2 x i64> @test_128_i64_x_2_2147483647_mask_lshr_1(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_2147483647_mask_lshr_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlq $1, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i64_x_2_2147483647_mask_lshr_1:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlq $1, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_2147483647_mask_lshr_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlq $1, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_2147483647_mask_lshr_1:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlq $1, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
+  %t1 = lshr <2 x i64> %t0, <i64 1, i64 1>
+  ret <2 x i64> %t1
+}
+
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_15(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_15:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlq $15, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_15:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlq $15, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_15:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlq $15, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_15:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlq $15, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = lshr <2 x i64> %t0, <i64 15, i64 15>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_16(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_16:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlq $16, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_16:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlq $16, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_16:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlq $16, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_16:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlq $16, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = lshr <2 x i64> %t0, <i64 16, i64 16>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_17(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_17:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlq $17, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_17:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlq $17, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_17:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlq $17, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_17:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlq $17, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = lshr <2 x i64> %t0, <i64 17, i64 17>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_18(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_18:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlq $18, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_18:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlq $18, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_18:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlq $18, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_18:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlq $18, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = lshr <2 x i64> %t0, <i64 18, i64 18>
+  ret <2 x i64> %t1
+}
+
+define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_lshr_1(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlq $1, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_1:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlq $1, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlq $1, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_1:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlq $1, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
+  %t1 = lshr <2 x i64> %t0, <i64 1, i64 1>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_lshr_32(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_32:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlq $32, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_32:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpsrlq $32, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_32:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [4294967294,4294967294,4294967294,4294967294]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpsrlq $32, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_32:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlq $32, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_32:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlq $32, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
+  %t1 = lshr <2 x i64> %t0, <i64 32, i64 32>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_lshr_33(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_33:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    psrlq $33, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_33:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpsrlq $33, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_33:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    psrlq $33, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_33:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpsrlq $33, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
+  %t1 = lshr <2 x i64> %t0, <i64 33, i64 33>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_lshr_34(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_34:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    psrlq $34, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_34:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpsrlq $34, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_34:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    psrlq $34, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_34:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpsrlq $34, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
+  %t1 = lshr <2 x i64> %t0, <i64 34, i64 34>
+  ret <2 x i64> %t1
+}
+
+; ashr
+
+define <2 x i64> @test_128_i64_x_2_2147483647_mask_ashr_1(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_2147483647_mask_ashr_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlq $1, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i64_x_2_2147483647_mask_ashr_1:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlq $1, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_2147483647_mask_ashr_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlq $1, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_2147483647_mask_ashr_1:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlq $1, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
+  %t1 = ashr <2 x i64> %t0, <i64 1, i64 1>
+  ret <2 x i64> %t1
+}
+
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_15(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_15:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlq $15, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_15:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlq $15, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_15:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlq $15, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_15:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlq $15, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = ashr <2 x i64> %t0, <i64 15, i64 15>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_16(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_16:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlq $16, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_16:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlq $16, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_16:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlq $16, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_16:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlq $16, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = ashr <2 x i64> %t0, <i64 16, i64 16>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_17(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_17:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlq $17, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_17:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlq $17, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_17:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlq $17, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_17:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlq $17, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = ashr <2 x i64> %t0, <i64 17, i64 17>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_18(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_18:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrlq $18, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_18:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsrlq $18, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_18:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrlq $18, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_18:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsrlq $18, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = ashr <2 x i64> %t0, <i64 18, i64 18>
+  ret <2 x i64> %t1
+}
+
+define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_1(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psrad $1, %xmm0
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_1:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpsrad $1, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; X32-SSE2AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_1:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [4294967294,4294967294,4294967294,4294967294]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpsrad $1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; X32-SSE2AVX1AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psrad $1, %xmm0
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_1:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpsrad $1, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; X64-SSE2AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_1:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpsrad $1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; X64-SSE2AVX1AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
+  %t1 = ashr <2 x i64> %t0, <i64 1, i64 1>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_32(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_32:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
+; X32-SSE2ONLY-NEXT:    psrad $31, %xmm0
+; X32-SSE2ONLY-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
+; X32-SSE2ONLY-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; X32-SSE2ONLY-NEXT:    movdqa %xmm1, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_32:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpsrad $31, %xmm0, %xmm1
+; X32-SSE2AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; X32-SSE2AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_32:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpsrad $31, %xmm0, %xmm1
+; X32-SSE2AVX1AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; X32-SSE2AVX1AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_32:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
+; X64-SSE2ONLY-NEXT:    psrad $31, %xmm0
+; X64-SSE2ONLY-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
+; X64-SSE2ONLY-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; X64-SSE2ONLY-NEXT:    movdqa %xmm1, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_32:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpsrad $31, %xmm0, %xmm1
+; X64-SSE2AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; X64-SSE2AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_32:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpsrad $31, %xmm0, %xmm1
+; X64-SSE2AVX1AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; X64-SSE2AVX1AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
+  %t1 = ashr <2 x i64> %t0, <i64 32, i64 32>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_33(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_33:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    movdqa %xmm0, %xmm1
+; X32-SSE2ONLY-NEXT:    psrad $31, %xmm1
+; X32-SSE2ONLY-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
+; X32-SSE2ONLY-NEXT:    psrad $1, %xmm0
+; X32-SSE2ONLY-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
+; X32-SSE2ONLY-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_33:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpsrad $31, %xmm0, %xmm1
+; X32-SSE2AVX1-NEXT:    vpsrad $1, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; X32-SSE2AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_33:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpsrad $31, %xmm0, %xmm1
+; X32-SSE2AVX1AVX2-NEXT:    vpsrad $1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; X32-SSE2AVX1AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_33:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    movdqa %xmm0, %xmm1
+; X64-SSE2ONLY-NEXT:    psrad $31, %xmm1
+; X64-SSE2ONLY-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
+; X64-SSE2ONLY-NEXT:    psrad $1, %xmm0
+; X64-SSE2ONLY-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
+; X64-SSE2ONLY-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_33:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpsrad $31, %xmm0, %xmm1
+; X64-SSE2AVX1-NEXT:    vpsrad $1, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; X64-SSE2AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_33:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpsrad $31, %xmm0, %xmm1
+; X64-SSE2AVX1AVX2-NEXT:    vpsrad $1, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; X64-SSE2AVX1AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
+  %t1 = ashr <2 x i64> %t0, <i64 33, i64 33>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_34(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_34:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    movdqa %xmm0, %xmm1
+; X32-SSE2ONLY-NEXT:    psrad $31, %xmm1
+; X32-SSE2ONLY-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
+; X32-SSE2ONLY-NEXT:    psrad $2, %xmm0
+; X32-SSE2ONLY-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
+; X32-SSE2ONLY-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_34:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpsrad $31, %xmm0, %xmm1
+; X32-SSE2AVX1-NEXT:    vpsrad $2, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; X32-SSE2AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_34:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpsrad $31, %xmm0, %xmm1
+; X32-SSE2AVX1AVX2-NEXT:    vpsrad $2, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; X32-SSE2AVX1AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_34:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    movdqa %xmm0, %xmm1
+; X64-SSE2ONLY-NEXT:    psrad $31, %xmm1
+; X64-SSE2ONLY-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
+; X64-SSE2ONLY-NEXT:    psrad $2, %xmm0
+; X64-SSE2ONLY-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
+; X64-SSE2ONLY-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX1-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_34:
+; X64-SSE2AVX1:       # %bb.0:
+; X64-SSE2AVX1-NEXT:    vpsrad $31, %xmm0, %xmm1
+; X64-SSE2AVX1-NEXT:    vpsrad $2, %xmm0, %xmm0
+; X64-SSE2AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; X64-SSE2AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
+; X64-SSE2AVX1-NEXT:    retq
+;
+; X64-SSE2AVX1AVX2-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_34:
+; X64-SSE2AVX1AVX2:       # %bb.0:
+; X64-SSE2AVX1AVX2-NEXT:    vpsrad $31, %xmm0, %xmm1
+; X64-SSE2AVX1AVX2-NEXT:    vpsrad $2, %xmm0, %xmm0
+; X64-SSE2AVX1AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; X64-SSE2AVX1AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
+; X64-SSE2AVX1AVX2-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
+  %t1 = ashr <2 x i64> %t0, <i64 34, i64 34>
+  ret <2 x i64> %t1
+}
+
+; shl
+
+define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_1(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_2147483647_mask_shl_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    paddq %xmm0, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i64_x_2_2147483647_mask_shl_1:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpaddq %xmm0, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_2147483647_mask_shl_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    paddq %xmm0, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_2147483647_mask_shl_1:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpaddq %xmm0, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
+  %t1 = shl <2 x i64> %t0, <i64 1, i64 1>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_32(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_2147483647_mask_shl_32:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psllq $32, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX1-LABEL: test_128_i64_x_2_2147483647_mask_shl_32:
+; X32-SSE2AVX1:       # %bb.0:
+; X32-SSE2AVX1-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    vpsllq $32, %xmm0, %xmm0
+; X32-SSE2AVX1-NEXT:    retl
+;
+; X32-SSE2AVX1AVX2-LABEL: test_128_i64_x_2_2147483647_mask_shl_32:
+; X32-SSE2AVX1AVX2:       # %bb.0:
+; X32-SSE2AVX1AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [2147483647,2147483647,2147483647,2147483647]
+; X32-SSE2AVX1AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    vpsllq $32, %xmm0, %xmm0
+; X32-SSE2AVX1AVX2-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_2147483647_mask_shl_32:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psllq $32, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_2147483647_mask_shl_32:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsllq $32, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
+  %t1 = shl <2 x i64> %t0, <i64 32, i64 32>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_33(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_2147483647_mask_shl_33:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    psllq $33, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i64_x_2_2147483647_mask_shl_33:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpsllq $33, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_2147483647_mask_shl_33:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    psllq $33, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_2147483647_mask_shl_33:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpsllq $33, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
+  %t1 = shl <2 x i64> %t0, <i64 33, i64 33>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_34(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_2147483647_mask_shl_34:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    psllq $34, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i64_x_2_2147483647_mask_shl_34:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpsllq $34, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_2147483647_mask_shl_34:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    psllq $34, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_2147483647_mask_shl_34:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpsllq $34, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
+  %t1 = shl <2 x i64> %t0, <i64 34, i64 34>
+  ret <2 x i64> %t1
+}
+
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_15(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_shl_15:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psllq $15, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_15:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsllq $15, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_shl_15:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psllq $15, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_15:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsllq $15, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = shl <2 x i64> %t0, <i64 15, i64 15>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_16(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_shl_16:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psllq $16, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_16:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsllq $16, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_shl_16:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psllq $16, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_16:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsllq $16, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = shl <2 x i64> %t0, <i64 16, i64 16>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_17(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_shl_17:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psllq $17, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_17:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsllq $17, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_shl_17:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psllq $17, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_17:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsllq $17, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = shl <2 x i64> %t0, <i64 17, i64 17>
+  ret <2 x i64> %t1
+}
+define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_18(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_shl_18:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    psllq $18, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_18:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpsllq $18, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_140737488289792_mask_shl_18:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    psllq $18, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_18:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpsllq $18, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
+  %t1 = shl <2 x i64> %t0, <i64 18, i64 18>
+  ret <2 x i64> %t1
+}
+
+define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_shl_1(<2 x i64> %a0) {
+; X32-SSE2ONLY-LABEL: test_128_i64_x_2_18446744065119617024_mask_shl_1:
+; X32-SSE2ONLY:       # %bb.0:
+; X32-SSE2ONLY-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE2ONLY-NEXT:    paddq %xmm0, %xmm0
+; X32-SSE2ONLY-NEXT:    retl
+;
+; X32-SSE2AVX-LABEL: test_128_i64_x_2_18446744065119617024_mask_shl_1:
+; X32-SSE2AVX:       # %bb.0:
+; X32-SSE2AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    vpaddq %xmm0, %xmm0, %xmm0
+; X32-SSE2AVX-NEXT:    retl
+;
+; X64-SSE2ONLY-LABEL: test_128_i64_x_2_18446744065119617024_mask_shl_1:
+; X64-SSE2ONLY:       # %bb.0:
+; X64-SSE2ONLY-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE2ONLY-NEXT:    paddq %xmm0, %xmm0
+; X64-SSE2ONLY-NEXT:    retq
+;
+; X64-SSE2AVX-LABEL: test_128_i64_x_2_18446744065119617024_mask_shl_1:
+; X64-SSE2AVX:       # %bb.0:
+; X64-SSE2AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    vpaddq %xmm0, %xmm0, %xmm0
+; X64-SSE2AVX-NEXT:    retq
+  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
+  %t1 = shl <2 x i64> %t0, <i64 1, i64 1>
+  ret <2 x i64> %t1
+}