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[AArch64][test] Add explicit dso_local to definitions in ELF static relocation model tests 

TargetMachine::shouldAssumeDSOLocal currently implies dso_local for such definitions.

Adding explicit dso_local makes these tests align with the clang -fno-pic behavior
and allow the removal of the TargetMachine::shouldAssumeDSOLocal special case.

Split tiny_model.ll to tiny-model-{static,pic}.ll
This commit is contained in:
Fangrui Song 2020-12-30 15:03:06 -08:00
parent e0f70ee01c
commit 7b529d0411
44 changed files with 1075 additions and 827 deletions
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4
llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir
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@ -4,9 +4,9 @@
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-none-linux-gnu"
@addr = global i8* null
@addr = dso_local global i8* null
define void @test_blockaddress() {
define dso_local void @test_blockaddress() {
store i8* blockaddress(@test_blockaddress, %block), i8** @addr
indirectbr i8* blockaddress(@test_blockaddress, %block), [label %block]

4
llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
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@ -7,9 +7,9 @@
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-none-linux-gnu"
@addr = global i8* null
@addr = dso_local global i8* null
define void @test_blockaddress() {
define dso_local void @test_blockaddress() {
store i8* blockaddress(@test_blockaddress, %block), i8** @addr
indirectbr i8* blockaddress(@test_blockaddress, %block), [label %block]

6
llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir
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@ -3,10 +3,10 @@
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
@foo1 = common global [1073741824 x i32] zeroinitializer, align 4
@foo2 = common global [1073741824 x i32] zeroinitializer, align 4
@foo1 = common dso_local global [1073741824 x i32] zeroinitializer, align 4
@foo2 = common dso_local global [1073741824 x i32] zeroinitializer, align 4
define i32 @gv_large() {
define dso_local i32 @gv_large() {
entry:
%retval = alloca i32, align 4
store i32 0, i32* %retval, align 4

6
llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir
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@ -3,10 +3,10 @@
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
@foo1 = common global [1073741824 x i32] zeroinitializer, align 4
@foo2 = common global [1073741824 x i32] zeroinitializer, align 4
@foo1 = common dso_local global [1073741824 x i32] zeroinitializer, align 4
@foo2 = common dso_local global [1073741824 x i32] zeroinitializer, align 4
define i32 @gv_tiny() {
define dso_local i32 @gv_tiny() {
entry:
%retval = alloca i32, align 4
store i32 0, i32* %retval, align 4

18
llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
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@ -3,25 +3,25 @@
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
define void @frame_index() {
define dso_local void @frame_index() {
%ptr0 = alloca i64
ret void
}
define i8* @ptr_mask(i8* %in) { ret i8* undef }
define dso_local i8* @ptr_mask(i8* %in) { ret i8* undef }
@var_local = global i8 0
define i8* @global_local() { ret i8* undef }
@var_local = dso_local global i8 0
define dso_local i8* @global_local() { ret i8* undef }
@var_got = external dso_local global i8
define i8* @global_got() { ret i8* undef }
define dso_local i8* @global_got() { ret i8* undef }
define void @icmp() { ret void }
define void @fcmp() { ret void }
define dso_local void @icmp() { ret void }
define dso_local void @fcmp() { ret void }
define void @phi() { ret void }
define dso_local void @phi() { ret void }
define void @select() { ret void }
define dso_local void @select() { ret void }
...
---

4
llvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir
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@ -4,9 +4,9 @@
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64"
@x = global i32 -32768, align 4
@x = dso_local global i32 -32768, align 4
define i32 @check_sext_not_lost(i32* %ptr) {
define dso_local i32 @check_sext_not_lost(i32* %ptr) {
entry:
%ptr.addr = alloca i32*, align 8
store i32* %ptr, i32** %ptr.addr, align 8

90
llvm/test/CodeGen/AArch64/aarch64-be-bv.ll
View File

@ -1,9 +1,9 @@
; RUN: llc -mtriple=aarch64_be--linux-gnu < %s | FileCheck %s
@vec_v8i16 = global <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
@vec_v8i16 = dso_local global <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
; CHECK-LABEL: movi_modimm_t1:
define void @movi_modimm_t1() nounwind {
define dso_local void @movi_modimm_t1() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1
; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
@ -15,7 +15,7 @@ define void @movi_modimm_t1() nounwind {
}
; CHECK-LABEL: movi_modimm_t2:
define void @movi_modimm_t2() nounwind {
define dso_local void @movi_modimm_t2() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #8
; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
@ -27,7 +27,7 @@ define void @movi_modimm_t2() nounwind {
}
; CHECK-LABEL: movi_modimm_t3:
define void @movi_modimm_t3() nounwind {
define dso_local void @movi_modimm_t3() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #16
; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
@ -39,7 +39,7 @@ define void @movi_modimm_t3() nounwind {
}
; CHECK-LABEL: movi_modimm_t4:
define void @movi_modimm_t4() nounwind {
define dso_local void @movi_modimm_t4() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #24
; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
@ -51,7 +51,7 @@ define void @movi_modimm_t4() nounwind {
}
; CHECK-LABEL: movi_modimm_t5:
define void @movi_modimm_t5() nounwind {
define dso_local void @movi_modimm_t5() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: movi v[[REG2:[0-9]+]].8h, #1
; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
@ -63,7 +63,7 @@ define void @movi_modimm_t5() nounwind {
}
; CHECK-LABEL: movi_modimm_t6:
define void @movi_modimm_t6() nounwind {
define dso_local void @movi_modimm_t6() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: movi v[[REG2:[0-9]+]].8h, #1, lsl #8
; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
@ -75,7 +75,7 @@ define void @movi_modimm_t6() nounwind {
}
; CHECK-LABEL: movi_modimm_t7:
define void @movi_modimm_t7() nounwind {
define dso_local void @movi_modimm_t7() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, msl #8
; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
@ -87,7 +87,7 @@ define void @movi_modimm_t7() nounwind {
}
; CHECK-LABEL: movi_modimm_t8:
define void @movi_modimm_t8() nounwind {
define dso_local void @movi_modimm_t8() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, msl #16
; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
@ -99,7 +99,7 @@ define void @movi_modimm_t8() nounwind {
}
; CHECK-LABEL: movi_modimm_t9:
define void @movi_modimm_t9() nounwind {
define dso_local void @movi_modimm_t9() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: movi v[[REG2:[0-9]+]].16b, #1
; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
@ -111,7 +111,7 @@ define void @movi_modimm_t9() nounwind {
}
; CHECK-LABEL: movi_modimm_t10:
define void @movi_modimm_t10() nounwind {
define dso_local void @movi_modimm_t10() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: movi v[[REG2:[0-9]+]].2d, #0x00ffff0000ffff
; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
@ -123,7 +123,7 @@ define void @movi_modimm_t10() nounwind {
}
; CHECK-LABEL: fmov_modimm_t11:
define void @fmov_modimm_t11() nounwind {
define dso_local void @fmov_modimm_t11() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: fmov v[[REG2:[0-9]+]].4s, #3.00000000
; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
@ -135,7 +135,7 @@ define void @fmov_modimm_t11() nounwind {
}
; CHECK-LABEL: fmov_modimm_t12:
define void @fmov_modimm_t12() nounwind {
define dso_local void @fmov_modimm_t12() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: fmov v[[REG2:[0-9]+]].2d, #0.17968750
; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
@ -147,7 +147,7 @@ define void @fmov_modimm_t12() nounwind {
}
; CHECK-LABEL: mvni_modimm_t1:
define void @mvni_modimm_t1() nounwind {
define dso_local void @mvni_modimm_t1() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1
; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
@ -159,7 +159,7 @@ define void @mvni_modimm_t1() nounwind {
}
; CHECK-LABEL: mvni_modimm_t2:
define void @mvni_modimm_t2() nounwind {
define dso_local void @mvni_modimm_t2() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1, lsl #8
; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
@ -171,7 +171,7 @@ define void @mvni_modimm_t2() nounwind {
}
; CHECK-LABEL: mvni_modimm_t3:
define void @mvni_modimm_t3() nounwind {
define dso_local void @mvni_modimm_t3() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1, lsl #16
; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
@ -183,7 +183,7 @@ define void @mvni_modimm_t3() nounwind {
}
; CHECK-LABEL: mvni_modimm_t4:
define void @mvni_modimm_t4() nounwind {
define dso_local void @mvni_modimm_t4() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1, lsl #24
; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
@ -195,7 +195,7 @@ define void @mvni_modimm_t4() nounwind {
}
; CHECK-LABEL: mvni_modimm_t5:
define void @mvni_modimm_t5() nounwind {
define dso_local void @mvni_modimm_t5() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: mvni v[[REG2:[0-9]+]].8h, #1
; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
@ -207,7 +207,7 @@ define void @mvni_modimm_t5() nounwind {
}
; CHECK-LABEL: mvni_modimm_t6:
define void @mvni_modimm_t6() nounwind {
define dso_local void @mvni_modimm_t6() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: mvni v[[REG2:[0-9]+]].8h, #1, lsl #8
; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
@ -219,7 +219,7 @@ define void @mvni_modimm_t6() nounwind {
}
; CHECK-LABEL: mvni_modimm_t7:
define void @mvni_modimm_t7() nounwind {
define dso_local void @mvni_modimm_t7() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1, msl #8
; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
@ -231,7 +231,7 @@ define void @mvni_modimm_t7() nounwind {
}
; CHECK-LABEL: mvni_modimm_t8:
define void @mvni_modimm_t8() nounwind {
define dso_local void @mvni_modimm_t8() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1, msl #16
; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
@ -243,7 +243,7 @@ define void @mvni_modimm_t8() nounwind {
}
; CHECK-LABEL: bic_modimm_t1:
define void @bic_modimm_t1() nounwind {
define dso_local void @bic_modimm_t1() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #1
; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
@ -254,7 +254,7 @@ define void @bic_modimm_t1() nounwind {
}
; CHECK-LABEL: bic_modimm_t2:
define void @bic_modimm_t2() nounwind {
define dso_local void @bic_modimm_t2() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #1, lsl #8
; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
@ -265,7 +265,7 @@ define void @bic_modimm_t2() nounwind {
}
; CHECK-LABEL: bic_modimm_t3:
define void @bic_modimm_t3() nounwind {
define dso_local void @bic_modimm_t3() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #1, lsl #16
; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
@ -276,7 +276,7 @@ define void @bic_modimm_t3() nounwind {
}
; CHECK-LABEL: bic_modimm_t4:
define void @bic_modimm_t4() nounwind {
define dso_local void @bic_modimm_t4() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #1, lsl #24
; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
@ -287,7 +287,7 @@ define void @bic_modimm_t4() nounwind {
}
; CHECK-LABEL: bic_modimm_t5:
define void @bic_modimm_t5() nounwind {
define dso_local void @bic_modimm_t5() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: bic v[[REG2:[0-9]+]].8h, #1
; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
@ -298,7 +298,7 @@ define void @bic_modimm_t5() nounwind {
}
; CHECK-LABEL: bic_modimm_t6:
define void @bic_modimm_t6() nounwind {
define dso_local void @bic_modimm_t6() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: bic v[[REG2:[0-9]+]].8h, #1, lsl #8
; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
@ -309,7 +309,7 @@ define void @bic_modimm_t6() nounwind {
}
; CHECK-LABEL: orr_modimm_t1:
define void @orr_modimm_t1() nounwind {
define dso_local void @orr_modimm_t1() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #1
; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
@ -320,7 +320,7 @@ define void @orr_modimm_t1() nounwind {
}
; CHECK-LABEL: orr_modimm_t2:
define void @orr_modimm_t2() nounwind {
define dso_local void @orr_modimm_t2() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #1, lsl #8
; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
@ -331,7 +331,7 @@ define void @orr_modimm_t2() nounwind {
}
; CHECK-LABEL: orr_modimm_t3:
define void @orr_modimm_t3() nounwind {
define dso_local void @orr_modimm_t3() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #1, lsl #16
; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
@ -342,7 +342,7 @@ define void @orr_modimm_t3() nounwind {
}
; CHECK-LABEL: orr_modimm_t4:
define void @orr_modimm_t4() nounwind {
define dso_local void @orr_modimm_t4() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #1, lsl #24
; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
@ -353,7 +353,7 @@ define void @orr_modimm_t4() nounwind {
}
; CHECK-LABEL: orr_modimm_t5:
define void @orr_modimm_t5() nounwind {
define dso_local void @orr_modimm_t5() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: orr v[[REG2:[0-9]+]].8h, #1
; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
@ -364,7 +364,7 @@ define void @orr_modimm_t5() nounwind {
}
; CHECK-LABEL: orr_modimm_t6:
define void @orr_modimm_t6() nounwind {
define dso_local void @orr_modimm_t6() nounwind {
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
; CHECK-NEXT: orr v[[REG2:[0-9]+]].8h, #1, lsl #8
; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
@ -384,7 +384,7 @@ declare i32 @f_v4i32(<4 x i32> %arg)
declare i64 @f_v2i64(<2 x i64> %arg)
; CHECK-LABEL: modimm_t1_call:
define void @modimm_t1_call() {
define dso_local void @modimm_t1_call() {
; CHECK: movi v[[REG1:[0-9]+]].2s, #8
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
; CHECK-NEXT: bl f_v8i8
@ -424,7 +424,7 @@ define void @modimm_t1_call() {
}
; CHECK-LABEL: modimm_t2_call:
define void @modimm_t2_call() {
define dso_local void @modimm_t2_call() {
; CHECK: movi v[[REG1:[0-9]+]].2s, #8, lsl #8
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
; CHECK-NEXT: bl f_v8i8
@ -464,7 +464,7 @@ define void @modimm_t2_call() {
}
; CHECK-LABEL: modimm_t3_call:
define void @modimm_t3_call() {
define dso_local void @modimm_t3_call() {
; CHECK: movi v[[REG1:[0-9]+]].2s, #8, lsl #16
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
; CHECK-NEXT: bl f_v8i8
@ -504,7 +504,7 @@ define void @modimm_t3_call() {
}
; CHECK-LABEL: modimm_t4_call:
define void @modimm_t4_call() {
define dso_local void @modimm_t4_call() {
; CHECK: movi v[[REG1:[0-9]+]].2s, #8, lsl #24
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
; CHECK-NEXT: bl f_v8i8
@ -544,7 +544,7 @@ define void @modimm_t4_call() {
}
; CHECK-LABEL: modimm_t5_call:
define void @modimm_t5_call() {
define dso_local void @modimm_t5_call() {
; CHECK: movi v[[REG1:[0-9]+]].4h, #8
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
; CHECK-NEXT: bl f_v8i8
@ -584,7 +584,7 @@ define void @modimm_t5_call() {
}
; CHECK-LABEL: modimm_t6_call:
define void @modimm_t6_call() {
define dso_local void @modimm_t6_call() {
; CHECK: movi v[[REG1:[0-9]+]].4h, #8, lsl #8
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
; CHECK-NEXT: bl f_v8i8
@ -624,7 +624,7 @@ define void @modimm_t6_call() {
}
; CHECK-LABEL: modimm_t7_call:
define void @modimm_t7_call() {
define dso_local void @modimm_t7_call() {
; CHECK: movi v[[REG1:[0-9]+]].2s, #8, msl #8
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
; CHECK-NEXT: bl f_v8i8
@ -664,7 +664,7 @@ define void @modimm_t7_call() {
}
; CHECK-LABEL: modimm_t8_call:
define void @modimm_t8_call() {
define dso_local void @modimm_t8_call() {
; CHECK: movi v[[REG1:[0-9]+]].2s, #8, msl #16
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
; CHECK-NEXT: bl f_v8i8
@ -704,7 +704,7 @@ define void @modimm_t8_call() {
}
; CHECK-LABEL: modimm_t9_call:
define void @modimm_t9_call() {
define dso_local void @modimm_t9_call() {
; CHECK: movi v[[REG1:[0-9]+]].8b, #8
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
; CHECK-NEXT: bl f_v8i8
@ -737,7 +737,7 @@ define void @modimm_t9_call() {
}
; CHECK-LABEL: modimm_t10_call:
define void @modimm_t10_call() {
define dso_local void @modimm_t10_call() {
; CHECK: movi d[[REG1:[0-9]+]], #0x0000ff000000ff
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
; CHECK-NEXT: bl f_v8i8
@ -770,7 +770,7 @@ define void @modimm_t10_call() {
}
; CHECK-LABEL: modimm_t11_call:
define void @modimm_t11_call() {
define dso_local void @modimm_t11_call() {
; CHECK: fmov v[[REG1:[0-9]+]].2s, #4.00000000
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
; CHECK-NEXT: bl f_v8i8
@ -810,7 +810,7 @@ define void @modimm_t11_call() {
}
; CHECK-LABEL: modimm_t12_call:
define void @modimm_t12_call() {
define dso_local void @modimm_t12_call() {
; CHECK: fmov v[[REG1:[0-9]+]].2d, #0.18750000
; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8

34
llvm/test/CodeGen/AArch64/addsub_ext.ll
View File

@ -5,12 +5,12 @@
; G_SEXT is lowered to anything else, it won't fold in a stx*.
; FIXME: GISel doesn't currently handle folding the addressing mode into a cmp.
@var8 = global i8 0
@var16 = global i16 0
@var32 = global i32 0
@var64 = global i64 0
@var8 = dso_local global i8 0
@var16 = dso_local global i16 0
@var32 = dso_local global i32 0
@var64 = dso_local global i64 0
define void @addsub_i8rhs() minsize {
define dso_local void @addsub_i8rhs() minsize {
; CHECK-LABEL: addsub_i8rhs:
; GISEL-LABEL: addsub_i8rhs:
%val8_tmp = load i8, i8* @var8
@ -89,7 +89,7 @@ end:
ret void
}
define void @sub_i8rhs() minsize {
define dso_local void @sub_i8rhs() minsize {
; CHECK-LABEL: sub_i8rhs:
%val8_tmp = load i8, i8* @var8
%lhs32 = load i32, i32* @var32
@ -150,7 +150,7 @@ define void @sub_i8rhs() minsize {
ret void
}
define void @addsub_i16rhs() minsize {
define dso_local void @addsub_i16rhs() minsize {
; CHECK-LABEL: addsub_i16rhs:
; GISEL-LABEL: addsub_i16rhs:
%val16_tmp = load i16, i16* @var16
@ -229,7 +229,7 @@ end:
ret void
}
define void @sub_i16rhs() minsize {
define dso_local void @sub_i16rhs() minsize {
; CHECK-LABEL: sub_i16rhs:
; GISEL-LABEL: sub_i16rhs:
%val16_tmp = load i16, i16* @var16
@ -294,7 +294,7 @@ define void @sub_i16rhs() minsize {
; N.b. we could probably check more here ("add w2, w3, w1, uxtw" for
; example), but the remaining instructions are probably not idiomatic
; in the face of "add/sub (shifted register)" so I don't intend to.
define void @addsub_i32rhs(i32 %in32) minsize {
define dso_local void @addsub_i32rhs(i32 %in32) minsize {
; CHECK-LABEL: addsub_i32rhs:
; GISEL-LABEL: addsub_i32rhs:
%val32_tmp = load i32, i32* @var32
@ -330,7 +330,7 @@ define void @addsub_i32rhs(i32 %in32) minsize {
ret void
}
define void @sub_i32rhs(i32 %in32) minsize {
define dso_local void @sub_i32rhs(i32 %in32) minsize {
; CHECK-LABEL: sub_i32rhs:
%val32_tmp = load i32, i32* @var32
%lhs64 = load i64, i64* @var64
@ -364,7 +364,7 @@ define void @sub_i32rhs(i32 %in32) minsize {
}
; Check that implicit zext from w reg write is used instead of uxtw form of add.
define i64 @add_fold_uxtw(i32 %x, i64 %y) {
define dso_local i64 @add_fold_uxtw(i32 %x, i64 %y) {
; CHECK-LABEL: add_fold_uxtw:
; GISEL-LABEL: add_fold_uxtw:
entry:
@ -381,7 +381,7 @@ entry:
; Check that implicit zext from w reg write is used instead of uxtw
; form of sub and that mov WZR is folded to form a neg instruction.
define i64 @sub_fold_uxtw_xzr(i32 %x) {
define dso_local i64 @sub_fold_uxtw_xzr(i32 %x) {
; CHECK-LABEL: sub_fold_uxtw_xzr:
; GISEL-LABEL: sub_fold_uxtw_xzr:
entry:
@ -396,7 +396,7 @@ entry:
}
; Check that implicit zext from w reg write is used instead of uxtw form of subs/cmp.
define i1 @cmp_fold_uxtw(i32 %x, i64 %y) {
define dso_local i1 @cmp_fold_uxtw(i32 %x, i64 %y) {
; CHECK-LABEL: cmp_fold_uxtw:
entry:
; CHECK: and w[[TMP:[0-9]+]], w0, #0x3
@ -410,7 +410,7 @@ entry:
; Check that implicit zext from w reg write is used instead of uxtw
; form of add, leading to madd selection.
define i64 @madd_fold_uxtw(i32 %x, i64 %y) {
define dso_local i64 @madd_fold_uxtw(i32 %x, i64 %y) {
; CHECK-LABEL: madd_fold_uxtw:
; GISEL-LABEL: madd_fold_uxtw:
entry:
@ -428,7 +428,7 @@ entry:
; Check that implicit zext from w reg write is used instead of uxtw
; form of sub, leading to sub/cmp folding.
; Check that implicit zext from w reg write is used instead of uxtw form of subs/cmp.
define i1 @cmp_sub_fold_uxtw(i32 %x, i64 %y, i64 %z) {
define dso_local i1 @cmp_sub_fold_uxtw(i32 %x, i64 %y, i64 %z) {
; CHECK-LABEL: cmp_sub_fold_uxtw:
entry:
; CHECK: and w[[TMP:[0-9]+]], w0, #0x3
@ -443,7 +443,7 @@ entry:
; Check that implicit zext from w reg write is used instead of uxtw
; form of add and add of -1 gets selected as sub.
define i64 @add_imm_fold_uxtw(i32 %x) {
define dso_local i64 @add_imm_fold_uxtw(i32 %x) {
; CHECK-LABEL: add_imm_fold_uxtw:
; GISEL-LABEL: add_imm_fold_uxtw:
entry:
@ -459,7 +459,7 @@ entry:
; Check that implicit zext from w reg write is used instead of uxtw
; form of add and add lsl form gets selected.
define i64 @add_lsl_fold_uxtw(i32 %x, i64 %y) {
define dso_local i64 @add_lsl_fold_uxtw(i32 %x, i64 %y) {
; CHECK-LABEL: add_lsl_fold_uxtw:
; GISEL-LABEL: add_lsl_fold_uxtw:
entry:

12
llvm/test/CodeGen/AArch64/and-sink.ll
View File

@ -1,12 +1,12 @@
; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs < %s | FileCheck %s
; RUN: opt -S -codegenprepare -mtriple=aarch64-linux %s | FileCheck --check-prefix=CHECK-CGP %s
@A = global i32 zeroinitializer
@B = global i32 zeroinitializer
@C = global i32 zeroinitializer
@A = dso_local global i32 zeroinitializer
@B = dso_local global i32 zeroinitializer
@C = dso_local global i32 zeroinitializer
; Test that and is sunk into cmp block to form tbz.
define i32 @and_sink1(i32 %a, i1 %c) {
define dso_local i32 @and_sink1(i32 %a, i1 %c) {
; CHECK-LABEL: and_sink1:
; CHECK: tbz w1, #0
; CHECK: str wzr, [x{{[0-9]+}}, :lo12:A]
@ -32,7 +32,7 @@ bb2:
}
; Test that both 'and' and cmp get sunk to form tbz.
define i32 @and_sink2(i32 %a, i1 %c, i1 %c2) {
define dso_local i32 @and_sink2(i32 %a, i1 %c, i1 %c2) {
; CHECK-LABEL: and_sink2:
; CHECK: str wzr, [x{{[0-9]+}}, :lo12:A]
; CHECK: tbz w1, #0
@ -68,7 +68,7 @@ bb3:
}
; Test that 'and' is not sunk since cbz is a better alternative.
define i32 @and_sink3(i32 %a) {
define dso_local i32 @and_sink3(i32 %a) {
; CHECK-LABEL: and_sink3:
; CHECK: and [[REG:w[0-9]+]], w0, #0x3
; CHECK: [[LOOP:.L[A-Z0-9_]+]]:

24
llvm/test/CodeGen/AArch64/arm64-aapcs.ll
View File

@ -1,9 +1,9 @@
; RUN: llc -mtriple=arm64-linux-gnu -enable-misched=false -disable-post-ra < %s | FileCheck %s
@var = global i32 0, align 4
@var = dso_local global i32 0, align 4
; CHECK-LABEL: @test_i128_align
define i128 @test_i128_align(i32, i128 %arg, i32 %after) {
define dso_local i128 @test_i128_align(i32, i128 %arg, i32 %after) {
store i32 %after, i32* @var, align 4
; CHECK-DAG: str w4, [{{x[0-9]+}}, :lo12:var]
@ -22,10 +22,10 @@ define [2 x i64] @test_i64x2_align(i32, [2 x i64] %arg, i32 %after) {
; CHECK: mov x1, x2
}
@var64 = global i64 0, align 8
@var64 = dso_local global i64 0, align 8
; Check stack slots are 64-bit at all times.
define void @test_stack_slots([8 x i64], i1 %bool, i8 %char, i16 %short,
define dso_local void @test_stack_slots([8 x i64], i1 %bool, i8 %char, i16 %short,
i32 %int, i64 %long) {
; CHECK-LABEL: test_stack_slots:
; CHECK-DAG: ldr w[[ext1:[0-9]+]], [sp, #24]
@ -60,7 +60,7 @@ define void @test_stack_slots([8 x i64], i1 %bool, i8 %char, i16 %short,
; Make sure the callee does extensions (in the absence of zext/sext
; keyword on args) while we're here.
define void @test_extension(i1 %bool, i8 %char, i16 %short, i32 %int) {
define dso_local void @test_extension(i1 %bool, i8 %char, i16 %short, i32 %int) {
%ext_bool = zext i1 %bool to i64
store volatile i64 %ext_bool, i64* @var64
; CHECK: and [[EXT:x[0-9]+]], x0, #0x1
@ -88,7 +88,7 @@ declare void @variadic(i32 %a, ...)
; Under AAPCS variadic functions have the same calling convention as
; others. The extra arguments should go in registers rather than on the stack.
define void @test_variadic() {
define dso_local void @test_variadic() {
call void(i32, ...) @variadic(i32 0, i64 1, double 2.0)
; CHECK: mov w1, #1
; CHECK: fmov d0, #2.0
@ -99,7 +99,7 @@ define void @test_variadic() {
; We weren't marking x7 as used after deciding that the i128 didn't fit into
; registers and putting the first half on the stack, so the *second* half went
; into x7. Yuck!
define i128 @test_i128_shadow([7 x i64] %x0_x6, i128 %sp) {
define dso_local i128 @test_i128_shadow([7 x i64] %x0_x6, i128 %sp) {
; CHECK-LABEL: test_i128_shadow:
; CHECK: ldp x0, x1, [sp]
@ -114,7 +114,7 @@ define fp128 @test_fp128([8 x float] %arg0, fp128 %arg1) {
}
; Check if VPR can be correctly pass by stack.
define <2 x double> @test_vreg_stack([8 x <2 x double>], <2 x double> %varg_stack) {
define dso_local <2 x double> @test_vreg_stack([8 x <2 x double>], <2 x double> %varg_stack) {
entry:
; CHECK-LABEL: test_vreg_stack:
; CHECK: ldr {{q[0-9]+}}, [sp]
@ -136,28 +136,28 @@ define half @test_half_const() {
}
; Check that v4f16 can be passed and returned in registers
define <4 x half> @test_v4_half_register(float, <4 x half> %arg) {
define dso_local <4 x half> @test_v4_half_register(float, <4 x half> %arg) {
; CHECK-LABEL: test_v4_half_register:
; CHECK: mov v0.16b, v1.16b
ret <4 x half> %arg;
}
; Check that v8f16 can be passed and returned in registers
define <8 x half> @test_v8_half_register(float, <8 x half> %arg) {
define dso_local <8 x half> @test_v8_half_register(float, <8 x half> %arg) {
; CHECK-LABEL: test_v8_half_register:
; CHECK: mov v0.16b, v1.16b
ret <8 x half> %arg;
}
; Check that v4f16 can be passed and returned on the stack
define <4 x half> @test_v4_half_stack([8 x <2 x double>], <4 x half> %arg) {
define dso_local <4 x half> @test_v4_half_stack([8 x <2 x double>], <4 x half> %arg) {
; CHECK-LABEL: test_v4_half_stack:
; CHECK: ldr d0, [sp]
ret <4 x half> %arg;
}
; Check that v8f16 can be passed and returned on the stack
define <8 x half> @test_v8_half_stack([8 x <2 x double>], <8 x half> %arg) {
define dso_local <8 x half> @test_v8_half_stack([8 x <2 x double>], <8 x half> %arg) {
; CHECK-LABEL: test_v8_half_stack:
; CHECK: ldr q0, [sp]
ret <8 x half> %arg;

6
llvm/test/CodeGen/AArch64/arm64-custom-call-saved-reg.ll
View File

@ -55,10 +55,10 @@
; RUN: --check-prefix=CHECK-SAVED-ALL-GISEL
; Used to exhaust the supply of GPRs.
@var = global [30 x i64] zeroinitializer
@var = dso_local global [30 x i64] zeroinitializer
; Check that callee preserves additional CSRs.
define void @callee() {
define dso_local void @callee() {
; CHECK-LABEL: callee
; CHECK-SAVED-X8: str x8, [sp
@ -100,7 +100,7 @@ define void @callee() {
}
; Check that caller doesn't shy away from allocating additional CSRs.
define void @caller() {
define dso_local void @caller() {
; CHECK-LABEL: caller
%val = load volatile [30 x i64], [30 x i64]* @var

36
llvm/test/CodeGen/AArch64/arm64-fp128.ll
View File

@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm64-linux-gnu -verify-machineinstrs -mcpu=cyclone -aarch64-enable-atomic-cfg-tidy=0 < %s | FileCheck -enable-var-scope %s
@lhs = global fp128 zeroinitializer, align 16
@rhs = global fp128 zeroinitializer, align 16
@lhs = dso_local global fp128 zeroinitializer, align 16
@rhs = dso_local global fp128 zeroinitializer, align 16
define fp128 @test_add() {
; CHECK-LABEL: test_add:
@ -68,10 +68,10 @@ define fp128 @test_div() {
ret fp128 %val
}
@var32 = global i32 0
@var64 = global i64 0
@var32 = dso_local global i32 0
@var64 = dso_local global i64 0
define void @test_fptosi() {
define dso_local void @test_fptosi() {
; CHECK-LABEL: test_fptosi:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32
@ -102,7 +102,7 @@ define void @test_fptosi() {
ret void
}
define void @test_fptoui() {
define dso_local void @test_fptoui() {
; CHECK-LABEL: test_fptoui:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32
@ -133,7 +133,7 @@ define void @test_fptoui() {
ret void
}
define void @test_sitofp() {
define dso_local void @test_sitofp() {
; CHECK-LABEL: test_sitofp:
; CHECK: // %bb.0:
; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
@ -163,7 +163,7 @@ define void @test_sitofp() {
ret void
}
define void @test_uitofp() {
define dso_local void @test_uitofp() {
; CHECK-LABEL: test_uitofp:
; CHECK: // %bb.0:
; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
@ -193,7 +193,7 @@ define void @test_uitofp() {
ret void
}
define i1 @test_setcc1() {
define dso_local i1 @test_setcc1() {
; CHECK-LABEL: test_setcc1:
; CHECK: // %bb.0:
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
@ -219,7 +219,7 @@ define i1 @test_setcc1() {
ret i1 %val
}
define i1 @test_setcc2() {
define dso_local i1 @test_setcc2() {
; CHECK-LABEL: test_setcc2:
; CHECK: // %bb.0:
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
@ -243,7 +243,7 @@ define i1 @test_setcc2() {
ret i1 %val
}
define i1 @test_setcc3() {
define dso_local i1 @test_setcc3() {
; CHECK-LABEL: test_setcc3:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48 // =48
@ -277,7 +277,7 @@ define i1 @test_setcc3() {
}
define i32 @test_br_cc() {
define dso_local i32 @test_br_cc() {
; CHECK-LABEL: test_br_cc:
; CHECK: // %bb.0:
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
@ -312,7 +312,7 @@ iffalse:
ret i32 29
}
define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) {
define dso_local void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) {
; CHECK-LABEL: test_select:
; CHECK: // %bb.0:
; CHECK-NEXT: tst w0, #0x1
@ -329,11 +329,11 @@ define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) {
ret void
}
@varhalf = global half 0.0, align 2
@varfloat = global float 0.0, align 4
@vardouble = global double 0.0, align 8
@varhalf = dso_local global half 0.0, align 2
@varfloat = dso_local global float 0.0, align 4
@vardouble = dso_local global double 0.0, align 8
define void @test_round() {
define dso_local void @test_round() {
; CHECK-LABEL: test_round:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32
@ -372,7 +372,7 @@ define void @test_round() {
ret void
}
define void @test_extend() {
define dso_local void @test_extend() {
; CHECK-LABEL: test_extend:
; CHECK: // %bb.0:
; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill

44
llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
View File

@ -3,7 +3,7 @@
%0 = type { i64, i64 }
define i128 @f0(i8* %p) nounwind readonly {
define dso_local i128 @f0(i8* %p) nounwind readonly {
; CHECK-LABEL: f0:
; CHECK: ldxp {{x[0-9]+}}, {{x[0-9]+}}, [x0]
entry:
@ -17,7 +17,7 @@ entry:
ret i128 %4
}
define i32 @f1(i8* %ptr, i128 %val) nounwind {
define dso_local i32 @f1(i8* %ptr, i128 %val) nounwind {
; CHECK-LABEL: f1:
; CHECK: stxp {{w[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, [x0]
entry:
@ -31,10 +31,10 @@ entry:
declare %0 @llvm.aarch64.ldxp(i8*) nounwind
declare i32 @llvm.aarch64.stxp(i64, i64, i8*) nounwind
@var = global i64 0, align 8
@var = dso_local global i64 0, align 8
; FALLBACK-NOT: remark:{{.*}}test_load_i8
define void @test_load_i8(i8* %addr) {
define dso_local void @test_load_i8(i8* %addr) {
; CHECK-LABEL: test_load_i8:
; CHECK: ldxrb w[[LOADVAL:[0-9]+]], [x0]
; CHECK-NOT: uxtb
@ -53,7 +53,7 @@ define void @test_load_i8(i8* %addr) {
}
; FALLBACK-NOT: remark:{{.*}}test_load_i16
define void @test_load_i16(i16* %addr) {
define dso_local void @test_load_i16(i16* %addr) {
; CHECK-LABEL: test_load_i16:
; CHECK: ldxrh w[[LOADVAL:[0-9]+]], [x0]
; CHECK-NOT: uxth
@ -72,7 +72,7 @@ define void @test_load_i16(i16* %addr) {
}
; FALLBACK-NOT: remark:{{.*}}test_load_i32
define void @test_load_i32(i32* %addr) {
define dso_local void @test_load_i32(i32* %addr) {
; CHECK-LABEL: test_load_i32:
; CHECK: ldxr w[[LOADVAL:[0-9]+]], [x0]
; CHECK-NOT: uxtw
@ -91,7 +91,7 @@ define void @test_load_i32(i32* %addr) {
}
; FALLBACK-NOT: remark:{{.*}}test_load_i64
define void @test_load_i64(i64* %addr) {
define dso_local void @test_load_i64(i64* %addr) {
; CHECK-LABEL: test_load_i64:
; CHECK: ldxr x[[LOADVAL:[0-9]+]], [x0]
; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
@ -112,7 +112,7 @@ declare i64 @llvm.aarch64.ldxr.p0i32(i32*) nounwind
declare i64 @llvm.aarch64.ldxr.p0i64(i64*) nounwind
; FALLBACK-NOT: remark:{{.*}}test_store_i8
define i32 @test_store_i8(i32, i8 %val, i8* %addr) {
define dso_local i32 @test_store_i8(i32, i8 %val, i8* %addr) {
; CHECK-LABEL: test_store_i8:
; CHECK-NOT: uxtb
; CHECK-NOT: and
@ -127,7 +127,7 @@ define i32 @test_store_i8(i32, i8 %val, i8* %addr) {
}
; FALLBACK-NOT: remark:{{.*}}test_store_i16
define i32 @test_store_i16(i32, i16 %val, i16* %addr) {
define dso_local i32 @test_store_i16(i32, i16 %val, i16* %addr) {
; CHECK-LABEL: test_store_i16:
; CHECK-NOT: uxth
; CHECK-NOT: and
@ -142,7 +142,7 @@ define i32 @test_store_i16(i32, i16 %val, i16* %addr) {
}
; FALLBACK-NOT: remark:{{.*}}test_store_i32
define i32 @test_store_i32(i32, i32 %val, i32* %addr) {
define dso_local i32 @test_store_i32(i32, i32 %val, i32* %addr) {
; CHECK-LABEL: test_store_i32:
; CHECK-NOT: uxtw
; CHECK-NOT: and
@ -157,7 +157,7 @@ define i32 @test_store_i32(i32, i32 %val, i32* %addr) {
}
; FALLBACK-NOT: remark:{{.*}}test_store_i64
define i32 @test_store_i64(i32, i64 %val, i64* %addr) {
define dso_local i32 @test_store_i64(i32, i64 %val, i64* %addr) {
; CHECK-LABEL: test_store_i64:
; CHECK: stxr w0, x1, [x2]
; GISEL-LABEL: test_store_i64:
@ -173,14 +173,14 @@ declare i32 @llvm.aarch64.stxr.p0i64(i64, i64*) nounwind
; CHECK: test_clear:
; CHECK: clrex
define void @test_clear() {
define dso_local void @test_clear() {
call void @llvm.aarch64.clrex()
ret void
}
declare void @llvm.aarch64.clrex() nounwind
define i128 @test_load_acquire_i128(i8* %p) nounwind readonly {
define dso_local i128 @test_load_acquire_i128(i8* %p) nounwind readonly {
; CHECK-LABEL: test_load_acquire_i128:
; CHECK: ldaxp {{x[0-9]+}}, {{x[0-9]+}}, [x0]
entry:
@ -194,7 +194,7 @@ entry:
ret i128 %4
}
define i32 @test_store_release_i128(i8* %ptr, i128 %val) nounwind {
define dso_local i32 @test_store_release_i128(i8* %ptr, i128 %val) nounwind {
; CHECK-LABEL: test_store_release_i128:
; CHECK: stlxp {{w[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, [x0]
entry:
@ -209,7 +209,7 @@ declare %0 @llvm.aarch64.ldaxp(i8*) nounwind
declare i32 @llvm.aarch64.stlxp(i64, i64, i8*) nounwind
; FALLBACK-NOT: remark:{{.*}}test_load_acquire_i8
define void @test_load_acquire_i8(i8* %addr) {
define dso_local void @test_load_acquire_i8(i8* %addr) {
; CHECK-LABEL: test_load_acquire_i8:
; CHECK: ldaxrb w[[LOADVAL:[0-9]+]], [x0]
; CHECK-NOT: uxtb
@ -227,7 +227,7 @@ define void @test_load_acquire_i8(i8* %addr) {
}
; FALLBACK-NOT: remark:{{.*}}test_load_acquire_i16
define void @test_load_acquire_i16(i16* %addr) {
define dso_local void @test_load_acquire_i16(i16* %addr) {
; CHECK-LABEL: test_load_acquire_i16:
; CHECK: ldaxrh w[[LOADVAL:[0-9]+]], [x0]
; CHECK-NOT: uxth
@ -245,7 +245,7 @@ define void @test_load_acquire_i16(i16* %addr) {
}
; FALLBACK-NOT: remark:{{.*}}test_load_acquire_i32
define void @test_load_acquire_i32(i32* %addr) {
define dso_local void @test_load_acquire_i32(i32* %addr) {
; CHECK-LABEL: test_load_acquire_i32:
; CHECK: ldaxr w[[LOADVAL:[0-9]+]], [x0]
; CHECK-NOT: uxtw
@ -263,7 +263,7 @@ define void @test_load_acquire_i32(i32* %addr) {
}
; FALLBACK-NOT: remark:{{.*}}test_load_acquire_i64
define void @test_load_acquire_i64(i64* %addr) {
define dso_local void @test_load_acquire_i64(i64* %addr) {
; CHECK-LABEL: test_load_acquire_i64:
; CHECK: ldaxr x[[LOADVAL:[0-9]+]], [x0]
; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
@ -283,7 +283,7 @@ declare i64 @llvm.aarch64.ldaxr.p0i32(i32*) nounwind
declare i64 @llvm.aarch64.ldaxr.p0i64(i64*) nounwind
; FALLBACK-NOT: remark:{{.*}}test_store_release_i8
define i32 @test_store_release_i8(i32, i8 %val, i8* %addr) {
define dso_local i32 @test_store_release_i8(i32, i8 %val, i8* %addr) {
; CHECK-LABEL: test_store_release_i8:
; CHECK-NOT: uxtb
; CHECK-NOT: and
@ -298,7 +298,7 @@ define i32 @test_store_release_i8(i32, i8 %val, i8* %addr) {
}
; FALLBACK-NOT: remark:{{.*}}test_store_release_i16
define i32 @test_store_release_i16(i32, i16 %val, i16* %addr) {
define dso_local i32 @test_store_release_i16(i32, i16 %val, i16* %addr) {
; CHECK-LABEL: test_store_release_i16:
; CHECK-NOT: uxth
; CHECK-NOT: and
@ -313,7 +313,7 @@ define i32 @test_store_release_i16(i32, i16 %val, i16* %addr) {
}
; FALLBACK-NOT: remark:{{.*}}test_store_release_i32
define i32 @test_store_release_i32(i32, i32 %val, i32* %addr) {
define dso_local i32 @test_store_release_i32(i32, i32 %val, i32* %addr) {
; CHECK-LABEL: test_store_release_i32:
; CHECK-NOT: uxtw
; CHECK-NOT: and
@ -328,7 +328,7 @@ define i32 @test_store_release_i32(i32, i32 %val, i32* %addr) {
}
; FALLBACK-NOT: remark:{{.*}}test_store_release_i64
define i32 @test_store_release_i64(i32, i64 %val, i64* %addr) {
define dso_local i32 @test_store_release_i64(i32, i64 %val, i64* %addr) {
; CHECK-LABEL: test_store_release_i64:
; CHECK: stlxr w0, x1, [x2]
; GISEL-LABEL: test_store_release_i64:

6
llvm/test/CodeGen/AArch64/arm64-misched-multimmo.ll
View File

@ -2,8 +2,8 @@
; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched=0 -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
@G1 = common global [100 x i32] zeroinitializer, align 4
@G2 = common global [100 x i32] zeroinitializer, align 4
@G1 = common dso_local global [100 x i32] zeroinitializer, align 4
@G2 = common dso_local global [100 x i32] zeroinitializer, align 4
; Check that no scheduling dependencies are created between the paired loads and the store during post-RA MI scheduling.
;
@ -13,7 +13,7 @@
; CHECK-NOT: ch SU(4)
; CHECK: SU(3)
; CHECK: SU(4): STRWui $wzr, renamable $x{{[0-9]+}}
define i32 @foo() {
define dso_local i32 @foo() {
entry:
%0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 0), align 4
%1 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 1), align 4

4
llvm/test/CodeGen/AArch64/arm64-sitofp-combine-chains.ll
View File

@ -5,9 +5,9 @@
; operations in this function both ended up direct successors to the EntryToken
; and could be reordered.
@var = global i32 0, align 4
@var = dso_local global i32 0, align 4
define float @foo() {
define dso_local float @foo() {
; CHECK-LABEL: foo:
; Load must come before we clobber @var
; CHECK: adrp x[[VARBASE:[0-9]+]], {{_?var}}

16
llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll
View File

@ -2,11 +2,11 @@
%va_list = type {i8*, i8*, i8*, i32, i32}
@var = global %va_list zeroinitializer, align 8
@var = dso_local global %va_list zeroinitializer, align 8
declare void @llvm.va_start(i8*)
define void @test_simple(i32 %n, ...) {
define dso_local void @test_simple(i32 %n, ...) {
; CHECK-LABEL: test_simple:
; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]]
@ -42,7 +42,7 @@ define void @test_simple(i32 %n, ...) {
ret void
}
define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) {
define dso_local void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) {
; CHECK-LABEL: test_fewargs:
; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]]
@ -77,7 +77,7 @@ define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) {
ret void
}
define void @test_nospare([8 x i64], [8 x float], ...) {
define dso_local void @test_nospare([8 x i64], [8 x float], ...) {
; CHECK-LABEL: test_nospare:
%addr = bitcast %va_list* @var to i8*
@ -92,7 +92,7 @@ define void @test_nospare([8 x i64], [8 x float], ...) {
; If there are non-variadic arguments on the stack (here two i64s) then the
; __stack field should point just past them.
define void @test_offsetstack([8 x i64], [2 x i64], [3 x float], ...) {
define dso_local void @test_offsetstack([8 x i64], [2 x i64], [3 x float], ...) {
; CHECK-LABEL: test_offsetstack:
; CHECK-DAG: stp {{q[0-9]+}}, {{q[0-9]+}}, [sp, #48]
@ -109,7 +109,7 @@ define void @test_offsetstack([8 x i64], [2 x i64], [3 x float], ...) {
declare void @llvm.va_end(i8*)
define void @test_va_end() nounwind {
define dso_local void @test_va_end() nounwind {
; CHECK-LABEL: test_va_end:
; CHECK-NEXT: %bb.0
@ -122,9 +122,9 @@ define void @test_va_end() nounwind {
declare void @llvm.va_copy(i8* %dest, i8* %src)
@second_list = global %va_list zeroinitializer
@second_list = dso_local global %va_list zeroinitializer
define void @test_va_copy() {
define dso_local void @test_va_copy() {
; CHECK-LABEL: test_va_copy:
%srcaddr = bitcast %va_list* @var to i8*
%dstaddr = bitcast %va_list* @second_list to i8*

806
llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
View File

File diff suppressed because it is too large Load Diff

124
llvm/test/CodeGen/AArch64/atomic-ops.ll
View File

@ -8,12 +8,12 @@
; CHECK-REG-NOT: stlxrb w[[NEW:[0-9]+]], w[[NEW]], [x{{[0-9]+}}]
; CHECK-REG-NOT: stlxrb w[[NEW:[0-9]+]], x[[NEW]], [x{{[0-9]+}}]
@var8 = global i8 0
@var16 = global i16 0
@var32 = global i32 0
@var64 = global i64 0
@var8 = dso_local global i8 0
@var16 = dso_local global i16 0
@var32 = dso_local global i32 0
@var64 = dso_local global i64 0
define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
define dso_local i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_add_i8:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_add_i8:
; OUTLINE_ATOMICS: // %bb.0:
@ -41,7 +41,7 @@ define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
ret i8 %old
}
define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
define dso_local i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_add_i16:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_add_i16:
; OUTLINE_ATOMICS: // %bb.0:
@ -69,7 +69,7 @@ define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
ret i16 %old
}
define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
define dso_local i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_add_i32:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_add_i32:
; OUTLINE_ATOMICS: // %bb.0:
@ -97,7 +97,7 @@ define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
ret i32 %old
}
define i64 @test_atomic_load_add_i64(i64 %offset) nounwind {
define dso_local i64 @test_atomic_load_add_i64(i64 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_add_i64:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_add_i64:
; OUTLINE_ATOMICS: // %bb.0:
@ -125,7 +125,7 @@ define i64 @test_atomic_load_add_i64(i64 %offset) nounwind {
ret i64 %old
}
define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind {
define dso_local i8 @test_atomic_load_sub_i8(i8 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_sub_i8:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_sub_i8:
; OUTLINE_ATOMICS: // %bb.0:
@ -154,7 +154,7 @@ define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind {
ret i8 %old
}
define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind {
define dso_local i16 @test_atomic_load_sub_i16(i16 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_sub_i16:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_sub_i16:
; OUTLINE_ATOMICS: // %bb.0:
@ -183,7 +183,7 @@ define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind {
ret i16 %old
}
define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind {
define dso_local i32 @test_atomic_load_sub_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_sub_i32:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_sub_i32:
; OUTLINE_ATOMICS: // %bb.0:
@ -212,7 +212,7 @@ define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind {
ret i32 %old
}
define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind {
define dso_local i64 @test_atomic_load_sub_i64(i64 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_sub_i64:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_sub_i64:
; OUTLINE_ATOMICS: // %bb.0:
@ -241,7 +241,7 @@ define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind {
ret i64 %old
}
define i8 @test_atomic_load_and_i8(i8 %offset) nounwind {
define dso_local i8 @test_atomic_load_and_i8(i8 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_and_i8:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_and_i8:
; OUTLINE_ATOMICS: // %bb.0:
@ -270,7 +270,7 @@ define i8 @test_atomic_load_and_i8(i8 %offset) nounwind {
ret i8 %old
}
define i16 @test_atomic_load_and_i16(i16 %offset) nounwind {
define dso_local i16 @test_atomic_load_and_i16(i16 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_and_i16:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_and_i16:
; OUTLINE_ATOMICS: // %bb.0:
@ -299,7 +299,7 @@ define i16 @test_atomic_load_and_i16(i16 %offset) nounwind {
ret i16 %old
}
define i32 @test_atomic_load_and_i32(i32 %offset) nounwind {
define dso_local i32 @test_atomic_load_and_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_and_i32:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_and_i32:
; OUTLINE_ATOMICS: // %bb.0:
@ -328,7 +328,7 @@ define i32 @test_atomic_load_and_i32(i32 %offset) nounwind {
ret i32 %old
}
define i64 @test_atomic_load_and_i64(i64 %offset) nounwind {
define dso_local i64 @test_atomic_load_and_i64(i64 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_and_i64:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_and_i64:
; OUTLINE_ATOMICS: // %bb.0:
@ -357,7 +357,7 @@ define i64 @test_atomic_load_and_i64(i64 %offset) nounwind {
ret i64 %old
}
define i8 @test_atomic_load_or_i8(i8 %offset) nounwind {
define dso_local i8 @test_atomic_load_or_i8(i8 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_or_i8:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_or_i8:
; OUTLINE_ATOMICS: // %bb.0:
@ -385,7 +385,7 @@ define i8 @test_atomic_load_or_i8(i8 %offset) nounwind {
ret i8 %old
}
define i16 @test_atomic_load_or_i16(i16 %offset) nounwind {
define dso_local i16 @test_atomic_load_or_i16(i16 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_or_i16:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_or_i16:
; OUTLINE_ATOMICS: // %bb.0:
@ -413,7 +413,7 @@ define i16 @test_atomic_load_or_i16(i16 %offset) nounwind {
ret i16 %old
}
define i32 @test_atomic_load_or_i32(i32 %offset) nounwind {
define dso_local i32 @test_atomic_load_or_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_or_i32:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_or_i32:
; OUTLINE_ATOMICS: // %bb.0:
@ -441,7 +441,7 @@ define i32 @test_atomic_load_or_i32(i32 %offset) nounwind {
ret i32 %old
}
define i64 @test_atomic_load_or_i64(i64 %offset) nounwind {
define dso_local i64 @test_atomic_load_or_i64(i64 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_or_i64:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_or_i64:
; OUTLINE_ATOMICS: // %bb.0:
@ -469,7 +469,7 @@ define i64 @test_atomic_load_or_i64(i64 %offset) nounwind {
ret i64 %old
}
define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind {
define dso_local i8 @test_atomic_load_xor_i8(i8 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_xor_i8:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_xor_i8:
; OUTLINE_ATOMICS: // %bb.0:
@ -497,7 +497,7 @@ define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind {
ret i8 %old
}
define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind {
define dso_local i16 @test_atomic_load_xor_i16(i16 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_xor_i16:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_xor_i16:
; OUTLINE_ATOMICS: // %bb.0:
@ -525,7 +525,7 @@ define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind {
ret i16 %old
}
define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind {
define dso_local i32 @test_atomic_load_xor_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_xor_i32:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_xor_i32:
; OUTLINE_ATOMICS: // %bb.0:
@ -553,7 +553,7 @@ define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind {
ret i32 %old
}
define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind {
define dso_local i64 @test_atomic_load_xor_i64(i64 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_xor_i64:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_xor_i64:
; OUTLINE_ATOMICS: // %bb.0:
@ -581,7 +581,7 @@ define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind {
ret i64 %old
}
define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind {
define dso_local i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_xchg_i8:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_xchg_i8:
; OUTLINE_ATOMICS: // %bb.0:
@ -608,7 +608,7 @@ define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind {
ret i8 %old
}
define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind {
define dso_local i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_xchg_i16:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_xchg_i16:
; OUTLINE_ATOMICS: // %bb.0:
@ -635,7 +635,7 @@ define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind {
ret i16 %old
}
define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind {
define dso_local i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_xchg_i32:
; CHECK: mov {{[xw]}}8, w[[OLD:[0-9]+]]
; OUTLINE_ATOMICS-LABEL: test_atomic_load_xchg_i32:
@ -661,7 +661,7 @@ define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind {
ret i32 %old
}
define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind {
define dso_local i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_xchg_i64:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_xchg_i64:
; OUTLINE_ATOMICS: // %bb.0:
@ -689,7 +689,7 @@ define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind {
}
define i8 @test_atomic_load_min_i8(i8 %offset) nounwind {
define dso_local i8 @test_atomic_load_min_i8(i8 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_min_i8:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_min_i8:
; OUTLINE_ATOMICS: // %bb.0:
@ -728,7 +728,7 @@ define i8 @test_atomic_load_min_i8(i8 %offset) nounwind {
ret i8 %old
}
define i16 @test_atomic_load_min_i16(i16 %offset) nounwind {
define dso_local i16 @test_atomic_load_min_i16(i16 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_min_i16:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_min_i16:
; OUTLINE_ATOMICS: // %bb.0:
@ -768,7 +768,7 @@ define i16 @test_atomic_load_min_i16(i16 %offset) nounwind {
ret i16 %old
}
define i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
define dso_local i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_min_i32:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_min_i32:
; OUTLINE_ATOMICS: // %bb.0:
@ -806,7 +806,7 @@ define i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
ret i32 %old
}
define i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
define dso_local i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_min_i64:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_min_i64:
; OUTLINE_ATOMICS: // %bb.0:
@ -844,7 +844,7 @@ define i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
ret i64 %old
}
define i8 @test_atomic_load_max_i8(i8 %offset) nounwind {
define dso_local i8 @test_atomic_load_max_i8(i8 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_max_i8:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_max_i8:
; OUTLINE_ATOMICS: // %bb.0:
@ -884,7 +884,7 @@ define i8 @test_atomic_load_max_i8(i8 %offset) nounwind {
ret i8 %old
}
define i16 @test_atomic_load_max_i16(i16 %offset) nounwind {
define dso_local i16 @test_atomic_load_max_i16(i16 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_max_i16:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_max_i16:
; OUTLINE_ATOMICS: // %bb.0:
@ -924,7 +924,7 @@ define i16 @test_atomic_load_max_i16(i16 %offset) nounwind {
ret i16 %old
}
define i32 @test_atomic_load_max_i32(i32 %offset) nounwind {
define dso_local i32 @test_atomic_load_max_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_max_i32:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_max_i32:
; OUTLINE_ATOMICS: // %bb.0:
@ -962,7 +962,7 @@ define i32 @test_atomic_load_max_i32(i32 %offset) nounwind {
ret i32 %old
}
define i64 @test_atomic_load_max_i64(i64 %offset) nounwind {
define dso_local i64 @test_atomic_load_max_i64(i64 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_max_i64:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_max_i64:
; OUTLINE_ATOMICS: // %bb.0:
@ -1000,7 +1000,7 @@ define i64 @test_atomic_load_max_i64(i64 %offset) nounwind {
ret i64 %old
}
define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
define dso_local i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_umin_i8:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_umin_i8:
; OUTLINE_ATOMICS: // %bb.0:
@ -1038,7 +1038,7 @@ define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
ret i8 %old
}
define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
define dso_local i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_umin_i16:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_umin_i16:
; OUTLINE_ATOMICS: // %bb.0:
@ -1076,7 +1076,7 @@ define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
ret i16 %old
}
define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
define dso_local i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_umin_i32:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_umin_i32:
; OUTLINE_ATOMICS: // %bb.0:
@ -1114,7 +1114,7 @@ define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
ret i32 %old
}
define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
define dso_local i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_umin_i64:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_umin_i64:
; OUTLINE_ATOMICS: // %bb.0:
@ -1152,7 +1152,7 @@ define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
ret i64 %old
}
define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind {
define dso_local i8 @test_atomic_load_umax_i8(i8 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_umax_i8:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_umax_i8:
; OUTLINE_ATOMICS: // %bb.0:
@ -1190,7 +1190,7 @@ define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind {
ret i8 %old
}
define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind {
define dso_local i16 @test_atomic_load_umax_i16(i16 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_umax_i16:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_umax_i16:
; OUTLINE_ATOMICS: // %bb.0:
@ -1228,7 +1228,7 @@ define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind {
ret i16 %old
}
define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind {
define dso_local i32 @test_atomic_load_umax_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_umax_i32:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_umax_i32:
; OUTLINE_ATOMICS: // %bb.0:
@ -1266,7 +1266,7 @@ define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind {
ret i32 %old
}
define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind {
define dso_local i64 @test_atomic_load_umax_i64(i64 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_umax_i64:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_umax_i64:
; OUTLINE_ATOMICS: // %bb.0:
@ -1304,7 +1304,7 @@ define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind {
ret i64 %old
}
define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind {
define dso_local i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind {
; CHECK-LABEL: test_atomic_cmpxchg_i8:
; OUTLINE_ATOMICS-LABEL: test_atomic_cmpxchg_i8:
; OUTLINE_ATOMICS: // %bb.0:
@ -1337,7 +1337,7 @@ define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind {
ret i8 %old
}
define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind {
define dso_local i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind {
; CHECK-LABEL: test_atomic_cmpxchg_i16:
; OUTLINE_ATOMICS-LABEL: test_atomic_cmpxchg_i16:
; OUTLINE_ATOMICS: // %bb.0:
@ -1370,7 +1370,7 @@ define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind {
ret i16 %old
}
define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
define dso_local i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
; CHECK-LABEL: test_atomic_cmpxchg_i32:
; OUTLINE_ATOMICS-LABEL: test_atomic_cmpxchg_i32:
; OUTLINE_ATOMICS: // %bb.0:
@ -1401,7 +1401,7 @@ define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
ret i32 %old
}
define void @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
define dso_local void @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
; CHECK-LABEL: test_atomic_cmpxchg_i64:
; OUTLINE_ATOMICS-LABEL: test_atomic_cmpxchg_i64:
; OUTLINE_ATOMICS: // %bb.0:
@ -1438,7 +1438,7 @@ define void @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
ret void
}
define i8 @test_atomic_load_monotonic_i8() nounwind {
define dso_local i8 @test_atomic_load_monotonic_i8() nounwind {
; CHECK-LABEL: test_atomic_load_monotonic_i8:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_monotonic_i8:
; OUTLINE_ATOMICS: // %bb.0:
@ -1454,7 +1454,7 @@ define i8 @test_atomic_load_monotonic_i8() nounwind {
ret i8 %val
}
define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind {
define dso_local i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind {
; CHECK-LABEL: test_atomic_load_monotonic_regoff_i8:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_monotonic_regoff_i8:
; OUTLINE_ATOMICS: // %bb.0:
@ -1471,7 +1471,7 @@ define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind {
ret i8 %val
}
define i8 @test_atomic_load_acquire_i8() nounwind {
define dso_local i8 @test_atomic_load_acquire_i8() nounwind {
; CHECK-LABEL: test_atomic_load_acquire_i8:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_acquire_i8:
; OUTLINE_ATOMICS: // %bb.0:
@ -1490,7 +1490,7 @@ define i8 @test_atomic_load_acquire_i8() nounwind {
ret i8 %val
}
define i8 @test_atomic_load_seq_cst_i8() nounwind {
define dso_local i8 @test_atomic_load_seq_cst_i8() nounwind {
; CHECK-LABEL: test_atomic_load_seq_cst_i8:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_seq_cst_i8:
; OUTLINE_ATOMICS: // %bb.0:
@ -1509,7 +1509,7 @@ define i8 @test_atomic_load_seq_cst_i8() nounwind {
ret i8 %val
}
define i16 @test_atomic_load_monotonic_i16() nounwind {
define dso_local i16 @test_atomic_load_monotonic_i16() nounwind {
; CHECK-LABEL: test_atomic_load_monotonic_i16:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_monotonic_i16:
; OUTLINE_ATOMICS: // %bb.0:
@ -1526,7 +1526,7 @@ define i16 @test_atomic_load_monotonic_i16() nounwind {
ret i16 %val
}
define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind {
define dso_local i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind {
; CHECK-LABEL: test_atomic_load_monotonic_regoff_i32:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_monotonic_regoff_i32:
; OUTLINE_ATOMICS: // %bb.0:
@ -1543,7 +1543,7 @@ define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind
ret i32 %val
}
define i64 @test_atomic_load_seq_cst_i64() nounwind {
define dso_local i64 @test_atomic_load_seq_cst_i64() nounwind {
; CHECK-LABEL: test_atomic_load_seq_cst_i64:
; OUTLINE_ATOMICS-LABEL: test_atomic_load_seq_cst_i64:
; OUTLINE_ATOMICS: // %bb.0:
@ -1562,7 +1562,7 @@ define i64 @test_atomic_load_seq_cst_i64() nounwind {
ret i64 %val
}
define void @test_atomic_store_monotonic_i8(i8 %val) nounwind {
define dso_local void @test_atomic_store_monotonic_i8(i8 %val) nounwind {
; CHECK-LABEL: test_atomic_store_monotonic_i8:
; OUTLINE_ATOMICS-LABEL: test_atomic_store_monotonic_i8:
; OUTLINE_ATOMICS: // %bb.0:
@ -1576,7 +1576,7 @@ define void @test_atomic_store_monotonic_i8(i8 %val) nounwind {
ret void
}
define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val) nounwind {
define dso_local void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val) nounwind {
; CHECK-LABEL: test_atomic_store_monotonic_regoff_i8:
; OUTLINE_ATOMICS-LABEL: test_atomic_store_monotonic_regoff_i8:
; OUTLINE_ATOMICS: // %bb.0:
@ -1590,7 +1590,7 @@ define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val)
ret void
}
define void @test_atomic_store_release_i8(i8 %val) nounwind {
define dso_local void @test_atomic_store_release_i8(i8 %val) nounwind {
; CHECK-LABEL: test_atomic_store_release_i8:
; OUTLINE_ATOMICS-LABEL: test_atomic_store_release_i8:
; OUTLINE_ATOMICS: // %bb.0:
@ -1609,7 +1609,7 @@ define void @test_atomic_store_release_i8(i8 %val) nounwind {
ret void
}
define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind {
define dso_local void @test_atomic_store_seq_cst_i8(i8 %val) nounwind {
; CHECK-LABEL: test_atomic_store_seq_cst_i8:
; OUTLINE_ATOMICS-LABEL: test_atomic_store_seq_cst_i8:
; OUTLINE_ATOMICS: // %bb.0:
@ -1629,7 +1629,7 @@ define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind {
ret void
}
define void @test_atomic_store_monotonic_i16(i16 %val) nounwind {
define dso_local void @test_atomic_store_monotonic_i16(i16 %val) nounwind {
; CHECK-LABEL: test_atomic_store_monotonic_i16:
; OUTLINE_ATOMICS-LABEL: test_atomic_store_monotonic_i16:
; OUTLINE_ATOMICS: // %bb.0:
@ -1645,7 +1645,7 @@ define void @test_atomic_store_monotonic_i16(i16 %val) nounwind {
ret void
}
define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %val) nounwind {
define dso_local void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %val) nounwind {
; CHECK-LABEL: test_atomic_store_monotonic_regoff_i32:
; OUTLINE_ATOMICS-LABEL: test_atomic_store_monotonic_regoff_i32:
; OUTLINE_ATOMICS: // %bb.0:
@ -1662,7 +1662,7 @@ define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %va
ret void
}
define void @test_atomic_store_release_i64(i64 %val) nounwind {
define dso_local void @test_atomic_store_release_i64(i64 %val) nounwind {
; CHECK-LABEL: test_atomic_store_release_i64:
; OUTLINE_ATOMICS-LABEL: test_atomic_store_release_i64:
; OUTLINE_ATOMICS: // %bb.0:

30
llvm/test/CodeGen/AArch64/bitfield.ll
View File

@ -1,9 +1,9 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
@var32 = global i32 0
@var64 = global i64 0
@var32 = dso_local global i32 0
@var64 = dso_local global i64 0
define void @test_extendb32(i8 %var) {
define dso_local void @test_extendb32(i8 %var) {
; CHECK-LABEL: test_extendb32:
%sxt32 = sext i8 %var to i32
@ -19,7 +19,7 @@ define void @test_extendb32(i8 %var) {
ret void
}
define void @test_extendb64(i8 %var) {
define dso_local void @test_extendb64(i8 %var) {
; CHECK-LABEL: test_extendb64:
%sxt64 = sext i8 %var to i64
@ -35,7 +35,7 @@ define void @test_extendb64(i8 %var) {
ret void
}
define void @test_extendh32(i16 %var) {
define dso_local void @test_extendh32(i16 %var) {
; CHECK-LABEL: test_extendh32:
%sxt32 = sext i16 %var to i32
@ -51,7 +51,7 @@ define void @test_extendh32(i16 %var) {
ret void
}
define void @test_extendh64(i16 %var) {
define dso_local void @test_extendh64(i16 %var) {
; CHECK-LABEL: test_extendh64:
%sxt64 = sext i16 %var to i64
@ -67,7 +67,7 @@ define void @test_extendh64(i16 %var) {
ret void
}
define void @test_extendw(i32 %var) {
define dso_local void @test_extendw(i32 %var) {
; CHECK-LABEL: test_extendw:
%sxt64 = sext i32 %var to i64
@ -80,7 +80,7 @@ define void @test_extendw(i32 %var) {
ret void
}
define void @test_shifts(i32 %val32, i64 %val64) {
define dso_local void @test_shifts(i32 %val32, i64 %val64) {
; CHECK-LABEL: test_shifts:
%shift1 = ashr i32 %val32, 31
@ -128,7 +128,7 @@ define void @test_shifts(i32 %val32, i64 %val64) {
; LLVM can produce in-register extensions taking place entirely with
; 64-bit registers too.
define void @test_sext_inreg_64(i64 %in) {
define dso_local void @test_sext_inreg_64(i64 %in) {
; CHECK-LABEL: test_sext_inreg_64:
; i1 doesn't have an official alias, but crops up and is handled by
@ -157,7 +157,7 @@ define void @test_sext_inreg_64(i64 %in) {
; These instructions don't actually select to official bitfield
; operations, but it's important that we select them somehow:
define void @test_zext_inreg_64(i64 %in) {
define dso_local void @test_zext_inreg_64(i64 %in) {
; CHECK-LABEL: test_zext_inreg_64:
%trunc_i8 = trunc i64 %in to i8
@ -178,7 +178,7 @@ define void @test_zext_inreg_64(i64 %in) {
ret void
}
define i64 @test_sext_inreg_from_32(i32 %in) {
define dso_local i64 @test_sext_inreg_from_32(i32 %in) {
; CHECK-LABEL: test_sext_inreg_from_32:
%small = trunc i32 %in to i1
@ -192,7 +192,7 @@ define i64 @test_sext_inreg_from_32(i32 %in) {
}
define i32 @test_ubfx32(i32* %addr) {
define dso_local i32 @test_ubfx32(i32* %addr) {
; CHECK-LABEL: test_ubfx32:
; CHECK: ubfx {{w[0-9]+}}, {{w[0-9]+}}, #23, #3
@ -202,7 +202,7 @@ define i32 @test_ubfx32(i32* %addr) {
ret i32 %masked
}
define i64 @test_ubfx64(i64* %addr) {
define dso_local i64 @test_ubfx64(i64* %addr) {
; CHECK-LABEL: test_ubfx64:
; CHECK: ubfx {{x[0-9]+}}, {{x[0-9]+}}, #25, #10
%fields = load i64, i64* %addr
@ -211,7 +211,7 @@ define i64 @test_ubfx64(i64* %addr) {
ret i64 %masked
}
define i32 @test_sbfx32(i32* %addr) {
define dso_local i32 @test_sbfx32(i32* %addr) {
; CHECK-LABEL: test_sbfx32:
; CHECK: sbfx {{w[0-9]+}}, {{w[0-9]+}}, #6, #3
@ -221,7 +221,7 @@ define i32 @test_sbfx32(i32* %addr) {
ret i32 %extended
}
define i64 @test_sbfx64(i64* %addr) {
define dso_local i64 @test_sbfx64(i64* %addr) {
; CHECK-LABEL: test_sbfx64:
; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #63

10
llvm/test/CodeGen/AArch64/bool-loads.ll
View File

@ -1,8 +1,8 @@
; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s
@var = global i1 0
@var = dso_local global i1 0
define i32 @test_sextloadi32() {
define dso_local i32 @test_sextloadi32() {
; CHECK-LABEL: test_sextloadi32
%val = load i1, i1* @var
@ -14,7 +14,7 @@ define i32 @test_sextloadi32() {
; CHECK: ret
}
define i64 @test_sextloadi64() {
define dso_local i64 @test_sextloadi64() {
; CHECK-LABEL: test_sextloadi64
%val = load i1, i1* @var
@ -26,7 +26,7 @@ define i64 @test_sextloadi64() {
; CHECK: ret
}
define i32 @test_zextloadi32() {
define dso_local i32 @test_zextloadi32() {
; CHECK-LABEL: test_zextloadi32
; It's not actually necessary that "ret" is next, but as far as LLVM
@ -40,7 +40,7 @@ define i32 @test_zextloadi32() {
; CHECK-NEXT: ret
}
define i64 @test_zextloadi64() {
define dso_local i64 @test_zextloadi64() {
; CHECK-LABEL: test_zextloadi64
; It's not actually necessary that "ret" is next, but as far as LLVM

4
llvm/test/CodeGen/AArch64/breg.ll
View File

@ -1,8 +1,8 @@
; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
@stored_label = global i8* null
@stored_label = dso_local global i8* null
define void @foo() {
define dso_local void @foo() {
; CHECK-LABEL: foo:
%lab = load i8*, i8** @stored_label
indirectbr i8* %lab, [label %otherlab, label %retlab]

16
llvm/test/CodeGen/AArch64/call-rv-marker.ll
View File

@ -22,10 +22,10 @@ declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
%struct.S = type { i8 }
@g = global i8* null, align 8
@fptr = global i8* ()* null, align 8
@g = dso_local global i8* null, align 8
@fptr = dso_local global i8* ()* null, align 8
define i8* @rv_marker_1() {
define dso_local i8* @rv_marker_1() {
; CHECK-LABEL: rv_marker_1:
; CHECK: .cfi_offset w30, -16
; CHECK-NEXT: bl foo1
@ -37,7 +37,7 @@ entry:
ret i8* %call
}
define void @rv_marker_2_select(i32 %c) {
define dso_local void @rv_marker_2_select(i32 %c) {
; CHECK-LABEL: rv_marker_2_select:
; SELDAG: cinc w0, w8, eq
; GISEL: csinc w0, w8, wzr, eq
@ -54,7 +54,7 @@ entry:
ret void
}
define void @rv_marker_3() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
define dso_local void @rv_marker_3() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
; CHECK-LABEL: rv_marker_3
; CHECK: .cfi_offset w30, -32
; CHECK-NEXT: bl foo1
@ -76,7 +76,7 @@ lpad: ; preds = %entry
resume { i8*, i32 } %0
}
define void @rv_marker_4() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
define dso_local void @rv_marker_4() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
; CHECK-LABEL: rv_marker_4
; CHECK: .Ltmp3:
; CHECK-NEXT: bl foo1
@ -118,7 +118,7 @@ ehcleanup: ; preds = %lpad1, %lpad
resume { i8*, i32 } %.pn
}
define i8* @rv_marker_5_indirect_call() {
define dso_local i8* @rv_marker_5_indirect_call() {
; CHECK-LABEL: rv_marker_5_indirect_call
; CHECK: ldr [[ADDR:x[0-9]+]], [
; CHECK-NEXT: blr [[ADDR]]
@ -134,7 +134,7 @@ entry:
declare void @foo(i64, i64, i64)
define void @rv_marker_multiarg(i64 %a, i64 %b, i64 %c) {
define dso_local void @rv_marker_multiarg(i64 %a, i64 %b, i64 %c) {
; CHECK-LABEL: rv_marker_multiarg
; CHECK: mov [[TMP:x[0-9]+]], x0
; CHECK-NEXT: mov x0, x2

2
llvm/test/CodeGen/AArch64/cmpxchg-O0.ll
View File

@ -90,7 +90,7 @@ define { i128, i1 } @test_cmpxchg_128(i128* %addr, i128 %desired, i128 %new) nou
; Original implementation assumed the desired & new arguments had already been
; type-legalized into some kind of BUILD_PAIR operation and crashed when this
; was false.
@var128 = global i128 0
@var128 = dso_local global i128 0
define {i128, i1} @test_cmpxchg_128_unsplit(i128* %addr) {
; OUTLINE-ATOMICS: bl __aarch64_cas16_acq_rel
; CHECK-LABEL: test_cmpxchg_128_unsplit:

20
llvm/test/CodeGen/AArch64/code-model-large-abs.ll
View File

@ -1,11 +1,11 @@
; RUN: llc -mtriple=aarch64-linux-gnu -code-model=large -o - %s | FileCheck %s
@var8 = global i8 0
@var16 = global i16 0
@var32 = global i32 0
@var64 = global i64 0
@var8 = dso_local global i8 0
@var16 = dso_local global i16 0
@var32 = dso_local global i32 0
@var64 = dso_local global i64 0
define i8* @global_addr() {
define dso_local i8* @global_addr() {
; CHECK-LABEL: global_addr:
ret i8* @var8
; The movz/movk calculation should end up returned directly in x0.
@ -16,7 +16,7 @@ define i8* @global_addr() {
; CHECK-NEXT: ret
}
define i8 @global_i8() {
define dso_local i8 @global_i8() {
; CHECK-LABEL: global_i8:
%val = load i8, i8* @var8
ret i8 %val
@ -27,7 +27,7 @@ define i8 @global_i8() {
; CHECK: ldrb w0, [x[[ADDR_REG]]]
}
define i16 @global_i16() {
define dso_local i16 @global_i16() {
; CHECK-LABEL: global_i16:
%val = load i16, i16* @var16
ret i16 %val
@ -38,7 +38,7 @@ define i16 @global_i16() {
; CHECK: ldrh w0, [x[[ADDR_REG]]]
}
define i32 @global_i32() {
define dso_local i32 @global_i32() {
; CHECK-LABEL: global_i32:
%val = load i32, i32* @var32
ret i32 %val
@ -49,7 +49,7 @@ define i32 @global_i32() {
; CHECK: ldr w0, [x[[ADDR_REG]]]
}
define i64 @global_i64() {
define dso_local i64 @global_i64() {
; CHECK-LABEL: global_i64:
%val = load i64, i64* @var64
ret i64 %val
@ -60,7 +60,7 @@ define i64 @global_i64() {
; CHECK: ldr x0, [x[[ADDR_REG]]]
}
define <2 x i64> @constpool() {
define dso_local <2 x i64> @constpool() {
; CHECK-LABEL: constpool:
ret <2 x i64> <i64 123456789, i64 987654321100>

20
llvm/test/CodeGen/AArch64/code-model-tiny-abs.ll
View File

@ -1,11 +1,11 @@
; RUN: llc -mtriple=aarch64-none-eabi -code-model=tiny < %s | FileCheck %s
@var8 = global i8 0
@var16 = global i16 0
@var32 = global i32 0
@var64 = global i64 0
@var8 = dso_local global i8 0
@var16 = dso_local global i16 0
@var32 = dso_local global i32 0
@var64 = dso_local global i64 0
define i8* @global_addr() {
define dso_local i8* @global_addr() {
; CHECK-LABEL: global_addr:
ret i8* @var8
; The adr calculation should end up returned directly in x0.
@ -13,7 +13,7 @@ define i8* @global_addr() {
; CHECK-NEXT: ret
}
define i8 @global_i8() {
define dso_local i8 @global_i8() {
; CHECK-LABEL: global_i8:
%val = load i8, i8* @var8
ret i8 %val
@ -21,7 +21,7 @@ define i8 @global_i8() {
; CHECK: ldrb w0, [x[[ADDR_REG]]]
}
define i16 @global_i16() {
define dso_local i16 @global_i16() {
; CHECK-LABEL: global_i16:
%val = load i16, i16* @var16
ret i16 %val
@ -29,21 +29,21 @@ define i16 @global_i16() {
; CHECK: ldrh w0, [x[[ADDR_REG]]]
}
define i32 @global_i32() {
define dso_local i32 @global_i32() {
; CHECK-LABEL: global_i32:
%val = load i32, i32* @var32
ret i32 %val
; CHECK: ldr w0, var32
}
define i64 @global_i64() {
define dso_local i64 @global_i64() {
; CHECK-LABEL: global_i64:
%val = load i64, i64* @var64
ret i64 %val
; CHECK: ldr x0, var64
}
define <2 x i64> @constpool() {
define dso_local <2 x i64> @constpool() {
; CHECK-LABEL: constpool:
ret <2 x i64> <i64 123456789, i64 987654321100>

6
llvm/test/CodeGen/AArch64/fcopysign.ll
View File

@ -6,9 +6,9 @@ target triple = "aarch64--"
declare fp128 @llvm.copysign.f128(fp128, fp128)
@val_float = global float zeroinitializer, align 4
@val_double = global double zeroinitializer, align 8
@val_fp128 = global fp128 zeroinitializer, align 16
@val_float = dso_local global float zeroinitializer, align 4
@val_double = dso_local global double zeroinitializer, align 8
@val_fp128 = dso_local global fp128 zeroinitializer, align 16
define fp128 @copysign0() {
; CHECK-LABEL: copysign0:

40
llvm/test/CodeGen/AArch64/func-argpassing.ll
View File

@ -3,15 +3,15 @@
%myStruct = type { i64 , i8, i32 }
@var8 = global i8 0
@var32 = global i32 0
@var64 = global i64 0
@var128 = global i128 0
@varfloat = global float 0.0
@vardouble = global double 0.0
@varstruct = global %myStruct zeroinitializer
@var8 = dso_local global i8 0
@var32 = dso_local global i32 0
@var64 = dso_local global i64 0
@var128 = dso_local global i128 0
@varfloat = dso_local global float 0.0
@vardouble = dso_local global double 0.0
@varstruct = dso_local global %myStruct zeroinitializer
define void @take_i8s(i8 %val1, i8 %val2) {
define dso_local void @take_i8s(i8 %val1, i8 %val2) {
; CHECK-LABEL: take_i8s:
store i8 %val2, i8* @var8
; Not using w1 may be technically allowed, but it would indicate a
@ -20,7 +20,7 @@ define void @take_i8s(i8 %val1, i8 %val2) {
ret void
}
define void @add_floats(float %val1, float %val2) {
define dso_local void @add_floats(float %val1, float %val2) {
; CHECK-LABEL: add_floats:
%newval = fadd float %val1, %val2
; CHECK: fadd [[ADDRES:s[0-9]+]], s0, s1
@ -32,7 +32,7 @@ define void @add_floats(float %val1, float %val2) {
; byval pointers should be allocated to the stack and copied as if
; with memcpy.
define void @take_struct(%myStruct* byval(%myStruct) %structval) {
define dso_local void @take_struct(%myStruct* byval(%myStruct) %structval) {
; CHECK-LABEL: take_struct:
%addr0 = getelementptr %myStruct, %myStruct* %structval, i64 0, i32 2
%addr1 = getelementptr %myStruct, %myStruct* %structval, i64 0, i32 0
@ -52,7 +52,7 @@ define void @take_struct(%myStruct* byval(%myStruct) %structval) {
}
; %structval should be at sp + 16
define void @check_byval_align(i32* byval(i32) %ignore, %myStruct* byval(%myStruct) align 16 %structval) {
define dso_local void @check_byval_align(i32* byval(i32) %ignore, %myStruct* byval(%myStruct) align 16 %structval) {
; CHECK-LABEL: check_byval_align:
%addr0 = getelementptr %myStruct, %myStruct* %structval, i64 0, i32 2
@ -72,7 +72,7 @@ define void @check_byval_align(i32* byval(i32) %ignore, %myStruct* byval(%myStru
ret void
}
define i32 @return_int() {
define dso_local i32 @return_int() {
; CHECK-LABEL: return_int:
%val = load i32, i32* @var32
ret i32 %val
@ -81,7 +81,7 @@ define i32 @return_int() {
; CHECK-NEXT: ret
}
define double @return_double() {
define dso_local double @return_double() {
; CHECK-LABEL: return_double:
ret double 3.14
; CHECK: ldr d0, [{{x[0-9]+}}, {{#?}}:lo12:.LCPI
@ -106,7 +106,7 @@ define [2 x i64] @return_struct() {
; to preserve value semantics) in x8. Strictly this only applies to
; structs larger than 16 bytes, but C semantics can still be provided
; if LLVM does it to %myStruct too. So this is the simplest check
define void @return_large_struct(%myStruct* sret(%myStruct) %retval) {
define dso_local void @return_large_struct(%myStruct* sret(%myStruct) %retval) {
; CHECK-LABEL: return_large_struct:
%addr0 = getelementptr %myStruct, %myStruct* %retval, i64 0, i32 0
%addr1 = getelementptr %myStruct, %myStruct* %retval, i64 0, i32 1
@ -125,7 +125,7 @@ define void @return_large_struct(%myStruct* sret(%myStruct) %retval) {
; This struct is just too far along to go into registers: (only x7 is
; available, but it needs two). Also make sure that %stacked doesn't
; sneak into x7 behind.
define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45,
define dso_local i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45,
i32* %var6, %myStruct* byval(%myStruct) %struct, i32* byval(i32) %stacked,
double %notstacked) {
; CHECK-LABEL: struct_on_stack:
@ -146,7 +146,7 @@ define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var
; CHECK-LE: ldr w0, [sp, #16]
}
define void @stacked_fpu(float %var0, double %var1, float %var2, float %var3,
define dso_local void @stacked_fpu(float %var0, double %var1, float %var2, float %var3,
float %var4, float %var5, float %var6, float %var7,
float %var8) {
; CHECK-LABEL: stacked_fpu:
@ -161,7 +161,7 @@ define void @stacked_fpu(float %var0, double %var1, float %var2, float %var3,
; 128-bit integer types should be passed in xEVEN, xODD rather than
; the reverse. In this case x2 and x3. Nothing should use x1.
define i64 @check_i128_regalign(i32 %val0, i128 %val1, i64 %val2) {
define dso_local i64 @check_i128_regalign(i32 %val0, i128 %val1, i64 %val2) {
; CHECK-LABEL: check_i128_regalign
store i128 %val1, i128* @var128
; CHECK-DAG: add x[[VAR128:[0-9]+]], {{x[0-9]+}}, :lo12:var128
@ -171,7 +171,7 @@ define i64 @check_i128_regalign(i32 %val0, i128 %val1, i64 %val2) {
; CHECK-DAG: mov x0, x4
}
define void @check_i128_stackalign(i32 %val0, i32 %val1, i32 %val2, i32 %val3,
define dso_local void @check_i128_stackalign(i32 %val0, i32 %val1, i32 %val2, i32 %val3,
i32 %val4, i32 %val5, i32 %val6, i32 %val7,
i32 %stack1, i128 %stack2) {
; CHECK-LABEL: check_i128_stackalign
@ -188,7 +188,7 @@ define void @check_i128_stackalign(i32 %val0, i32 %val1, i32 %val2, i32 %val3,
declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i1)
define i32 @test_extern() {
define dso_local i32 @test_extern() {
; CHECK-LABEL: test_extern:
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 undef, i8* align 4 undef, i32 undef, i1 0)
; CHECK: bl memcpy
@ -198,7 +198,7 @@ define i32 @test_extern() {
; A sub-i32 stack argument must be loaded on big endian with ldr{h,b}, not just
; implicitly extended to a 32-bit load.
define i16 @stacked_i16(i32 %val0, i32 %val1, i32 %val2, i32 %val3,
define dso_local i16 @stacked_i16(i32 %val0, i32 %val1, i32 %val2, i32 %val3,
i32 %val4, i32 %val5, i32 %val6, i32 %val7,
i16 %stack1) {
; CHECK-LABEL: stacked_i16

32
llvm/test/CodeGen/AArch64/func-calls.ll
View File

@ -5,21 +5,21 @@
%myStruct = type { i64 , i8, i32 }
@var8 = global i8 0
@var8_2 = global i8 0
@var32 = global i32 0
@var64 = global i64 0
@var128 = global i128 0
@varfloat = global float 0.0
@varfloat_2 = global float 0.0
@vardouble = global double 0.0
@varstruct = global %myStruct zeroinitializer
@varsmallstruct = global [2 x i64] zeroinitializer
@var8 = dso_local global i8 0
@var8_2 = dso_local global i8 0
@var32 = dso_local global i32 0
@var64 = dso_local global i64 0
@var128 = dso_local global i128 0
@varfloat = dso_local global float 0.0
@varfloat_2 = dso_local global float 0.0
@vardouble = dso_local global double 0.0
@varstruct = dso_local global %myStruct zeroinitializer
@varsmallstruct = dso_local global [2 x i64] zeroinitializer
declare void @take_i8s(i8 %val1, i8 %val2)
declare void @take_floats(float %val1, float %val2)
define void @simple_args() {
define dso_local void @simple_args() {
; CHECK-LABEL: simple_args:
%char1 = load i8, i8* @var8
%char2 = load i8, i8* @var8_2
@ -45,7 +45,7 @@ declare double @return_double()
declare [2 x i64] @return_smallstruct()
declare void @return_large_struct(%myStruct* sret(%myStruct) %retval)
define void @simple_rets() {
define dso_local void @simple_rets() {
; CHECK-LABEL: simple_rets:
%int = call i32 @return_int()
@ -80,7 +80,7 @@ declare void @stacked_fpu(float %var0, double %var1, float %var2, float %var3,
float %var4, float %var5, float %var6, float %var7,
float %var8)
define void @check_stack_args() {
define dso_local void @check_stack_args() {
; CHECK-LABEL: check_stack_args:
call i32 @struct_on_stack(i8 0, i16 12, i32 42, i64 99, i128 1,
i32* @var32, %myStruct* byval(%myStruct) @varstruct,
@ -120,7 +120,7 @@ declare void @check_i128_stackalign(i32 %val0, i32 %val1, i32 %val2, i32 %val3,
declare void @check_i128_regalign(i32 %val0, i128 %val1)
define void @check_i128_align() {
define dso_local void @check_i128_align() {
; CHECK-LABEL: check_i128_align:
%val = load i128, i128* @var128
call void @check_i128_stackalign(i32 0, i32 1, i32 2, i32 3,
@ -146,9 +146,9 @@ define void @check_i128_align() {
ret void
}
@fptr = global void()* null
@fptr = dso_local global void()* null
define void @check_indirect_call() {
define dso_local void @check_indirect_call() {
; CHECK-LABEL: check_indirect_call:
%func = load void()*, void()** @fptr
call void %func()

20
llvm/test/CodeGen/AArch64/global-alignment.ll
View File

@ -1,11 +1,11 @@
; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs -o - %s | FileCheck %s
@var32 = global [3 x i32] zeroinitializer
@var64 = global [3 x i64] zeroinitializer
@var32_align64 = global [3 x i32] zeroinitializer, align 8
@alias = alias [3 x i32], [3 x i32]* @var32_align64
@var32 = dso_local global [3 x i32] zeroinitializer
@var64 = dso_local global [3 x i64] zeroinitializer
@var32_align64 = dso_local global [3 x i32] zeroinitializer, align 8
@alias = dso_local alias [3 x i32], [3 x i32]* @var32_align64
define i64 @test_align32() {
define dso_local i64 @test_align32() {
; CHECK-LABEL: test_align32:
%addr = bitcast [3 x i32]* @var32 to i64*
@ -19,7 +19,7 @@ define i64 @test_align32() {
ret i64 %val
}
define i64 @test_align64() {
define dso_local i64 @test_align64() {
; CHECK-LABEL: test_align64:
%addr = bitcast [3 x i64]* @var64 to i64*
@ -33,7 +33,7 @@ define i64 @test_align64() {
ret i64 %val
}
define i64 @test_var32_align64() {
define dso_local i64 @test_var32_align64() {
; CHECK-LABEL: test_var32_align64:
%addr = bitcast [3 x i32]* @var32_align64 to i64*
@ -47,7 +47,7 @@ define i64 @test_var32_align64() {
ret i64 %val
}
define i64 @test_var32_alias() {
define dso_local i64 @test_var32_alias() {
; CHECK-LABEL: test_var32_alias:
%addr = bitcast [3 x i32]* @alias to i64*
@ -62,7 +62,7 @@ define i64 @test_var32_alias() {
@yet_another_var = external dso_local global {i32, i32}
define i64 @test_yet_another_var() {
define dso_local i64 @test_yet_another_var() {
; CHECK-LABEL: test_yet_another_var:
; @yet_another_var has a preferred alignment of 8, but that's not enough if
@ -75,7 +75,7 @@ define i64 @test_yet_another_var() {
ret i64 %val
}
define i64()* @test_functions() {
define dso_local i64()* @test_functions() {
; CHECK-LABEL: test_functions:
ret i64()* @test_yet_another_var
; CHECK: adrp [[HIBITS:x[0-9]+]], test_yet_another_var

10
llvm/test/CodeGen/AArch64/global-merge-2.ll
View File

@ -2,11 +2,11 @@
; RUN: llc %s -mtriple=aarch64-linux-gnuabi -aarch64-enable-global-merge -global-merge-on-external -o - | FileCheck %s
; RUN: llc %s -mtriple=aarch64-apple-ios -aarch64-enable-global-merge -global-merge-on-external -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS
@x = global i32 0, align 4
@y = global i32 0, align 4
@z = global i32 0, align 4
@x = dso_local global i32 0, align 4
@y = dso_local global i32 0, align 4
@z = dso_local global i32 0, align 4
define void @f1(i32 %a1, i32 %a2) {
define dso_local void @f1(i32 %a1, i32 %a2) {
;CHECK-APPLE-IOS-LABEL: _f1:
;CHECK-APPLE-IOS-NOT: adrp
;CHECK-APPLE-IOS: adrp x8, __MergedGlobals_x@PAGE
@ -17,7 +17,7 @@ define void @f1(i32 %a1, i32 %a2) {
ret void
}
define void @g1(i32 %a1, i32 %a2) {
define dso_local void @g1(i32 %a1, i32 %a2) {
;CHECK-APPLE-IOS-LABEL: _g1:
;CHECK-APPLE-IOS: adrp x8, __MergedGlobals_x@PAGE
;CHECK-APPLE-IOS: add x8, x8, __MergedGlobals_x@PAGEOFF

6
llvm/test/CodeGen/AArch64/global-merge-3.ll
View File

@ -2,11 +2,11 @@
; RUN: llc %s -mtriple=aarch64-linux-gnuabi -aarch64-enable-global-merge -global-merge-on-external -disable-post-ra -o - | FileCheck %s
; RUN: llc %s -mtriple=aarch64-apple-ios -aarch64-enable-global-merge -global-merge-on-external -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS
@x = global [100 x i32] zeroinitializer, align 1
@y = global [100 x i32] zeroinitializer, align 1
@x = dso_local global [100 x i32] zeroinitializer, align 1
@y = dso_local global [100 x i32] zeroinitializer, align 1
@z = internal global i32 1, align 4
define void @f1(i32 %a1, i32 %a2, i32 %a3) {
define dso_local void @f1(i32 %a1, i32 %a2, i32 %a3) {
;CHECK-APPLE-IOS: adrp x8, __MergedGlobals_x@PAGE+12
;CHECK-APPLE-IOS-NOT: adrp
;CHECK-APPLE-IOS: add x8, x8, __MergedGlobals_x@PAGEOFF+12

10
llvm/test/CodeGen/AArch64/i1-contents.ll
View File

@ -1,11 +1,11 @@
; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s
%big = type i32
@var = global %big 0
@var = dso_local global %big 0
; AAPCS: low 8 bits of %in (== w0) will be either 0 or 1. Need to extend to
; 32-bits.
define void @consume_i1_arg(i1 %in) {
define dso_local void @consume_i1_arg(i1 %in) {
; CHECK-LABEL: consume_i1_arg:
; CHECK: and [[BOOL32:w[0-9]+]], w0, #{{0x1|0xff}}
; CHECK: str [[BOOL32]], [{{x[0-9]+}}, :lo12:var]
@ -16,7 +16,7 @@ define void @consume_i1_arg(i1 %in) {
; AAPCS: low 8 bits of %val1 (== w0) will be either 0 or 1. Need to extend to
; 32-bits (doesn't really matter if it's from 1 or 8 bits).
define void @consume_i1_ret() {
define dso_local void @consume_i1_ret() {
; CHECK-LABEL: consume_i1_ret:
; CHECK: bl produce_i1_ret
; CHECK: and [[BOOL32:w[0-9]+]], w0, #{{0x1|0xff}}
@ -28,7 +28,7 @@ define void @consume_i1_ret() {
}
; AAPCS: low 8 bits of w0 must be either 0 or 1. Need to mask them off.
define i1 @produce_i1_ret() {
define dso_local i1 @produce_i1_ret() {
; CHECK-LABEL: produce_i1_ret:
; CHECK: ldr [[VAR32:w[0-9]+]], [{{x[0-9]+}}, :lo12:var]
; CHECK: and w0, [[VAR32]], #{{0x1|0xff}}
@ -37,7 +37,7 @@ define i1 @produce_i1_ret() {
ret i1 %val1
}
define void @produce_i1_arg() {
define dso_local void @produce_i1_arg() {
; CHECK-LABEL: produce_i1_arg:
; CHECK: ldr [[VAR32:w[0-9]+]], [{{x[0-9]+}}, :lo12:var]
; CHECK: and w0, [[VAR32]], #{{0x1|0xff}}

14
llvm/test/CodeGen/AArch64/irg_sp_tagp.ll
View File

@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=aarch64 -mattr=+mte | FileCheck %s
define i8* @small_alloca() {
define dso_local i8* @small_alloca() {
entry:
; CHECK-LABEL: small_alloca:
; CHECK: irg x0, sp{{$}}
@ -11,12 +11,12 @@ entry:
ret i8* %q1
}
@sink = global i8* null, align 8
@sink = dso_local global i8* null, align 8
; Check that IRG is pinned to %b because the store instruction needs
; the address in a non-fixed physical register and can benefit from it
; being equal to the base tagged pointer.
define i8* @small_allocas() {
define dso_local i8* @small_allocas() {
entry:
; CHECK-LABEL: small_allocas:
; CHECK: irg [[R:x[0-9]+]], sp{{$}}
@ -33,7 +33,7 @@ entry:
}
; Two large allocas. One's offset overflows addg immediate.
define void @huge_allocas() {
define dso_local void @huge_allocas() {
entry:
; CHECK-LABEL: huge_allocas:
; CHECK: irg x1, sp{{$}}
@ -51,7 +51,7 @@ entry:
; Realigned stack frame. IRG uses value of SP after realignment,
; ADDG for the first stack allocation has offset 0.
define void @realign() {
define dso_local void @realign() {
entry:
; CHECK-LABEL: realign:
; CHECK: mov x29, sp
@ -67,7 +67,7 @@ entry:
; With a dynamic alloca, IRG has to use FP with non-zero offset.
; ADDG offset for the single static alloca is still zero.
define void @dynamic_alloca(i64 %size) {
define dso_local void @dynamic_alloca(i64 %size) {
entry:
; CHECK-LABEL: dynamic_alloca:
; CHECK: sub x1, x29, #[[OFS:[0-9]+]]
@ -86,7 +86,7 @@ entry:
; After initial realignment, generate the base pointer.
; IRG uses the base pointer w/o offset.
; Offsets for tagged and untagged pointers to the same alloca match.
define void @dynamic_alloca_and_realign(i64 %size) {
define dso_local void @dynamic_alloca_and_realign(i64 %size) {
entryz:
; CHECK-LABEL: dynamic_alloca_and_realign:
; CHECK: and sp, x{{.*}}, #0xffffffffffffffc0

24
llvm/test/CodeGen/AArch64/ldst-unscaledimm.ll
View File

@ -1,17 +1,17 @@
; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
@var_8bit = global i8 0
@var_16bit = global i16 0
@var_32bit = global i32 0
@var_64bit = global i64 0
@var_8bit = dso_local global i8 0
@var_16bit = dso_local global i16 0
@var_32bit = dso_local global i32 0
@var_64bit = dso_local global i64 0
@var_float = global float 0.0
@var_double = global double 0.0
@var_float = dso_local global float 0.0
@var_double = dso_local global double 0.0
@varptr = global i8* null
@varptr = dso_local global i8* null
define void @ldst_8bit() {
define dso_local void @ldst_8bit() {
; CHECK-LABEL: ldst_8bit:
; No architectural support for loads to 16-bit or 8-bit since we
@ -72,7 +72,7 @@ define void @ldst_8bit() {
ret void
}
define void @ldst_16bit() {
define dso_local void @ldst_16bit() {
; CHECK-LABEL: ldst_16bit:
; No architectural support for loads to 16-bit or 16-bit since we
@ -140,7 +140,7 @@ define void @ldst_16bit() {
ret void
}
define void @ldst_32bit() {
define dso_local void @ldst_32bit() {
; CHECK-LABEL: ldst_32bit:
%addr_8bit = load i8*, i8** @varptr
@ -186,7 +186,7 @@ define void @ldst_32bit() {
ret void
}
define void @ldst_float() {
define dso_local void @ldst_float() {
; CHECK-LABEL: ldst_float:
%addr_8bit = load i8*, i8** @varptr
@ -204,7 +204,7 @@ define void @ldst_float() {
ret void
}
define void @ldst_double() {
define dso_local void @ldst_double() {
; CHECK-LABEL: ldst_double:
%addr_8bit = load i8*, i8** @varptr

32
llvm/test/CodeGen/AArch64/ldst-unsignedimm.ll
View File

@ -1,15 +1,15 @@
; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
@var_8bit = global i8 0
@var_16bit = global i16 0
@var_32bit = global i32 0
@var_64bit = global i64 0
@var_8bit = dso_local global i8 0
@var_16bit = dso_local global i16 0
@var_32bit = dso_local global i32 0
@var_64bit = dso_local global i64 0
@var_float = global float 0.0
@var_double = global double 0.0
@var_float = dso_local global float 0.0
@var_double = dso_local global double 0.0
define void @ldst_8bit() {
define dso_local void @ldst_8bit() {
; CHECK-LABEL: ldst_8bit:
; No architectural support for loads to 16-bit or 8-bit since we
@ -63,7 +63,7 @@ define void @ldst_8bit() {
ret void
}
define void @ldst_16bit() {
define dso_local void @ldst_16bit() {
; CHECK-LABEL: ldst_16bit:
; No architectural support for load volatiles to 16-bit promote i16 during
@ -117,7 +117,7 @@ define void @ldst_16bit() {
ret void
}
define void @ldst_32bit() {
define dso_local void @ldst_32bit() {
; CHECK-LABEL: ldst_32bit:
; Straight 32-bit load/store
@ -151,17 +151,17 @@ define void @ldst_32bit() {
ret void
}
@arr8 = global i8* null
@arr16 = global i16* null
@arr32 = global i32* null
@arr64 = global i64* null
@arr8 = dso_local global i8* null
@arr16 = dso_local global i16* null
@arr32 = dso_local global i32* null
@arr64 = dso_local global i64* null
; Now check that our selection copes with accesses more complex than a
; single symbol. Permitted offsets should be folded into the loads and
; stores. Since all forms use the same Operand it's only necessary to
; check the various access-sizes involved.
define void @ldst_complex_offsets() {
define dso_local void @ldst_complex_offsets() {
; CHECK: ldst_complex_offsets
%arr8_addr = load volatile i8*, i8** @arr8
; CHECK: adrp {{x[0-9]+}}, arr8
@ -225,7 +225,7 @@ define void @ldst_complex_offsets() {
ret void
}
define void @ldst_float() {
define dso_local void @ldst_float() {
; CHECK-LABEL: ldst_float:
%valfp = load volatile float, float* @var_float
@ -240,7 +240,7 @@ define void @ldst_float() {
ret void
}
define void @ldst_double() {
define dso_local void @ldst_double() {
; CHECK-LABEL: ldst_double:
%valfp = load volatile double, double* @var_double

6
llvm/test/CodeGen/AArch64/literal_pools_float.ll
View File

@ -5,10 +5,10 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -code-model=large -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP-LARGE %s
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-none-eabi -code-model=tiny -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP-TINY %s
@varfloat = global float 0.0
@vardouble = global double 0.0
@varfloat = dso_local global float 0.0
@vardouble = dso_local global double 0.0
define void @floating_lits() {
define dso_local void @floating_lits() {
; CHECK-LABEL: floating_lits:
%floatval = load float, float* @varfloat

32
llvm/test/CodeGen/AArch64/misched-fusion-addr.ll
View File

@ -5,17 +5,17 @@
target triple = "aarch64-unknown"
@var_8bit = global i8 0
@var_16bit = global i16 0
@var_32bit = global i32 0
@var_64bit = global i64 0
@var_128bit = global i128 0
@var_half = global half 0.0
@var_float = global float 0.0
@var_double = global double 0.0
@var_double2 = global <2 x double> <double 0.0, double 0.0>
@var_8bit = dso_local global i8 0
@var_16bit = dso_local global i16 0
@var_32bit = dso_local global i32 0
@var_64bit = dso_local global i64 0
@var_128bit = dso_local global i128 0
@var_half = dso_local global half 0.0
@var_float = dso_local global float 0.0
@var_double = dso_local global double 0.0
@var_double2 = dso_local global <2 x double> <double 0.0, double 0.0>
define void @ldst_8bit() {
define dso_local void @ldst_8bit() {
%val8 = load volatile i8, i8* @var_8bit
%ext = zext i8 %val8 to i64
%add = add i64 %ext, 1
@ -30,7 +30,7 @@ define void @ldst_8bit() {
; CHECK-NEXT: strh {{w[0-9]+}}, {{\[}}[[RH]], {{#?}}:lo12:var_16bit{{\]}}
}
define void @ldst_16bit() {
define dso_local void @ldst_16bit() {
%val16 = load volatile i16, i16* @var_16bit
%ext = zext i16 %val16 to i64
%add = add i64 %ext, 1
@ -45,7 +45,7 @@ define void @ldst_16bit() {
; CHECK-NEXT: str {{w[0-9]+}}, {{\[}}[[RW]], {{#?}}:lo12:var_32bit{{\]}}
}
define void @ldst_32bit() {
define dso_local void @ldst_32bit() {
%val32 = load volatile i32, i32* @var_32bit
%ext = zext i32 %val32 to i64
%val64 = add i64 %ext, 1
@ -59,7 +59,7 @@ define void @ldst_32bit() {
; CHECK-NEXT: str {{x[0-9]+}}, {{\[}}[[RL]], {{#?}}:lo12:var_64bit{{\]}}
}
define void @ldst_64bit() {
define dso_local void @ldst_64bit() {
%val64 = load volatile i64, i64* @var_64bit
%ext = zext i64 %val64 to i128
%val128 = add i128 %ext, 1
@ -73,7 +73,7 @@ define void @ldst_64bit() {
; CHECK-NEXT: add {{x[0-9]+}}, [[RQ]], {{#?}}:lo12:var_128bit
}
define void @ldst_half() {
define dso_local void @ldst_half() {
%valh = load volatile half, half* @var_half
%valf = fpext half %valh to float
store volatile float %valf, float* @var_float
@ -86,7 +86,7 @@ define void @ldst_half() {
; CHECK-NEXT: str {{s[0-9]+}}, {{\[}}[[RF]], {{#?}}:lo12:var_float{{\]}}
}
define void @ldst_float() {
define dso_local void @ldst_float() {
%valf = load volatile float, float* @var_float
%vald = fpext float %valf to double
store volatile double %vald, double* @var_double
@ -99,7 +99,7 @@ define void @ldst_float() {
; CHECK-NEXT: str {{d[0-9]+}}, {{\[}}[[RD]], {{#?}}:lo12:var_double{{\]}}
}
define void @ldst_double() {
define dso_local void @ldst_double() {
%valf = load volatile float, float* @var_float
%vale = fpext float %valf to double
%vald = load volatile double, double* @var_double

8
llvm/test/CodeGen/AArch64/misched-fusion-lit.ll
View File

@ -7,7 +7,7 @@
@g = common local_unnamed_addr global i8* null, align 8
define i8* @litp(i32 %a, i32 %b) {
define dso_local i8* @litp(i32 %a, i32 %b) {
entry:
%add = add nsw i32 %b, %a
%idx.ext = sext i32 %add to i64
@ -21,7 +21,7 @@ entry:
; CHECKFUSE-NEXT: add {{x[0-9]+}}, [[R]], :lo12:litp
}
define i32 @liti(i32 %a, i32 %b) {
define dso_local i32 @liti(i32 %a, i32 %b) {
entry:
%add = add i32 %a, -262095121
%add1 = add i32 %add, %b
@ -34,7 +34,7 @@ entry:
}
; Function Attrs: norecurse nounwind readnone
define i64 @litl(i64 %a, i64 %b) {
define dso_local i64 @litl(i64 %a, i64 %b) {
entry:
%add = add i64 %a, 2208998440489107183
%add1 = add i64 %add, %b
@ -49,7 +49,7 @@ entry:
}
; Function Attrs: norecurse nounwind readnone
define double @litf() {
define dso_local double @litf() {
entry:
ret double 0x400921FB54442D18

4
llvm/test/CodeGen/AArch64/movw-shift-encoding.ll
View File

@ -1,11 +1,11 @@
; RUN: llc -mtriple=aarch64-linux-gnu < %s -show-mc-encoding -code-model=large | FileCheck %s
@var = global i32 0
@var = dso_local global i32 0
; CodeGen should ensure that the correct shift bits are set, because the linker
; isn't going to!
define i32* @get_var() {
define dso_local i32* @get_var() {
ret i32* @var
; CHECK: movz x0, #:abs_g0_nc:var // encoding: [0bAAA00000,A,0b100AAAAA,0xd2]

4
llvm/test/CodeGen/AArch64/pie.ll
View File

@ -1,8 +1,8 @@
; RUN: llc -mtriple aarch64-pc-linux -relocation-model=pic < %s | FileCheck %s
@g1 = global i32 42
@g1 = dso_local global i32 42
define i32* @get_g1() {
define dso_local i32* @get_g1() {
; CHECK: get_g1:
; CHECK: adrp x0, g1
; CHECK-NEXT: add x0, x0, :lo12:g1

18
llvm/test/CodeGen/AArch64/sibling-call.ll
View File

@ -4,7 +4,7 @@ declare void @callee_stack0()
declare void @callee_stack8([8 x i64], i64)
declare void @callee_stack16([8 x i64], i64, i64)
define void @caller_to0_from0() nounwind {
define dso_local void @caller_to0_from0() nounwind {
; CHECK-LABEL: caller_to0_from0:
; CHECK-NEXT: // %bb.
tail call void @callee_stack0()
@ -12,7 +12,7 @@ define void @caller_to0_from0() nounwind {
; CHECK-NEXT: b callee_stack0
}
define void @caller_to0_from8([8 x i64], i64) nounwind{
define dso_local void @caller_to0_from8([8 x i64], i64) nounwind{
; CHECK-LABEL: caller_to0_from8:
; CHECK-NEXT: // %bb.
@ -21,7 +21,7 @@ define void @caller_to0_from8([8 x i64], i64) nounwind{
; CHECK-NEXT: b callee_stack0
}
define void @caller_to8_from0() {
define dso_local void @caller_to8_from0() {
; CHECK-LABEL: caller_to8_from0:
; Caller isn't going to clean up any extra stack we allocate, so it
@ -31,7 +31,7 @@ define void @caller_to8_from0() {
; CHECK: bl callee_stack8
}
define void @caller_to8_from8([8 x i64], i64 %a) {
define dso_local void @caller_to8_from8([8 x i64], i64 %a) {
; CHECK-LABEL: caller_to8_from8:
; CHECK-NOT: sub sp, sp,
@ -42,7 +42,7 @@ define void @caller_to8_from8([8 x i64], i64 %a) {
; CHECK-NEXT: b callee_stack8
}
define void @caller_to16_from8([8 x i64], i64 %a) {
define dso_local void @caller_to16_from8([8 x i64], i64 %a) {
; CHECK-LABEL: caller_to16_from8:
; Shouldn't be a tail call: we can't use SP+8 because our caller might
@ -53,7 +53,7 @@ define void @caller_to16_from8([8 x i64], i64 %a) {
ret void
}
define void @caller_to8_from24([8 x i64], i64 %a, i64 %b, i64 %c) {
define dso_local void @caller_to8_from24([8 x i64], i64 %a, i64 %b, i64 %c) {
; CHECK-LABEL: caller_to8_from24:
; CHECK-NOT: sub sp, sp
@ -64,7 +64,7 @@ define void @caller_to8_from24([8 x i64], i64 %a, i64 %b, i64 %c) {
; CHECK-NEXT: b callee_stack8
}
define void @caller_to16_from16([8 x i64], i64 %a, i64 %b) {
define dso_local void @caller_to16_from16([8 x i64], i64 %a, i64 %b) {
; CHECK-LABEL: caller_to16_from16:
; CHECK-NOT: sub sp, sp,
@ -82,9 +82,9 @@ define void @caller_to16_from16([8 x i64], i64 %a, i64 %b) {
; CHECK: b callee_stack16
}
@func = global void(i32)* null
@func = dso_local global void(i32)* null
define void @indirect_tail() {
define dso_local void @indirect_tail() {
; CHECK-LABEL: indirect_tail:
; CHECK-NOT: sub sp, sp

31
llvm/test/CodeGen/AArch64/tiny_model.ll → llvm/test/CodeGen/AArch64/tiny-model-pic.ll
View File

@ -1,10 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-linux-gnu -code-model=tiny < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-linux-gnu -code-model=tiny -fast-isel < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-linux-gnu -code-model=tiny -global-isel < %s | FileCheck %s --check-prefix=CHECK-GLOBISEL
; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-linux-gnu -code-model=tiny -relocation-model=pic < %s | FileCheck %s --check-prefix=CHECK-PIC
; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-linux-gnu -code-model=tiny -relocation-model=pic -fast-isel < %s | FileCheck %s --check-prefix=CHECK-PIC
; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-linux-gnu -code-model=tiny -relocation-model=pic -global-isel < %s | FileCheck %s --check-prefix=CHECK-PIC-GLOBISEL
; RUN: llc -verify-machineinstrs -mtriple=aarch64 -code-model=tiny -relocation-model=pic < %s | FileCheck %s --check-prefix=CHECK-PIC
; RUN: llc -verify-machineinstrs -mtriple=aarch64 -code-model=tiny -relocation-model=pic -fast-isel < %s | FileCheck %s --check-prefix=CHECK-PIC
; RUN: llc -verify-machineinstrs -mtriple=aarch64 -code-model=tiny -relocation-model=pic -global-isel < %s | FileCheck %s --check-prefix=CHECK-PIC-GLOBISEL
; Note fast-isel tests here will fall back to isel
@ -12,7 +9,7 @@
@dst = external global [65536 x i8], align 1
@ptr = external local_unnamed_addr global i8*, align 8
define void @foo1() {
define dso_preemptable void @foo1() {
; CHECK-LABEL: foo1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr x8, :got:src
@ -50,7 +47,7 @@ entry:
ret void
}
define void @foo2() {
define dso_preemptable void @foo2() {
; CHECK-LABEL: foo2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr x8, :got:ptr
@ -83,7 +80,7 @@ entry:
ret void
}
define void @foo3() {
define dso_preemptable void @foo3() {
; FIXME: Needn't adr ptr
;
; CHECK-LABEL: foo3:
@ -132,7 +129,7 @@ entry:
@ldst = internal global i8 0, align 4
@lptr = internal global i8* null, align 8
define void @bar1() {
define dso_preemptable void @bar1() {
; CHECK-LABEL: bar1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adr x8, lsrc
@ -170,7 +167,7 @@ entry:
ret void
}
define void @bar2() {
define dso_preemptable void @bar2() {
; CHECK-LABEL: bar2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adr x8, lptr
@ -203,7 +200,7 @@ entry:
ret void
}
define void @bar3() {
define dso_preemptable void @bar3() {
; FIXME: Needn't adr lptr
;
; CHECK-LABEL: bar3:
@ -250,7 +247,7 @@ entry:
@lbsrc = internal global [65536 x i8] zeroinitializer, align 4
@lbdst = internal global [65536 x i8] zeroinitializer, align 4
define void @baz1() {
define dso_preemptable void @baz1() {
; CHECK-LABEL: baz1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adr x8, lbsrc
@ -288,7 +285,7 @@ entry:
ret void
}
define void @baz2() {
define dso_preemptable void @baz2() {
; CHECK-LABEL: baz2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adr x8, lptr
@ -321,7 +318,7 @@ entry:
ret void
}
define void @baz3() {
define dso_preemptable void @baz3() {
; FIXME: Needn't adr lptr
;
; CHECK-LABEL: baz3:
@ -367,7 +364,7 @@ entry:
declare void @func(...)
define i8* @externfuncaddr() {
define dso_preemptable i8* @externfuncaddr() {
; CHECK-LABEL: externfuncaddr:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr x0, :got:func
@ -391,7 +388,7 @@ entry:
ret i8* bitcast (void (...)* @func to i8*)
}
define i8* @localfuncaddr() {
define dso_preemptable i8* @localfuncaddr() {
; CHECK-LABEL: localfuncaddr:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adr x0, externfuncaddr

251
llvm/test/CodeGen/AArch64/tiny-model-static.ll Normal file
View File

@ -0,0 +1,251 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-linux-gnu -code-model=tiny < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-linux-gnu -code-model=tiny -fast-isel < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-linux-gnu -code-model=tiny -global-isel < %s | FileCheck %s --check-prefix=CHECK-GLOBISEL
; Note fast-isel tests here will fall back to isel
@src = external local_unnamed_addr global [65536 x i8], align 1
@dst = external global [65536 x i8], align 1
@ptr = external local_unnamed_addr global i8*, align 8
define dso_local void @foo1() {
; CHECK-LABEL: foo1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr x8, :got:src
; CHECK-NEXT: ldrb w8, [x8]
; CHECK-NEXT: ldr x9, :got:dst
; CHECK-NEXT: strb w8, [x9]
; CHECK-NEXT: ret
;
; CHECK-GLOBISEL-LABEL: foo1:
; CHECK-GLOBISEL: // %bb.0: // %entry
; CHECK-GLOBISEL-NEXT: ldr x8, :got:src
; CHECK-GLOBISEL-NEXT: ldrb w8, [x8]
; CHECK-GLOBISEL-NEXT: ldr x9, :got:dst
; CHECK-GLOBISEL-NEXT: strb w8, [x9]
; CHECK-GLOBISEL-NEXT: ret
entry:
%0 = load i8, i8* getelementptr inbounds ([65536 x i8], [65536 x i8]* @src, i64 0, i64 0), align 1
store i8 %0, i8* getelementptr inbounds ([65536 x i8], [65536 x i8]* @dst, i64 0, i64 0), align 1
ret void
}
define dso_local void @foo2() {
; CHECK-LABEL: foo2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr x8, :got:ptr
; CHECK-NEXT: ldr x9, :got:dst
; CHECK-NEXT: str x9, [x8]
; CHECK-NEXT: ret
;
; CHECK-GLOBISEL-LABEL: foo2:
; CHECK-GLOBISEL: // %bb.0: // %entry
; CHECK-GLOBISEL-NEXT: ldr x8, :got:ptr
; CHECK-GLOBISEL-NEXT: ldr x9, :got:dst
; CHECK-GLOBISEL-NEXT: str x9, [x8]
; CHECK-GLOBISEL-NEXT: ret
entry:
store i8* getelementptr inbounds ([65536 x i8], [65536 x i8]* @dst, i64 0, i64 0), i8** @ptr, align 8
ret void
}
define dso_local void @foo3() {
; FIXME: Needn't adr ptr
;
; CHECK-LABEL: foo3:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr x8, :got:src
; CHECK-NEXT: ldr x9, :got:ptr
; CHECK-NEXT: ldrb w8, [x8]
; CHECK-NEXT: ldr x9, [x9]
; CHECK-NEXT: strb w8, [x9]
; CHECK-NEXT: ret
;
; CHECK-GLOBISEL-LABEL: foo3:
; CHECK-GLOBISEL: // %bb.0: // %entry
; CHECK-GLOBISEL-NEXT: ldr x8, :got:src
; CHECK-GLOBISEL-NEXT: ldr x9, :got:ptr
; CHECK-GLOBISEL-NEXT: ldrb w8, [x8]
; CHECK-GLOBISEL-NEXT: ldr x9, [x9]
; CHECK-GLOBISEL-NEXT: strb w8, [x9]
; CHECK-GLOBISEL-NEXT: ret
entry:
%0 = load i8, i8* getelementptr inbounds ([65536 x i8], [65536 x i8]* @src, i64 0, i64 0), align 1
%1 = load i8*, i8** @ptr, align 8
store i8 %0, i8* %1, align 1
ret void
}
@lsrc = internal global i8 0, align 4
@ldst = internal global i8 0, align 4
@lptr = internal global i8* null, align 8
define dso_local void @bar1() {
; CHECK-LABEL: bar1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adr x8, lsrc
; CHECK-NEXT: ldrb w8, [x8]
; CHECK-NEXT: adr x9, ldst
; CHECK-NEXT: strb w8, [x9]
; CHECK-NEXT: ret
;
; CHECK-GLOBISEL-LABEL: bar1:
; CHECK-GLOBISEL: // %bb.0: // %entry
; CHECK-GLOBISEL-NEXT: adr x8, lsrc
; CHECK-GLOBISEL-NEXT: ldrb w8, [x8]
; CHECK-GLOBISEL-NEXT: adr x9, ldst
; CHECK-GLOBISEL-NEXT: strb w8, [x9]
; CHECK-GLOBISEL-NEXT: ret
entry:
%0 = load i8, i8* @lsrc, align 4
store i8 %0, i8* @ldst, align 4
ret void
}
define dso_local void @bar2() {
; CHECK-LABEL: bar2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adr x8, lptr
; CHECK-NEXT: adr x9, ldst
; CHECK-NEXT: str x9, [x8]
; CHECK-NEXT: ret
;
; CHECK-GLOBISEL-LABEL: bar2:
; CHECK-GLOBISEL: // %bb.0: // %entry
; CHECK-GLOBISEL-NEXT: adr x8, lptr
; CHECK-GLOBISEL-NEXT: adr x9, ldst
; CHECK-GLOBISEL-NEXT: str x9, [x8]
; CHECK-GLOBISEL-NEXT: ret
entry:
store i8* @ldst, i8** @lptr, align 8
ret void
}
define dso_local void @bar3() {
; FIXME: Needn't adr lptr
;
; CHECK-LABEL: bar3:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adr x8, lsrc
; CHECK-NEXT: ldrb w8, [x8]
; CHECK-NEXT: ldr x9, lptr
; CHECK-NEXT: strb w8, [x9]
; CHECK-NEXT: ret
;
; CHECK-GLOBISEL-LABEL: bar3:
; CHECK-GLOBISEL: // %bb.0: // %entry
; CHECK-GLOBISEL-NEXT: adr x8, lsrc
; CHECK-GLOBISEL-NEXT: adr x9, lptr
; CHECK-GLOBISEL-NEXT: ldrb w8, [x8]
; CHECK-GLOBISEL-NEXT: ldr x9, [x9]
; CHECK-GLOBISEL-NEXT: strb w8, [x9]
; CHECK-GLOBISEL-NEXT: ret
entry:
%0 = load i8, i8* @lsrc, align 4
%1 = load i8*, i8** @lptr, align 8
store i8 %0, i8* %1, align 1
ret void
}
@lbsrc = internal global [65536 x i8] zeroinitializer, align 4
@lbdst = internal global [65536 x i8] zeroinitializer, align 4
define dso_local void @baz1() {
; CHECK-LABEL: baz1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adr x8, lbsrc
; CHECK-NEXT: ldrb w8, [x8]
; CHECK-NEXT: adr x9, lbdst
; CHECK-NEXT: strb w8, [x9]
; CHECK-NEXT: ret
;
; CHECK-GLOBISEL-LABEL: baz1:
; CHECK-GLOBISEL: // %bb.0: // %entry
; CHECK-GLOBISEL-NEXT: adr x8, lbsrc
; CHECK-GLOBISEL-NEXT: ldrb w8, [x8]
; CHECK-GLOBISEL-NEXT: adr x9, lbdst
; CHECK-GLOBISEL-NEXT: strb w8, [x9]
; CHECK-GLOBISEL-NEXT: ret
entry:
%0 = load i8, i8* getelementptr inbounds ([65536 x i8], [65536 x i8]* @lbsrc, i64 0, i64 0), align 4
store i8 %0, i8* getelementptr inbounds ([65536 x i8], [65536 x i8]* @lbdst, i64 0, i64 0), align 4
ret void
}
define dso_local void @baz2() {
; CHECK-LABEL: baz2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adr x8, lptr
; CHECK-NEXT: adr x9, lbdst
; CHECK-NEXT: str x9, [x8]
; CHECK-NEXT: ret
;
; CHECK-GLOBISEL-LABEL: baz2:
; CHECK-GLOBISEL: // %bb.0: // %entry
; CHECK-GLOBISEL-NEXT: adr x8, lptr
; CHECK-GLOBISEL-NEXT: adr x9, lbdst
; CHECK-GLOBISEL-NEXT: str x9, [x8]
; CHECK-GLOBISEL-NEXT: ret
entry:
store i8* getelementptr inbounds ([65536 x i8], [65536 x i8]* @lbdst, i64 0, i64 0), i8** @lptr, align 8
ret void
}
define dso_local void @baz3() {
; FIXME: Needn't adr lptr
;
; CHECK-LABEL: baz3:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adr x8, lbsrc
; CHECK-NEXT: ldrb w8, [x8]
; CHECK-NEXT: ldr x9, lptr
; CHECK-NEXT: strb w8, [x9]
; CHECK-NEXT: ret
;
; CHECK-GLOBISEL-LABEL: baz3:
; CHECK-GLOBISEL: // %bb.0: // %entry
; CHECK-GLOBISEL-NEXT: adr x8, lbsrc
; CHECK-GLOBISEL-NEXT: adr x9, lptr
; CHECK-GLOBISEL-NEXT: ldrb w8, [x8]
; CHECK-GLOBISEL-NEXT: ldr x9, [x9]
; CHECK-GLOBISEL-NEXT: strb w8, [x9]
; CHECK-GLOBISEL-NEXT: ret
entry:
%0 = load i8, i8* getelementptr inbounds ([65536 x i8], [65536 x i8]* @lbsrc, i64 0, i64 0), align 4
%1 = load i8*, i8** @lptr, align 8
store i8 %0, i8* %1, align 1
ret void
}
declare void @func(...)
define dso_local i8* @externfuncaddr() {
; CHECK-LABEL: externfuncaddr:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr x0, :got:func
; CHECK-NEXT: ret
;
; CHECK-GLOBISEL-LABEL: externfuncaddr:
; CHECK-GLOBISEL: // %bb.0: // %entry
; CHECK-GLOBISEL-NEXT: ldr x0, :got:func
; CHECK-GLOBISEL-NEXT: ret
entry:
ret i8* bitcast (void (...)* @func to i8*)
}
define dso_local i8* @localfuncaddr() {
; CHECK-LABEL: localfuncaddr:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adr x0, externfuncaddr
; CHECK-NEXT: ret
;
; CHECK-GLOBISEL-LABEL: localfuncaddr:
; CHECK-GLOBISEL: // %bb.0: // %entry
; CHECK-GLOBISEL-NEXT: adr x0, externfuncaddr
; CHECK-GLOBISEL-NEXT: ret
entry:
ret i8* bitcast (i8* ()* @externfuncaddr to i8*)
}

8
llvm/test/CodeGen/AArch64/zero-reg.ll
View File

@ -1,9 +1,9 @@
; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s
@var32 = global i32 0
@var64 = global i64 0
@var32 = dso_local global i32 0
@var64 = dso_local global i64 0
define void @test_zr() {
define dso_local void @test_zr() {
; CHECK-LABEL: test_zr:
store i32 0, i32* @var32
@ -15,7 +15,7 @@ define void @test_zr() {
; CHECK: ret
}
define void @test_sp(i32 %val) {
define dso_local void @test_sp(i32 %val) {
; CHECK-LABEL: test_sp:
; Important correctness point here is that LLVM doesn't try to use xzr