From 7b4ef068c6f5e1199f37b6f8a2881491b0cc09db Mon Sep 17 00:00:00 2001 From: Rafael Espindola Date: Tue, 21 Jun 2016 21:51:41 +0000 Subject: [PATCH] Delete more dead code. Found by gcc 6. llvm-svn: 273322 --- llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 32 ----- .../Target/AMDGPU/AMDILCFGStructurizer.cpp | 113 ------------------ .../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 46 ------- llvm/lib/Target/ARM/ARMFastISel.cpp | 37 ------ .../ARM/MCTargetDesc/ARMMCCodeEmitter.cpp | 40 ------- .../Hexagon/AsmParser/HexagonAsmParser.cpp | 13 -- .../lib/Target/Hexagon/HexagonBitSimplify.cpp | 13 -- .../lib/Target/Hexagon/HexagonOptAddrMode.cpp | 37 ------ .../Target/Mips/AsmParser/MipsAsmParser.cpp | 51 -------- 9 files changed, 382 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index a4a4f6f7cdcf..749642f170d4 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -74,8 +74,6 @@ private: bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector &); // Complex pattern selectors - bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2); - bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2); bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2); static bool checkType(const Value *ptr, unsigned int addrspace); @@ -236,36 +234,6 @@ const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N, } } -bool AMDGPUDAGToDAGISel::SelectADDRParam( - SDValue Addr, SDValue& R1, SDValue& R2) { - - if (Addr.getOpcode() == ISD::FrameIndex) { - if (FrameIndexSDNode *FIN = dyn_cast(Addr)) { - R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); - R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32); - } else { - R1 = Addr; - R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32); - } - } else if (Addr.getOpcode() == ISD::ADD) { - R1 = Addr.getOperand(0); - R2 = Addr.getOperand(1); - } else { - R1 = Addr; - R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32); - } - return true; -} - -bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) { - if (Addr.getOpcode() == ISD::TargetExternalSymbol || - Addr.getOpcode() == ISD::TargetGlobalAddress) { - return false; - } - return SelectADDRParam(Addr, R1, R2); -} - - bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) { if (Addr.getOpcode() == ISD::TargetExternalSymbol || Addr.getOpcode() == ISD::TargetGlobalAddress) { diff --git a/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp b/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp index 79cee08168b1..0d7c5989f040 100644 --- a/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp +++ b/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp @@ -50,8 +50,6 @@ STATISTIC(numSerialPatternMatch, "CFGStructurizer number of serial pattern " "matched"); STATISTIC(numIfPatternMatch, "CFGStructurizer number of if pattern " "matched"); -STATISTIC(numLoopcontPatternMatch, "CFGStructurizer number of loop-continue " - "pattern matched"); STATISTIC(numClonedBlock, "CFGStructurizer cloned blocks"); STATISTIC(numClonedInstr, "CFGStructurizer cloned instructions"); @@ -213,7 +211,6 @@ protected: int getSCCNum(MachineBasicBlock *MBB) const; MachineBasicBlock *getLoopLandInfo(MachineLoop *LoopRep) const; bool hasBackEdge(MachineBasicBlock *MBB) const; - static unsigned getLoopDepth(MachineLoop *LoopRep); bool isRetiredBlock(MachineBasicBlock *MBB) const; bool isActiveLoophead(MachineBasicBlock *MBB) const; PathToKind singlePathTo(MachineBasicBlock *SrcMBB, MachineBasicBlock *DstMBB, @@ -238,7 +235,6 @@ protected: void insertCondBranchBefore(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, int NewOpcode, int RegNum, const DebugLoc &DL); - void insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum); static int getBranchNzeroOpcode(int OldOpcode); static int getBranchZeroOpcode(int OldOpcode); static int getContinueNzeroOpcode(int OldOpcode); @@ -257,7 +253,6 @@ protected: /// instruction. Such move instruction "belong to" the loop backward-edge. MachineInstr *getLoopendBlockBranchInstr(MachineBasicBlock *MBB); static MachineInstr *getReturnInstr(MachineBasicBlock *MBB); - static MachineInstr *getContinueInstr(MachineBasicBlock *MBB); static bool isReturnBlock(MachineBasicBlock *MBB); static void cloneSuccessorList(MachineBasicBlock *DstMBB, MachineBasicBlock *SrcMBB) ; @@ -276,11 +271,7 @@ protected: int ifPatternMatch(MachineBasicBlock *MBB); int loopendPatternMatch(); int mergeLoop(MachineLoop *LoopRep); - int loopcontPatternMatch(MachineLoop *LoopRep, MachineBasicBlock *LoopHeader); - void handleLoopcontBlock(MachineBasicBlock *ContingMBB, - MachineLoop *ContingLoop, MachineBasicBlock *ContMBB, - MachineLoop *ContLoop); /// return true iff src1Blk->succ_size() == 0 && src1Blk and src2Blk are in /// the same loop with LoopLandInfo without explicitly keeping track of /// loopContBlks and loopBreakBlks, this is a method to get the information. @@ -337,9 +328,7 @@ protected: MachineBasicBlock *DstMBB, MachineBasicBlock::iterator I); void recordSccnum(MachineBasicBlock *MBB, int SCCNum); void retireBlock(MachineBasicBlock *MBB); - void setLoopLandBlock(MachineLoop *LoopRep, MachineBasicBlock *MBB = nullptr); - MachineBasicBlock *findNearestCommonPostDom(std::set&); /// This is work around solution for findNearestCommonDominator not available /// to post dom a proper fix should go to Dominators.h. MachineBasicBlock *findNearestCommonPostDom(MachineBasicBlock *MBB1, @@ -376,10 +365,6 @@ bool AMDGPUCFGStructurizer::hasBackEdge(MachineBasicBlock *MBB) const { return MBB->isSuccessor(LoopHeader); } -unsigned AMDGPUCFGStructurizer::getLoopDepth(MachineLoop *LoopRep) { - return LoopRep ? LoopRep->getLoopDepth() : 0; -} - bool AMDGPUCFGStructurizer::isRetiredBlock(MachineBasicBlock *MBB) const { MBBInfoMap::const_iterator It = BlockInfoMap.find(MBB); if (It == BlockInfoMap.end()) @@ -526,16 +511,6 @@ void AMDGPUCFGStructurizer::insertCondBranchBefore( SHOWNEWINSTR(NewInstr); } -void AMDGPUCFGStructurizer::insertCondBranchEnd(MachineBasicBlock *MBB, - int NewOpcode, int RegNum) { - MachineFunction *MF = MBB->getParent(); - MachineInstr *NewInstr = - MF->CreateMachineInstr(TII->get(NewOpcode), DebugLoc()); - MBB->push_back(NewInstr); - MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false); - SHOWNEWINSTR(NewInstr); -} - int AMDGPUCFGStructurizer::getBranchNzeroOpcode(int OldOpcode) { switch(OldOpcode) { case AMDGPU::JUMP_COND: @@ -665,16 +640,6 @@ MachineInstr *AMDGPUCFGStructurizer::getReturnInstr(MachineBasicBlock *MBB) { return nullptr; } -MachineInstr *AMDGPUCFGStructurizer::getContinueInstr(MachineBasicBlock *MBB) { - MachineBasicBlock::reverse_iterator It = MBB->rbegin(); - if (It != MBB->rend()) { - MachineInstr *MI = &(*It); - if (MI->getOpcode() == AMDGPU::CONTINUE) - return MI; - } - return nullptr; -} - bool AMDGPUCFGStructurizer::isReturnBlock(MachineBasicBlock *MBB) { MachineInstr *MI = getReturnInstr(MBB); bool IsReturn = (MBB->succ_size() == 0); @@ -1146,34 +1111,6 @@ int AMDGPUCFGStructurizer::mergeLoop(MachineLoop *LoopRep) { return 1; } -int AMDGPUCFGStructurizer::loopcontPatternMatch(MachineLoop *LoopRep, - MachineBasicBlock *LoopHeader) { - int NumCont = 0; - SmallVector ContMBB; - typedef GraphTraits > GTIM; - GTIM::ChildIteratorType It = GTIM::child_begin(LoopHeader), - E = GTIM::child_end(LoopHeader); - for (; It != E; ++It) { - MachineBasicBlock *MBB = *It; - if (LoopRep->contains(MBB)) { - handleLoopcontBlock(MBB, MLI->getLoopFor(MBB), - LoopHeader, LoopRep); - ContMBB.push_back(MBB); - ++NumCont; - } - } - - for (SmallVectorImpl::iterator It = ContMBB.begin(), - E = ContMBB.end(); It != E; ++It) { - (*It)->removeSuccessor(LoopHeader, true); - } - - numLoopcontPatternMatch += NumCont; - - return NumCont; -} - - bool AMDGPUCFGStructurizer::isSameloopDetachedContbreak( MachineBasicBlock *Src1MBB, MachineBasicBlock *Src2MBB) { if (Src1MBB->succ_size() == 0) { @@ -1469,17 +1406,6 @@ int AMDGPUCFGStructurizer::improveSimpleJumpintoIf(MachineBasicBlock *HeadMBB, return NumNewBlk; } -void AMDGPUCFGStructurizer::handleLoopcontBlock(MachineBasicBlock *ContingMBB, - MachineLoop *ContingLoop, MachineBasicBlock *ContMBB, - MachineLoop *ContLoop) { - DEBUG(dbgs() << "loopcontPattern cont = BB" << ContingMBB->getNumber() - << " header = BB" << ContMBB->getNumber() << "\n"; - dbgs() << "Trying to continue loop-depth = " - << getLoopDepth(ContLoop) - << " from loop-depth = " << getLoopDepth(ContingLoop) << "\n";); - settleLoopcontBlock(ContingMBB, ContMBB); -} - void AMDGPUCFGStructurizer::mergeSerialBlock(MachineBasicBlock *DstMBB, MachineBasicBlock *SrcMBB) { DEBUG( @@ -1810,22 +1736,6 @@ void AMDGPUCFGStructurizer::retireBlock(MachineBasicBlock *MBB) { && "can't retire block yet"); } -void AMDGPUCFGStructurizer::setLoopLandBlock(MachineLoop *loopRep, - MachineBasicBlock *MBB) { - MachineBasicBlock *&TheEntry = LLInfoMap[loopRep]; - if (!MBB) { - MBB = FuncRep->CreateMachineBasicBlock(); - FuncRep->push_back(MBB); //insert to function - SHOWNEWBLK(MBB, "DummyLandingBlock for loop without break: "); - } - TheEntry = MBB; - DEBUG( - dbgs() << "setLoopLandBlock loop-header = BB" - << loopRep->getHeader()->getNumber() - << " landing-block = BB" << MBB->getNumber() << "\n"; - ); -} - MachineBasicBlock * AMDGPUCFGStructurizer::findNearestCommonPostDom(MachineBasicBlock *MBB1, MachineBasicBlock *MBB2) { @@ -1857,29 +1767,6 @@ AMDGPUCFGStructurizer::findNearestCommonPostDom(MachineBasicBlock *MBB1, return nullptr; } -MachineBasicBlock * -AMDGPUCFGStructurizer::findNearestCommonPostDom( - std::set &MBBs) { - MachineBasicBlock *CommonDom; - std::set::const_iterator It = MBBs.begin(); - std::set::const_iterator E = MBBs.end(); - for (CommonDom = *It; It != E && CommonDom; ++It) { - MachineBasicBlock *MBB = *It; - if (MBB != CommonDom) - CommonDom = findNearestCommonPostDom(MBB, CommonDom); - } - - DEBUG( - dbgs() << "Common post dominator for exit blocks is "; - if (CommonDom) - dbgs() << "BB" << CommonDom->getNumber() << "\n"; - else - dbgs() << "NULL\n"; - ); - - return CommonDom; -} - char AMDGPUCFGStructurizer::ID = 0; } // end anonymous namespace diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 8541e6d5106b..df225f6ffcce 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -301,7 +301,6 @@ public: bool isSWaitCnt() const; bool isHwreg() const; bool isSendMsg() const; - bool isMubufOffset() const; bool isSMRDOffset() const; bool isSMRDLiteralOffset() const; bool isDPPCtrl() const; @@ -689,7 +688,6 @@ public: OperandMatchResultTy parseSendMsgOp(OperandVector &Operands); OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands); - AMDGPUOperand::Ptr defaultHwreg() const; void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, false); } void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, false); } @@ -706,9 +704,6 @@ public: AMDGPUOperand::Ptr defaultSMRDOffset() const; AMDGPUOperand::Ptr defaultSMRDLiteralOffset() const; - AMDGPUOperand::Ptr defaultClampSI() const; - AMDGPUOperand::Ptr defaultOModSI() const; - OperandMatchResultTy parseOModOperand(OperandVector &Operands); void cvtId(MCInst &Inst, const OperandVector &Operands); @@ -727,11 +722,6 @@ public: OperandMatchResultTy parseSDWASel(OperandVector &Operands, StringRef Prefix, AMDGPUOperand::ImmTy Type); OperandMatchResultTy parseSDWADstUnused(OperandVector &Operands); - AMDGPUOperand::Ptr defaultSDWASel(AMDGPUOperand::ImmTy Type) const; - AMDGPUOperand::Ptr defaultSDWADstSel() const; - AMDGPUOperand::Ptr defaultSDWASrc0Sel() const; - AMDGPUOperand::Ptr defaultSDWASrc1Sel() const; - AMDGPUOperand::Ptr defaultSDWADstUnused() const; void cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands); void cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands); void cvtSDWA(MCInst &Inst, const OperandVector &Operands, bool IsVOP1); @@ -1917,10 +1907,6 @@ bool AMDGPUOperand::isHwreg() const { return isImmTy(ImmTyHwreg); } -AMDGPUOperand::Ptr AMDGPUAsmParser::defaultHwreg() const { - return AMDGPUOperand::CreateImm(0, SMLoc(), AMDGPUOperand::ImmTyHwreg); -} - bool AMDGPUAsmParser::parseSendMsgConstruct(OperandInfoTy &Msg, OperandInfoTy &Operation, int64_t &StreamId) { using namespace llvm::AMDGPU::SendMsg; @@ -2131,10 +2117,6 @@ AMDGPUAsmParser::parseSOppBrTarget(OperandVector &Operands) { // mubuf //===----------------------------------------------------------------------===// -bool AMDGPUOperand::isMubufOffset() const { - return isImmTy(ImmTyOffset) && isUInt<12>(getImm()); -} - AMDGPUOperand::Ptr AMDGPUAsmParser::defaultGLC() const { return AMDGPUOperand::CreateImm(0, SMLoc(), AMDGPUOperand::ImmTyGLC); } @@ -2412,14 +2394,6 @@ AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::parseOModOperand(OperandV } } -AMDGPUOperand::Ptr AMDGPUAsmParser::defaultClampSI() const { - return AMDGPUOperand::CreateImm(0, SMLoc(), AMDGPUOperand::ImmTyClampSI); -} - -AMDGPUOperand::Ptr AMDGPUAsmParser::defaultOModSI() const { - return AMDGPUOperand::CreateImm(1, SMLoc(), AMDGPUOperand::ImmTyOModSI); -} - void AMDGPUAsmParser::cvtId(MCInst &Inst, const OperandVector &Operands) { unsigned I = 1; const MCInstrDesc &Desc = MII.get(Inst.getOpcode()); @@ -2705,26 +2679,6 @@ AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) { return MatchOperand_Success; } -AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSDWASel(AMDGPUOperand::ImmTy Type) const { - return AMDGPUOperand::CreateImm(6, SMLoc(), Type); -} - -AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSDWADstSel() const { - return defaultSDWASel(AMDGPUOperand::ImmTySdwaDstSel); -} - -AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSDWASrc0Sel() const { - return defaultSDWASel(AMDGPUOperand::ImmTySdwaSrc0Sel); -} - -AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSDWASrc1Sel() const { - return defaultSDWASel(AMDGPUOperand::ImmTySdwaSrc1Sel); -} - -AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSDWADstUnused() const { - return AMDGPUOperand::CreateImm(0, SMLoc(), AMDGPUOperand::ImmTySdwaDstUnused); -} - void AMDGPUAsmParser::cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands) { cvtSDWA(Inst, Operands, true); } diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp index 5e8459db38d3..a1cd24ebba59 100644 --- a/llvm/lib/Target/ARM/ARMFastISel.cpp +++ b/llvm/lib/Target/ARM/ARMFastISel.cpp @@ -109,11 +109,6 @@ class ARMFastISel final : public FastISel { const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill); - unsigned fastEmitInst_rrr(unsigned MachineInstOpcode, - const TargetRegisterClass *RC, - unsigned Op0, bool Op0IsKill, - unsigned Op1, bool Op1IsKill, - unsigned Op2, bool Op2IsKill); unsigned fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, @@ -331,38 +326,6 @@ unsigned ARMFastISel::fastEmitInst_rr(unsigned MachineInstOpcode, return ResultReg; } -unsigned ARMFastISel::fastEmitInst_rrr(unsigned MachineInstOpcode, - const TargetRegisterClass *RC, - unsigned Op0, bool Op0IsKill, - unsigned Op1, bool Op1IsKill, - unsigned Op2, bool Op2IsKill) { - unsigned ResultReg = createResultReg(RC); - const MCInstrDesc &II = TII.get(MachineInstOpcode); - - // Make sure the input operands are sufficiently constrained to be legal - // for this instruction. - Op0 = constrainOperandRegClass(II, Op0, 1); - Op1 = constrainOperandRegClass(II, Op1, 2); - Op2 = constrainOperandRegClass(II, Op1, 3); - - if (II.getNumDefs() >= 1) { - AddOptionalDefs( - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) - .addReg(Op0, Op0IsKill * RegState::Kill) - .addReg(Op1, Op1IsKill * RegState::Kill) - .addReg(Op2, Op2IsKill * RegState::Kill)); - } else { - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) - .addReg(Op0, Op0IsKill * RegState::Kill) - .addReg(Op1, Op1IsKill * RegState::Kill) - .addReg(Op2, Op2IsKill * RegState::Kill)); - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, - TII.get(TargetOpcode::COPY), ResultReg) - .addReg(II.ImplicitDefs[0])); - } - return ResultReg; -} - unsigned ARMFastISel::fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp index 901ab45c2dcd..1b40655fbe15 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp @@ -214,11 +214,6 @@ public: llvm_unreachable("Invalid ShiftOpc!"); } - /// getAddrMode2OpValue - Return encoding for addrmode2 operands. - uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups, - const MCSubtargetInfo &STI) const; - /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands. uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups, @@ -346,9 +341,6 @@ public: unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; - unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups, - const MCSubtargetInfo &STI) const; /// getSORegOpValue - Return an encoded so_reg shifted register value. unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op, @@ -1105,21 +1097,6 @@ getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, return Binary; } -uint32_t ARMMCCodeEmitter:: -getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups, - const MCSubtargetInfo &STI) const { - // {17-14} Rn - // {13} 1 == imm12, 0 == Rm - // {12} isAdd - // {11-0} imm12/Rm - const MCOperand &MO = MI.getOperand(OpIdx); - unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); - uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups, STI); - Binary |= Rn << 14; - return Binary; -} - uint32_t ARMMCCodeEmitter:: getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups, @@ -1486,23 +1463,6 @@ getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, return Value; } -unsigned ARMMCCodeEmitter:: -getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups, - const MCSubtargetInfo &STI) const { - const MCOperand &MO1 = MI.getOperand(OpNum); - - // FIXME: Needs fixup support. - unsigned Value = 0; - int32_t tmp = (int32_t)MO1.getImm(); - if (tmp < 0) - tmp = abs(tmp); - else - Value |= 4096; // Set the ADD bit - Value |= tmp & 4095; - return Value; -} - unsigned ARMMCCodeEmitter:: getT2SORegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups, diff --git a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp index 6cf5f505fea8..496efbf7374b 100644 --- a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp +++ b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp @@ -151,7 +151,6 @@ public: } } - bool mustExtend(OperandVector &Operands); bool splitIdentifier(OperandVector &Operands); bool parseOperand(OperandVector &Operands); bool parseInstruction(OperandVector &Operands); @@ -817,18 +816,6 @@ bool HexagonAsmParser::matchOneInstruction(MCInst &MCI, SMLoc IDLoc, llvm_unreachable("Implement any new match types added!"); } -bool HexagonAsmParser::mustExtend(OperandVector &Operands) { - unsigned Count = 0; - for (std::unique_ptr &i : Operands) - if (i->isImm()) - if (HexagonMCInstrInfo::mustExtend( - *static_cast(i.get())->Imm.Val)) - ++Count; - // Multiple extenders should have been filtered by iss9Ext et. al. - assert(Count < 2 && "Multiple extenders"); - return Count == 1; -} - bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp index d69554f95f99..93dd6f8f0808 100644 --- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -158,8 +158,6 @@ namespace { static void getInstrUses(const MachineInstr &MI, RegisterSet &Uses); static bool isEqual(const BitTracker::RegisterCell &RC1, uint16_t B1, const BitTracker::RegisterCell &RC2, uint16_t B2, uint16_t W); - static bool isConst(const BitTracker::RegisterCell &RC, uint16_t B, - uint16_t W); static bool isZero(const BitTracker::RegisterCell &RC, uint16_t B, uint16_t W); static bool getConst(const BitTracker::RegisterCell &RC, uint16_t B, @@ -283,17 +281,6 @@ bool HexagonBitSimplify::isEqual(const BitTracker::RegisterCell &RC1, return true; } - -bool HexagonBitSimplify::isConst(const BitTracker::RegisterCell &RC, - uint16_t B, uint16_t W) { - assert(B < RC.width() && B+W <= RC.width()); - for (uint16_t i = B; i < B+W; ++i) - if (!RC[i].num()) - return false; - return true; -} - - bool HexagonBitSimplify::isZero(const BitTracker::RegisterCell &RC, uint16_t B, uint16_t W) { assert(B < RC.width() && B+W <= RC.width()); diff --git a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp index caadd58c74f8..4dff0dbc2b71 100644 --- a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp +++ b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp @@ -80,8 +80,6 @@ private: bool analyzeUses(unsigned DefR, const NodeList &UNodeList, InstrEvalMap &InstrEvalResult, short &SizeInc); bool hasRepForm(MachineInstr *MI, unsigned TfrDefR); - MachineInstr *getReachedDefMI(NodeAddr SN, unsigned OffsetReg, - bool &HasReachingDef); bool canRemoveAddasl(NodeAddr AddAslSN, MachineInstr *MI, const NodeList &UNodeList); void getAllRealUses(NodeAddr SN, NodeList &UNodeList); @@ -128,41 +126,6 @@ bool HexagonOptAddrMode::hasRepForm(MachineInstr *MI, unsigned TfrDefR) { return false; } -MachineInstr *HexagonOptAddrMode::getReachedDefMI(NodeAddr SN, - unsigned OffsetReg, - bool &HasReachingDef) { - MachineInstr *ReachedDefMI = NULL; - NodeId RD = 0; - for (NodeAddr UN : SN.Addr->members_if(DFG->IsUse, *DFG)) { - RegisterRef UR = UN.Addr->getRegRef(); - if (OffsetReg == UR.Reg) { - RD = UN.Addr->getReachingDef(); - if (!RD) - continue; - HasReachingDef = true; - } - } - if (HasReachingDef) { - NodeAddr RDN = DFG->addr(RD); - DEBUG({ - NodeAddr ReachingIA = RDN.Addr->getOwner(*DFG); - dbgs() << "\t\t\t[Def Node]: " - << Print>(ReachingIA, *DFG) << "\n"; - }); - NodeId ReachedID = RDN.Addr->getReachedDef(); - if (!ReachedID) - return ReachedDefMI; - - NodeAddr ReachedDN = DFG->addr(ReachedID); - NodeAddr ReachedIA = ReachedDN.Addr->getOwner(*DFG); - DEBUG(dbgs() << "\t\t\t[Reached Def Node]: " - << Print>(ReachedIA, *DFG) << "\n"); - ReachedDefMI = ReachedIA.Addr->getCode(); - DEBUG(dbgs() << "\nReached Def MI === " << *ReachedDefMI << "\n"); - } - return ReachedDefMI; -} - // Check if addasl instruction can be removed. This is possible only // if it's feeding to only load/store instructions with base + register // offset as these instruction can be tranformed to use 'absolute plus diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index f6c2e5bb247c..2ab78490c5ae 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -158,7 +158,6 @@ class MipsAsmParser : public MCTargetAsmParser { OperandMatchResultTy parseImm(OperandVector &Operands); OperandMatchResultTy parseJumpTarget(OperandVector &Operands); OperandMatchResultTy parseInvNum(OperandVector &Operands); - OperandMatchResultTy parseLSAImm(OperandVector &Operands); OperandMatchResultTy parseRegisterPair(OperandVector &Operands); OperandMatchResultTy parseMovePRegPair(OperandVector &Operands); OperandMatchResultTy parseRegisterList(OperandVector &Operands); @@ -306,8 +305,6 @@ class MipsAsmParser : public MCTargetAsmParser { int matchHWRegsRegisterName(StringRef Symbol); - int matchRegisterByNumber(unsigned RegNum, unsigned RegClass); - int matchFPURegisterName(StringRef Name); int matchFCCRegisterName(StringRef Name); @@ -4122,14 +4119,6 @@ unsigned MipsAsmParser::getReg(int RC, int RegNo) { return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo); } -int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) { - if (RegNum > - getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs() - 1) - return -1; - - return getReg(RegClass, RegNum); -} - bool MipsAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { MCAsmParser &Parser = getParser(); DEBUG(dbgs() << "parseOperand\n"); @@ -4662,46 +4651,6 @@ MipsAsmParser::parseInvNum(OperandVector &Operands) { return MatchOperand_Success; } -MipsAsmParser::OperandMatchResultTy -MipsAsmParser::parseLSAImm(OperandVector &Operands) { - MCAsmParser &Parser = getParser(); - switch (getLexer().getKind()) { - default: - return MatchOperand_NoMatch; - case AsmToken::LParen: - case AsmToken::Plus: - case AsmToken::Minus: - case AsmToken::Integer: - break; - } - - const MCExpr *Expr; - SMLoc S = Parser.getTok().getLoc(); - - if (getParser().parseExpression(Expr)) - return MatchOperand_ParseFail; - - int64_t Val; - if (!Expr->evaluateAsAbsolute(Val)) { - Error(S, "expected immediate value"); - return MatchOperand_ParseFail; - } - - // The LSA instruction allows a 2-bit unsigned immediate. For this reason - // and because the CPU always adds one to the immediate field, the allowed - // range becomes 1..4. We'll only check the range here and will deal - // with the addition/subtraction when actually decoding/encoding - // the instruction. - if (Val < 1 || Val > 4) { - Error(S, "immediate not in range (1..4)"); - return MatchOperand_ParseFail; - } - - Operands.push_back( - MipsOperand::CreateImm(Expr, S, Parser.getTok().getLoc(), *this)); - return MatchOperand_Success; -} - MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseRegisterList(OperandVector &Operands) { MCAsmParser &Parser = getParser();