forked from OSchip/llvm-project
AMDGPU: Use better alignment for kernarg lowering
This was just emitting loads with the ABI alignment for the raw type. The true alignment is often better, especially when an illegal vector type was scalarized. The better alignment allows using a scalar load more often. llvm-svn: 333558
This commit is contained in:
Matt Arsenault
parent
ebaaa2ddae
commit
7b4826e6ce
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@ -1068,15 +1068,12 @@ SDValue SITargetLowering::convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT,
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SDValue SITargetLowering::lowerKernargMemParameter(
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SelectionDAG &DAG, EVT VT, EVT MemVT,
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const SDLoc &SL, SDValue Chain,
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uint64_t Offset, bool Signed,
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uint64_t Offset, unsigned Align, bool Signed,
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const ISD::InputArg *Arg) const {
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const DataLayout &DL = DAG.getDataLayout();
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Type *Ty = MemVT.getTypeForEVT(*DAG.getContext());
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PointerType *PtrTy = PointerType::get(Ty, AMDGPUASI.CONSTANT_ADDRESS);
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MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
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unsigned Align = DL.getABITypeAlignment(Ty);
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SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, Offset);
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SDValue Load = DAG.getLoad(MemVT, SL, Chain, Ptr, PtrInfo, Align,
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MachineMemOperand::MODereferenceable |
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@ -1663,7 +1660,15 @@ SDValue SITargetLowering::LowerFormalArguments(
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SmallVector<SDValue, 16> Chains;
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for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
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// FIXME: This is the minimum kernel argument alignment. We should improve
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// this to the maximum alignment of the arguments.
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//
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// FIXME: Alignment of explicit arguments totally broken with non-0 explicit
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// kern arg offset.
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const unsigned KernelArgBaseAlign = 16;
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const unsigned ExplicitOffset = Subtarget->getExplicitKernelArgOffset(Fn);
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for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
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const ISD::InputArg &Arg = Ins[i];
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if (Skipped[i]) {
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InVals.push_back(DAG.getUNDEF(Arg.VT));
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@ -1677,14 +1682,14 @@ SDValue SITargetLowering::LowerFormalArguments(
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VT = Ins[i].VT;
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EVT MemVT = VA.getLocVT();
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const uint64_t Offset = Subtarget->getExplicitKernelArgOffset(Fn) +
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VA.getLocMemOffset();
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const uint64_t Offset = ExplicitOffset + VA.getLocMemOffset();
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Info->setABIArgOffset(Offset + MemVT.getStoreSize());
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unsigned Align = MinAlign(KernelArgBaseAlign, Offset);
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// The first 36 bytes of the input buffer contains information about
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// thread group and global sizes.
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// thread group and global sizes for clover.
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SDValue Arg = lowerKernargMemParameter(
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DAG, VT, MemVT, DL, Chain, Offset, Ins[i].Flags.isSExt(), &Ins[i]);
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DAG, VT, MemVT, DL, Chain, Offset, Align, Ins[i].Flags.isSExt(), &Ins[i]);
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Chains.push_back(Arg.getValue(1));
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auto *ParamTy =
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@ -4303,7 +4308,7 @@ SDValue SITargetLowering::lowerImplicitZextParam(SelectionDAG &DAG,
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unsigned Offset) const {
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SDLoc SL(Op);
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SDValue Param = lowerKernargMemParameter(DAG, MVT::i32, MVT::i32, SL,
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DAG.getEntryNode(), Offset, false);
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DAG.getEntryNode(), Offset, 4, false);
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// The local size values will have the hi 16-bits as zero.
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return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param,
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DAG.getValueType(VT));
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@ -4404,37 +4409,37 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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return emitNonHSAIntrinsicError(DAG, DL, VT);
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return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
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SI::KernelInputOffsets::NGROUPS_X, false);
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SI::KernelInputOffsets::NGROUPS_X, 4, false);
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case Intrinsic::r600_read_ngroups_y:
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if (Subtarget->isAmdHsaOS())
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return emitNonHSAIntrinsicError(DAG, DL, VT);
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return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
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SI::KernelInputOffsets::NGROUPS_Y, false);
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SI::KernelInputOffsets::NGROUPS_Y, 4, false);
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case Intrinsic::r600_read_ngroups_z:
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if (Subtarget->isAmdHsaOS())
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return emitNonHSAIntrinsicError(DAG, DL, VT);
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return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
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SI::KernelInputOffsets::NGROUPS_Z, false);
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SI::KernelInputOffsets::NGROUPS_Z, 4, false);
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case Intrinsic::r600_read_global_size_x:
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if (Subtarget->isAmdHsaOS())
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return emitNonHSAIntrinsicError(DAG, DL, VT);
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return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
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SI::KernelInputOffsets::GLOBAL_SIZE_X, false);
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SI::KernelInputOffsets::GLOBAL_SIZE_X, 4, false);
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case Intrinsic::r600_read_global_size_y:
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if (Subtarget->isAmdHsaOS())
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return emitNonHSAIntrinsicError(DAG, DL, VT);
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return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
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SI::KernelInputOffsets::GLOBAL_SIZE_Y, false);
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SI::KernelInputOffsets::GLOBAL_SIZE_Y, 4, false);
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case Intrinsic::r600_read_global_size_z:
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if (Subtarget->isAmdHsaOS())
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return emitNonHSAIntrinsicError(DAG, DL, VT);
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return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
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SI::KernelInputOffsets::GLOBAL_SIZE_Z, false);
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SI::KernelInputOffsets::GLOBAL_SIZE_Z, 4, false);
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case Intrinsic::r600_read_local_size_x:
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if (Subtarget->isAmdHsaOS())
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return emitNonHSAIntrinsicError(DAG, DL, VT);
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@ -27,7 +27,7 @@ class SITargetLowering final : public AMDGPUTargetLowering {
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SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
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SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
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const SDLoc &SL, SDValue Chain,
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uint64_t Offset, bool Signed,
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uint64_t Offset, unsigned Align, bool Signed,
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const ISD::InputArg *Arg = nullptr) const;
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SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
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@ -88,11 +88,9 @@ define amdgpu_kernel void @s_fneg_fabs_v2f16_non_bc_src(<2 x half> addrspace(1)*
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; Combine turns this into integer op when bitcast source (from load)
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; GCN-LABEL: {{^}}s_fneg_fabs_v2f16_bc_src:
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; CI: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 16, v{{[0-9]+}}
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; CI: v_or_b32_e32 [[OR:v[0-9]+]], v{{[0-9]+}}, [[SHL]]
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; CI: v_or_b32_e32 v{{[0-9]+}}, 0x80008000, [[OR]]
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; FIXME: Random commute
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; CI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80008000
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; VI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80008000
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; GFX9: s_or_b32 s{{[0-9]+}}, 0x80008000, s{{[0-9]+}}
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define amdgpu_kernel void @s_fneg_fabs_v2f16_bc_src(<2 x half> addrspace(1)* %out, <2 x half> %in) {
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@ -103,16 +101,12 @@ define amdgpu_kernel void @s_fneg_fabs_v2f16_bc_src(<2 x half> addrspace(1)* %ou
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}
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; GCN-LABEL: {{^}}fneg_fabs_v4f16:
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; CI: s_mov_b32 [[MASK:s[0-9]+]], 0x80008000
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; CI: v_lshlrev_b32_e32 [[SHL0:v[0-9]+]], 16, v{{[0-9]+}}
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; CI: v_or_b32_e32 [[OR0:v[0-9]+]], v{{[0-9]+}}, [[SHL0]]
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; CI: v_lshlrev_b32_e32 [[SHL1:v[0-9]+]], 16, v{{[0-9]+}}
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; CI: v_or_b32_e32 [[OR1:v[0-9]+]], v{{[0-9]+}}, [[SHL1]]
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; CI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], [[OR0]]
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; CI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], [[OR1]]
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; FIXME: Random commute
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; GFX89: s_mov_b32 [[MASK:s[0-9]+]], 0x80008000
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; GCN: s_mov_b32 [[MASK:s[0-9]+]], 0x80008000
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; CI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, [[MASK]]
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; CI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, [[MASK]]
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; VI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, [[MASK]]
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; VI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, [[MASK]]
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@ -13,17 +13,10 @@ define amdgpu_kernel void @load_f16_arg(half addrspace(1)* %out, half %arg) #0 {
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ret void
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}
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; FIXME: Should always be the same
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; GCN-LABEL: {{^}}load_v2f16_arg:
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; SI-DAG: buffer_load_ushort [[V0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:44
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; SI-DAG: buffer_load_ushort [[V1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:46
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; SI: v_lshlrev_b32_e32 [[HI:v[0-9]+]], 16, [[V1]]
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; SI: v_or_b32_e32 [[PACKED:v[0-9]+]], [[V0]], [[HI]]
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; SI: buffer_store_dword [[PACKED]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; VI: s_load_dword [[ARG:s[0-9]+]]
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; VI: v_mov_b32_e32 [[V_ARG:v[0-9]+]], [[ARG]]
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; VI: buffer_store_dword [[V_ARG]]
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; GCN: s_load_dword [[ARG:s[0-9]+]]
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; GCN: v_mov_b32_e32 [[V_ARG:v[0-9]+]], [[ARG]]
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; GCN: buffer_store_dword [[V_ARG]]
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define amdgpu_kernel void @load_v2f16_arg(<2 x half> addrspace(1)* %out, <2 x half> %arg) #0 {
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store <2 x half> %arg, <2 x half> addrspace(1)* %out
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ret void
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@ -31,8 +24,8 @@ define amdgpu_kernel void @load_v2f16_arg(<2 x half> addrspace(1)* %out, <2 x ha
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; GCN-LABEL: {{^}}load_v3f16_arg:
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; GCN: buffer_load_ushort
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; GCN: buffer_load_ushort
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; GCN: buffer_load_ushort
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; GCN: s_load_dword s
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; GCN-NOT: buffer_load
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; GCN-DAG: buffer_store_dword
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; GCN-DAG: buffer_store_short
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@ -43,19 +36,14 @@ define amdgpu_kernel void @load_v3f16_arg(<3 x half> addrspace(1)* %out, <3 x ha
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ret void
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}
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; GCN-LABEL: {{^}}load_v4f16_arg:
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; SI: buffer_load_ushort
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; SI: buffer_load_ushort
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; SI: buffer_load_ushort
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; SI: buffer_load_ushort
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; SI: buffer_store_dwordx2
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; FIXME: Why not one load?
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; VI-DAG: s_load_dword [[ARG0_LO:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
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; VI-DAG: s_load_dword [[ARG0_HI:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
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; VI-DAG: v_mov_b32_e32 v[[V_ARG0_LO:[0-9]+]], [[ARG0_LO]]
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; VI-DAG: v_mov_b32_e32 v[[V_ARG0_HI:[0-9]+]], [[ARG0_HI]]
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; VI: buffer_store_dwordx2 v{{\[}}[[V_ARG0_LO]]:[[V_ARG0_HI]]{{\]}}
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; GCN-LABEL: {{^}}load_v4f16_arg:
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; GCN-DAG: s_load_dword [[ARG0_LO:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
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; GCN-DAG: s_load_dword [[ARG0_HI:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0xc|0x30}}
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; GCN-DAG: v_mov_b32_e32 v[[V_ARG0_LO:[0-9]+]], [[ARG0_LO]]
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; GCN-DAG: v_mov_b32_e32 v[[V_ARG0_HI:[0-9]+]], [[ARG0_HI]]
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; GCN: buffer_store_dwordx2 v{{\[}}[[V_ARG0_LO]]:[[V_ARG0_HI]]{{\]}}
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define amdgpu_kernel void @load_v4f16_arg(<4 x half> addrspace(1)* %out, <4 x half> %arg) #0 {
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store <4 x half> %arg, <4 x half> addrspace(1)* %out
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ret void
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@ -162,10 +162,11 @@ entry:
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; EG: VTX_READ_8
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; EG: VTX_READ_8
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; MESA-GCN: buffer_load_ubyte
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; MESA-GCN: buffer_load_ubyte
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; HSA-VI: flat_load_ubyte
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; HSA-VI: flat_load_ubyte
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; SI: buffer_load_ubyte
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; SI: buffer_load_ubyte
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; HSA: flat_load_ushort
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define amdgpu_kernel void @v2i8_arg(<2 x i8> addrspace(1)* %out, <2 x i8> %in) {
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entry:
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store <2 x i8> %in, <2 x i8> addrspace(1)* %out
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@ -179,10 +180,9 @@ entry:
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; EG: VTX_READ_16
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; EG: VTX_READ_16
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; SI: buffer_load_ushort
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; SI: buffer_load_ushort
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; VI: s_load_dword s
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; SI: s_load_dword s{{[0-9]+}}, s[0:1], 0xb
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; MESA-VI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c
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; HSA-VI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x8
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define amdgpu_kernel void @v2i16_arg(<2 x i16> addrspace(1)* %out, <2 x i16> %in) {
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entry:
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store <2 x i16> %in, <2 x i16> addrspace(1)* %out
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@ -226,11 +226,14 @@ entry:
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; EG-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 40
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; EG-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 41
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; EG-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 42
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; MESA-GCN: buffer_load_ubyte
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; MESA-GCN: buffer_load_ubyte
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; MESA-GCN: buffer_load_ubyte
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; HSA-VI: flat_load_ubyte
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; HSA-VI: flat_load_ubyte
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; SI: buffer_load_ubyte
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; SI: buffer_load_ubyte
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; SI: buffer_load_ubyte
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; MESA-VI: buffer_load_ushort
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; MESA-VI: buffer_load_ubyte
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; HSA-VI: flat_load_ushort
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; HSA-VI: flat_load_ubyte
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define amdgpu_kernel void @v3i8_arg(<3 x i8> addrspace(1)* nocapture %out, <3 x i8> %in) nounwind {
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entry:
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@ -245,12 +248,9 @@ entry:
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; EG-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 44
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; EG-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 46
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; EG-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 48
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; MESA-GCN: buffer_load_ushort
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; MESA-GCN: buffer_load_ushort
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; MESA-GCN: buffer_load_ushort
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; HSA-VI: flat_load_ushort
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; HSA-VI: flat_load_ushort
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; HSA-VI: flat_load_ushort
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; GCN-DAG: s_load_dword s
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; GCN-DAG: {{buffer|flat}}_load_ushort
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define amdgpu_kernel void @v3i16_arg(<3 x i16> addrspace(1)* nocapture %out, <3 x i16> %in) nounwind {
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entry:
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store <3 x i16> %in, <3 x i16> addrspace(1)* %out, align 4
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@ -293,14 +293,13 @@ entry:
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; EG: VTX_READ_8
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; EG: VTX_READ_8
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; EG: VTX_READ_8
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; MESA-GCN: buffer_load_ubyte
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; MESA-GCN: buffer_load_ubyte
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; MESA-GCN: buffer_load_ubyte
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; MESA-GCN: buffer_load_ubyte
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; HSA-VI: flat_load_ubyte
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; HSA-VI: flat_load_ubyte
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; HSA-VI: flat_load_ubyte
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; HSA-VI: flat_load_ubyte
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; SI: buffer_load_ubyte
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; SI: buffer_load_ubyte
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; SI: buffer_load_ubyte
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; SI: buffer_load_ubyte
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; VI: s_load_dword s
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define amdgpu_kernel void @v4i8_arg(<4 x i8> addrspace(1)* %out, <4 x i8> %in) {
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entry:
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store <4 x i8> %in, <4 x i8> addrspace(1)* %out
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@ -315,13 +314,14 @@ entry:
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; EG: VTX_READ_16
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; EG: VTX_READ_16
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; SI: buffer_load_ushort
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; SI: buffer_load_ushort
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; SI: buffer_load_ushort
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; SI: buffer_load_ushort
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; SI-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0xb
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; SI-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x9
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; VI: s_load_dword s
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; VI: s_load_dword s
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; MESA-VI-DAG: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x2c
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; MESA-VI-DAG: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x30
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; HSA-VI-DAG: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x8
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; HSA-VI-DAG: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0xc
|
||||
define amdgpu_kernel void @v4i16_arg(<4 x i16> addrspace(1)* %out, <4 x i16> %in) {
|
||||
entry:
|
||||
store <4 x i16> %in, <4 x i16> addrspace(1)* %out
|
||||
|
|
@ -372,21 +372,17 @@ entry:
|
|||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; HSA-GCN: float_load_ubyte
|
||||
; HSA-GCN: float_load_ubyte
|
||||
; HSA-GCN: float_load_ubyte
|
||||
; HSA-GCN: float_load_ubyte
|
||||
; HSA-GCN: float_load_ubyte
|
||||
; HSA-GCN: float_load_ubyte
|
||||
; HSA-GCN: float_load_ubyte
|
||||
; HSA-GCN: float_load_ubyte
|
||||
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
|
||||
; VI: s_load_dwordx2
|
||||
; VI: s_load_dwordx2
|
||||
define amdgpu_kernel void @v8i8_arg(<8 x i8> addrspace(1)* %out, <8 x i8> %in) {
|
||||
entry:
|
||||
store <8 x i8> %in, <8 x i8> addrspace(1)* %out
|
||||
|
|
@ -405,15 +401,11 @@ entry:
|
|||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: s_load_dwordx2
|
||||
; SI: s_load_dwordx2
|
||||
; SI: s_load_dwordx2
|
||||
|
||||
; VI: s_load_dwordx2
|
||||
; VI: s_load_dword s
|
||||
; VI: s_load_dword s
|
||||
; VI: s_load_dword s
|
||||
|
|
@ -481,38 +473,27 @@ entry:
|
|||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; EG: VTX_READ_8
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; MESA-GCN: buffer_load_ubyte
|
||||
; HSA-VI: flat_load_ubyte
|
||||
; HSA-VI: flat_load_ubyte
|
||||
; HSA-VI: flat_load_ubyte
|
||||
; HSA-VI: flat_load_ubyte
|
||||
; HSA-VI: flat_load_ubyte
|
||||
; HSA-VI: flat_load_ubyte
|
||||
; HSA-VI: flat_load_ubyte
|
||||
; HSA-VI: flat_load_ubyte
|
||||
; HSA-VI: flat_load_ubyte
|
||||
; HSA-VI: flat_load_ubyte
|
||||
; HSA-VI: flat_load_ubyte
|
||||
; HSA-VI: flat_load_ubyte
|
||||
; HSA-VI: flat_load_ubyte
|
||||
; HSA-VI: flat_load_ubyte
|
||||
; HSA-VI: flat_load_ubyte
|
||||
; HSA-VI: flat_load_ubyte
|
||||
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
|
||||
; VI: s_load_dwordx2
|
||||
; VI: s_load_dwordx2
|
||||
; VI: s_load_dwordx2
|
||||
define amdgpu_kernel void @v16i8_arg(<16 x i8> addrspace(1)* %out, <16 x i8> %in) {
|
||||
entry:
|
||||
store <16 x i8> %in, <16 x i8> addrspace(1)* %out
|
||||
|
|
@ -539,22 +520,13 @@ entry:
|
|||
; EG: VTX_READ_16
|
||||
; EG: VTX_READ_16
|
||||
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: buffer_load_ushort
|
||||
; SI: s_load_dword s
|
||||
; SI: s_load_dword s
|
||||
; SI: s_load_dword s
|
||||
; SI: s_load_dword s
|
||||
; SI: s_load_dwordx2
|
||||
; SI: s_load_dwordx2
|
||||
; SI: s_load_dwordx2
|
||||
|
||||
; VI: s_load_dword s
|
||||
; VI: s_load_dword s
|
||||
|
|
|
|||
|
|
@ -39,10 +39,8 @@ define amdgpu_kernel void @store_v4i32_as_v2i64_align_4(<2 x i64> addrspace(3)*
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_v4i16_as_v2i32_align_4:
|
||||
; GCN: buffer_load_ushort
|
||||
; GCN: buffer_load_ushort
|
||||
; GCN: buffer_load_ushort
|
||||
; GCN: buffer_load_ushort
|
||||
; GCN: s_load_dword s
|
||||
; GCN: s_load_dwordx2 s
|
||||
; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}}
|
||||
define amdgpu_kernel void @store_v4i16_as_v2i32_align_4(<2 x i32> addrspace(3)* align 4 %out, <4 x i16> %x) #0 {
|
||||
%x.bc = bitcast <4 x i16> %x to <2 x i32>
|
||||
|
|
|
|||
Loading…
Reference in New Issue