forked from OSchip/llvm-project
[llvm-mca] Use llvm::make_unique in a few places. NFC
Also, clang-format a couple of DEBUG functions. llvm-svn: 327978
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@ -33,8 +33,8 @@ void Backend::runCycle(unsigned Cycle) {
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while (SM.hasNext()) {
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InstRef IR = SM.peekNext();
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std::unique_ptr<Instruction> NewIS(
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IB->createInstruction(IR.first, *IR.second));
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std::unique_ptr<Instruction> NewIS =
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IB->createInstruction(IR.first, *IR.second);
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const InstrDesc &Desc = NewIS->getDesc();
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if (!DU->isAvailable(Desc.NumMicroOps) ||
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!DU->canDispatch(IR.first, *NewIS))
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@ -80,5 +80,4 @@ void Backend::notifyCycleEnd(unsigned Cycle) {
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for (HWEventListener *Listener : Listeners)
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Listener->onCycleEnd(Cycle);
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}
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} // namespace mca.
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@ -112,12 +112,12 @@ initializeUsedResources(InstrDesc &ID, const MCSchedClassDesc &SCDesc,
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}
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}
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DEBUG(
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DEBUG({
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for (const std::pair<uint64_t, ResourceUsage> &R : ID.Resources)
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dbgs() << "\t\tMask=" << R.first << ", cy=" << R.second.size() << '\n';
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for (const uint64_t R : ID.Buffers)
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dbgs() << "\t\tBuffer Mask=" << R << '\n';
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);
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});
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}
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static void computeMaxLatency(InstrDesc &ID, const MCInstrDesc &MCDesc,
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@ -260,11 +260,10 @@ static void populateWrites(InstrDesc &ID, const MCInst &MCI,
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}
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Write.FullyUpdatesSuperRegs = FullyUpdatesSuperRegisters;
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Write.IsOptionalDef = false;
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DEBUG(
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dbgs() << "\t\tOpIdx=" << Write.OpIndex
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<< ", Latency=" << Write.Latency << ", WriteResourceID="
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<< Write.SClassOrWriteResourceID << '\n';
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);
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DEBUG({
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dbgs() << "\t\tOpIdx=" << Write.OpIndex << ", Latency=" << Write.Latency
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<< ", WriteResourceID=" << Write.SClassOrWriteResourceID << '\n';
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});
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CurrentDef++;
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}
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@ -371,7 +370,7 @@ void InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
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*SM.getSchedClassDesc(MCDesc.getSchedClass());
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// Create a new empty descriptor.
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InstrDesc *ID = new InstrDesc();
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std::unique_ptr<InstrDesc> ID = llvm::make_unique<InstrDesc>();
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if (SCDesc.isVariant()) {
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errs() << "warning: don't know how to model variant opcodes.\n"
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@ -406,7 +405,7 @@ void InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
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DEBUG(dbgs() << "\t\tNumMicroOps=" << ID->NumMicroOps << '\n');
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// Now add the new descriptor.
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Descriptors[Opcode] = std::unique_ptr<const InstrDesc>(ID);
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Descriptors[Opcode] = std::move(ID);
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}
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const InstrDesc &InstrBuilder::getOrCreateInstrDesc(const MCInst &MCI) {
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@ -416,9 +415,10 @@ const InstrDesc &InstrBuilder::getOrCreateInstrDesc(const MCInst &MCI) {
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return *Descriptors[MCI.getOpcode()].get();
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}
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Instruction *InstrBuilder::createInstruction(unsigned Idx, const MCInst &MCI) {
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std::unique_ptr<Instruction>
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InstrBuilder::createInstruction(unsigned Idx, const MCInst &MCI) {
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const InstrDesc &D = getOrCreateInstrDesc(MCI);
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Instruction *NewIS = new Instruction(D);
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std::unique_ptr<Instruction> NewIS = llvm::make_unique<Instruction>(D);
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// Populate Reads first.
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for (const ReadDescriptor &RD : D.Reads) {
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@ -441,8 +441,7 @@ Instruction *InstrBuilder::createInstruction(unsigned Idx, const MCInst &MCI) {
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// Okay, this is a register operand. Create a ReadState for it.
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assert(RegID > 0 && "Invalid register ID found!");
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ReadState *NewRDS = new ReadState(RD, RegID);
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NewIS->getUses().emplace_back(std::unique_ptr<ReadState>(NewRDS));
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NewIS->getUses().emplace_back(llvm::make_unique<ReadState>(RD, RegID));
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}
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// Now populate writes.
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@ -455,12 +454,9 @@ Instruction *InstrBuilder::createInstruction(unsigned Idx, const MCInst &MCI) {
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if (WD.IsOptionalDef && !RegID)
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continue;
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WriteState *NewWS = new WriteState(WD);
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NewIS->getDefs().emplace_back(std::unique_ptr<WriteState>(NewWS));
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NewWS->setRegisterID(RegID);
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NewIS->getDefs().emplace_back(llvm::make_unique<WriteState>(WD, RegID));
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}
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return NewIS;
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}
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} // namespace mca
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@ -53,7 +53,8 @@ public:
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const InstrDesc &getOrCreateInstrDesc(const llvm::MCInst &MCI);
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Instruction *createInstruction(unsigned Idx, const llvm::MCInst &MCI);
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std::unique_ptr<Instruction> createInstruction(unsigned Idx,
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const llvm::MCInst &MCI);
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};
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} // namespace mca
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@ -102,8 +102,8 @@ class WriteState {
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std::set<std::pair<ReadState *, int>> Users;
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public:
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WriteState(const WriteDescriptor &Desc)
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: WD(Desc), CyclesLeft(UNKNOWN_CYCLES), RegisterID(Desc.RegisterID) {}
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WriteState(const WriteDescriptor &Desc, unsigned RegID)
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: WD(Desc), CyclesLeft(UNKNOWN_CYCLES), RegisterID(RegID) {}
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WriteState(const WriteState &Other) = delete;
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WriteState &operator=(const WriteState &Other) = delete;
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