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[AMDGPU] gfx1010 Strengthen some SMEM WAR hazard unit tests. NFC. 

Tighten conditions on SMEM WAR hazard unit tests to ensure rejection
of workaround insertion where a s_waitcnt is present in dependency
chain. The current workaround code already conforms to these revise
tests.

llvm-svn: 360686
This commit is contained in:
Stanislav Mekhanoshin 2019-05-14 16:04:03 +00:00
parent e041d15f5e
commit 7b20032628
1 changed files with 19 additions and 2 deletions
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21
llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir
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@ -31,8 +31,8 @@ body: |
# GCN-LABEL: name: hazard_smem_war_related_clause
# GCN: S_LOAD_DWORD_IMM
# GCN: S_WAITCNT
# GCN: S_ADD_U32
# GCN-NEXT: S_WAITCNT
# GCN-NEXT: S_ADD_U32
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_related_clause
@ -46,6 +46,23 @@ body: |
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_smem_war_related_clause_vmcnt
# GCN: S_LOAD_DWORD_IMM
# GCN-NEXT: S_WAITCNT 3952{{$}}
# GCN-NEXT: S_ADD_U32
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_related_clause_vmcnt
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr4, $vgpr0, $vgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
S_WAITCNT 3952
$sgpr3 = S_ADD_U32 $sgpr2, $sgpr4, implicit-def $scc
$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_smem_war_branch
# GCN: S_LOAD_DWORD_IMM
# GCN: $sgpr_null = S_MOV_B32 0