forked from OSchip/llvm-project
AMDGPU: Use i64 scalar compare instructions
VI added eq/ne for i64, so use them. llvm-svn: 281800
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6fa7681bb6
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@ -38,18 +38,6 @@ class R600InstrInfo;
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namespace {
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namespace {
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static bool isCBranchSCC(const SDNode *N) {
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assert(N->getOpcode() == ISD::BRCOND);
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if (!N->hasOneUse())
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return false;
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SDValue Cond = N->getOperand(1);
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if (Cond.getOpcode() == ISD::CopyToReg)
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Cond = Cond.getOperand(2);
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return Cond.getOpcode() == ISD::SETCC &&
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Cond.getOperand(0).getValueType() == MVT::i32 && Cond.hasOneUse();
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}
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/// AMDGPU specific code to select AMDGPU machine instructions for
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/// AMDGPU specific code to select AMDGPU machine instructions for
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/// SelectionDAG operations.
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/// SelectionDAG operations.
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class AMDGPUDAGToDAGISel : public SelectionDAGISel {
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class AMDGPUDAGToDAGISel : public SelectionDAGISel {
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@ -150,6 +138,7 @@ private:
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uint32_t Offset, uint32_t Width);
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uint32_t Offset, uint32_t Width);
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void SelectS_BFEFromShifts(SDNode *N);
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void SelectS_BFEFromShifts(SDNode *N);
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void SelectS_BFE(SDNode *N);
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void SelectS_BFE(SDNode *N);
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bool isCBranchSCC(const SDNode *N) const;
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void SelectBRCOND(SDNode *N);
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void SelectBRCOND(SDNode *N);
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void SelectATOMIC_CMP_SWAP(SDNode *N);
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void SelectATOMIC_CMP_SWAP(SDNode *N);
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@ -1337,6 +1326,32 @@ void AMDGPUDAGToDAGISel::SelectS_BFE(SDNode *N) {
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SelectCode(N);
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SelectCode(N);
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}
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}
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bool AMDGPUDAGToDAGISel::isCBranchSCC(const SDNode *N) const {
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assert(N->getOpcode() == ISD::BRCOND);
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if (!N->hasOneUse())
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return false;
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SDValue Cond = N->getOperand(1);
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if (Cond.getOpcode() == ISD::CopyToReg)
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Cond = Cond.getOperand(2);
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if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse())
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return false;
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MVT VT = Cond.getOperand(0).getSimpleValueType();
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if (VT == MVT::i32)
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return true;
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if (VT == MVT::i64) {
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auto ST = static_cast<const SISubtarget *>(Subtarget);
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ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
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return (CC == ISD::SETEQ || CC == ISD::SETNE) && ST->hasScalarCompareEq64();
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}
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return false;
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}
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void AMDGPUDAGToDAGISel::SelectBRCOND(SDNode *N) {
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void AMDGPUDAGToDAGISel::SelectBRCOND(SDNode *N) {
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SDValue Cond = N->getOperand(1);
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SDValue Cond = N->getOperand(1);
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@ -488,6 +488,10 @@ public:
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return Has16BitInsts;
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return Has16BitInsts;
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}
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}
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bool hasScalarCompareEq64() const {
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return getGeneration() >= VOLCANIC_ISLANDS;
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}
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bool enableSIScheduler() const {
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bool enableSIScheduler() const {
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return EnableSIScheduler;
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return EnableSIScheduler;
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}
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}
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@ -1930,6 +1930,8 @@ unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
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case AMDGPU::S_CMP_GE_U32: return AMDGPU::V_CMP_GE_U32_e32;
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case AMDGPU::S_CMP_GE_U32: return AMDGPU::V_CMP_GE_U32_e32;
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case AMDGPU::S_CMP_LT_U32: return AMDGPU::V_CMP_LT_U32_e32;
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case AMDGPU::S_CMP_LT_U32: return AMDGPU::V_CMP_LT_U32_e32;
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case AMDGPU::S_CMP_LE_U32: return AMDGPU::V_CMP_LE_U32_e32;
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case AMDGPU::S_CMP_LE_U32: return AMDGPU::V_CMP_LE_U32_e32;
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case AMDGPU::S_CMP_EQ_U64: return AMDGPU::V_CMP_EQ_U64_e32;
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case AMDGPU::S_CMP_LG_U64: return AMDGPU::V_CMP_NE_U64_e32;
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case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
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case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
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case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
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case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
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case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
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case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
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@ -630,6 +630,14 @@ class SOPC_CMP_32<bits<7> op, string opName,
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let isCommutable = 1;
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let isCommutable = 1;
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}
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}
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class SOPC_CMP_64<bits<7> op, string opName,
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PatLeaf cond = COND_NULL, string revOp = opName>
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: SOPC_Helper<op, SSrc_b64, i64, opName, cond>,
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Commutable_REV<revOp, !eq(revOp, opName)> {
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let isCompare = 1;
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let isCommutable = 1;
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}
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class SOPC_32<bits<7> op, string opName, list<dag> pattern = []>
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class SOPC_32<bits<7> op, string opName, list<dag> pattern = []>
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: SOPC_Base<op, SSrc_b32, SSrc_b32, opName, pattern>;
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: SOPC_Base<op, SSrc_b32, SSrc_b32, opName, pattern>;
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@ -655,6 +663,10 @@ def S_BITCMP0_B64 : SOPC_64_32 <0x0e, "s_bitcmp0_b64">;
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def S_BITCMP1_B64 : SOPC_64_32 <0x0f, "s_bitcmp1_b64">;
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def S_BITCMP1_B64 : SOPC_64_32 <0x0f, "s_bitcmp1_b64">;
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def S_SETVSKIP : SOPC_32 <0x10, "s_setvskip">;
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def S_SETVSKIP : SOPC_32 <0x10, "s_setvskip">;
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let SubtargetPredicate = isVI in {
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def S_CMP_EQ_U64 : SOPC_CMP_64 <0x12, "s_cmp_eq_u64", COND_EQ>;
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def S_CMP_LG_U64 : SOPC_CMP_64 <0x13, "s_cmp_lg_u64", COND_NE>;
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// SOPP Instructions
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// SOPP Instructions
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@ -569,5 +569,81 @@ endif:
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ret void
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ret void
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}
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}
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; GCN-LABEL: {{^}}br_scc_eq_i64_inline_imm:
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; VI: s_cmp_eq_u64 s{{\[[0-9]+:[0-9]+\]}}, 4
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; SI: v_cmp_eq_i64_e64
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define void @br_scc_eq_i64_inline_imm(i64 %cond, i32 addrspace(1)* %out) #0 {
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entry:
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%cmp0 = icmp eq i64 %cond, 4
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br i1 %cmp0, label %endif, label %if
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if:
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call void asm sideeffect "", ""()
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br label %endif
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endif:
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store volatile i32 1, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}br_scc_eq_i64_simm16:
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; VI-DAG: s_movk_i32 s[[K_LO:[0-9]+]], 0x4d2
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; VI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0
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; VI: s_cmp_eq_u64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}
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; SI: v_cmp_eq_i64_e32
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define void @br_scc_eq_i64_simm16(i64 %cond, i32 addrspace(1)* %out) #0 {
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entry:
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%cmp0 = icmp eq i64 %cond, 1234
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br i1 %cmp0, label %endif, label %if
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if:
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call void asm sideeffect "", ""()
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br label %endif
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endif:
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store volatile i32 1, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}br_scc_ne_i64_inline_imm:
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; VI: s_cmp_lg_u64 s{{\[[0-9]+:[0-9]+\]}}, 4
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; SI: v_cmp_ne_i64_e64
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define void @br_scc_ne_i64_inline_imm(i64 %cond, i32 addrspace(1)* %out) #0 {
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entry:
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%cmp0 = icmp ne i64 %cond, 4
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br i1 %cmp0, label %endif, label %if
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if:
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call void asm sideeffect "", ""()
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br label %endif
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endif:
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store volatile i32 1, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}br_scc_ne_i64_simm16:
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; VI-DAG: s_movk_i32 s[[K_LO:[0-9]+]], 0x4d2
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; VI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0
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; VI: s_cmp_lg_u64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}
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; SI: v_cmp_ne_i64_e32
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define void @br_scc_ne_i64_simm16(i64 %cond, i32 addrspace(1)* %out) #0 {
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entry:
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%cmp0 = icmp ne i64 %cond, 1234
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br i1 %cmp0, label %endif, label %if
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if:
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call void asm sideeffect "", ""()
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br label %endif
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endif:
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store volatile i32 1, i32 addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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attributes #1 = { nounwind readnone }
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@ -1,16 +1,16 @@
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; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; SI-LABEL: {{^}}uniform_if_scc:
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; GCN-LABEL: {{^}}uniform_if_scc:
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; SI-DAG: s_cmp_eq_i32 s{{[0-9]+}}, 0
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; GCN-DAG: s_cmp_eq_i32 s{{[0-9]+}}, 0
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; SI-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0
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; GCN-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0
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; SI: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]]
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; GCN: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]]
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; Fall-through to the else
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; Fall-through to the else
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; SI: v_mov_b32_e32 [[STORE_VAL]], 1
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; GCN: v_mov_b32_e32 [[STORE_VAL]], 1
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; SI: [[IF_LABEL]]:
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; GCN: [[IF_LABEL]]:
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; SI: buffer_store_dword [[STORE_VAL]]
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; GCN: buffer_store_dword [[STORE_VAL]]
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define void @uniform_if_scc(i32 %cond, i32 addrspace(1)* %out) {
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define void @uniform_if_scc(i32 %cond, i32 addrspace(1)* %out) {
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entry:
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entry:
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%cmp0 = icmp eq i32 %cond, 0
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%cmp0 = icmp eq i32 %cond, 0
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ret void
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ret void
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}
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}
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; SI-LABEL: {{^}}uniform_if_vcc:
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; GCN-LABEL: {{^}}uniform_if_vcc:
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; FIXME: We could use _e32 here if we re-used the 0 from [[STORE_VAL]], and
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; FIXME: We could use _e32 here if we re-used the 0 from [[STORE_VAL]], and
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; also scheduled the write first.
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; also scheduled the write first.
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; SI-DAG: v_cmp_eq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}}
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; GCN-DAG: v_cmp_eq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}}
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; SI-DAG: s_and_b64 vcc, exec, [[COND]]
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; GCN-DAG: s_and_b64 vcc, exec, [[COND]]
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; SI-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0
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; GCN-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0
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; SI: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]]
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; GCN: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]]
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; Fall-through to the else
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; Fall-through to the else
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; SI: v_mov_b32_e32 [[STORE_VAL]], 1
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; GCN: v_mov_b32_e32 [[STORE_VAL]], 1
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; SI: [[IF_LABEL]]:
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; GCN: [[IF_LABEL]]:
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; SI: buffer_store_dword [[STORE_VAL]]
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; GCN: buffer_store_dword [[STORE_VAL]]
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define void @uniform_if_vcc(float %cond, i32 addrspace(1)* %out) {
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define void @uniform_if_vcc(float %cond, i32 addrspace(1)* %out) {
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entry:
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entry:
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%cmp0 = fcmp oeq float %cond, 0.0
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%cmp0 = fcmp oeq float %cond, 0.0
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ret void
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ret void
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}
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}
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; SI-LABEL: {{^}}uniform_if_swap_br_targets_scc:
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; GCN-LABEL: {{^}}uniform_if_swap_br_targets_scc:
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; SI-DAG: s_cmp_lg_i32 s{{[0-9]+}}, 0
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; GCN-DAG: s_cmp_lg_i32 s{{[0-9]+}}, 0
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; SI-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0
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; GCN-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0
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; SI: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]]
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; GCN: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]]
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; Fall-through to the else
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; Fall-through to the else
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; SI: v_mov_b32_e32 [[STORE_VAL]], 1
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; GCN: v_mov_b32_e32 [[STORE_VAL]], 1
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; SI: [[IF_LABEL]]:
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; GCN: [[IF_LABEL]]:
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; SI: buffer_store_dword [[STORE_VAL]]
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; GCN: buffer_store_dword [[STORE_VAL]]
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define void @uniform_if_swap_br_targets_scc(i32 %cond, i32 addrspace(1)* %out) {
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define void @uniform_if_swap_br_targets_scc(i32 %cond, i32 addrspace(1)* %out) {
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entry:
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entry:
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%cmp0 = icmp eq i32 %cond, 0
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%cmp0 = icmp eq i32 %cond, 0
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@ -85,19 +85,19 @@ done:
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ret void
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ret void
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}
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}
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; SI-LABEL: {{^}}uniform_if_swap_br_targets_vcc:
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; GCN-LABEL: {{^}}uniform_if_swap_br_targets_vcc:
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; FIXME: We could use _e32 here if we re-used the 0 from [[STORE_VAL]], and
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; FIXME: We could use _e32 here if we re-used the 0 from [[STORE_VAL]], and
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; also scheduled the write first.
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; also scheduled the write first.
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; SI-DAG: v_cmp_neq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}}
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; GCN-DAG: v_cmp_neq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}}
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; SI-DAG: s_and_b64 vcc, exec, [[COND]]
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; GCN-DAG: s_and_b64 vcc, exec, [[COND]]
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; SI-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0
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; GCN-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0
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; SI: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]]
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; GCN: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]]
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; Fall-through to the else
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; Fall-through to the else
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; SI: v_mov_b32_e32 [[STORE_VAL]], 1
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; GCN: v_mov_b32_e32 [[STORE_VAL]], 1
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; SI: [[IF_LABEL]]:
|
; GCN: [[IF_LABEL]]:
|
||||||
; SI: buffer_store_dword [[STORE_VAL]]
|
; GCN: buffer_store_dword [[STORE_VAL]]
|
||||||
define void @uniform_if_swap_br_targets_vcc(float %cond, i32 addrspace(1)* %out) {
|
define void @uniform_if_swap_br_targets_vcc(float %cond, i32 addrspace(1)* %out) {
|
||||||
entry:
|
entry:
|
||||||
%cmp0 = fcmp oeq float %cond, 0.0
|
%cmp0 = fcmp oeq float %cond, 0.0
|
||||||
|
@ -115,16 +115,16 @@ done:
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|
||||||
; SI-LABEL: {{^}}uniform_if_move_valu:
|
; GCN-LABEL: {{^}}uniform_if_move_valu:
|
||||||
; SI: v_add_f32_e32 [[CMP:v[0-9]+]]
|
; GCN: v_add_f32_e32 [[CMP:v[0-9]+]]
|
||||||
; Using a floating-point value in an integer compare will cause the compare to
|
; Using a floating-point value in an integer compare will cause the compare to
|
||||||
; be selected for the SALU and then later moved to the VALU.
|
; be selected for the SALU and then later moved to the VALU.
|
||||||
; SI: v_cmp_ne_i32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 5, [[CMP]]
|
; GCN: v_cmp_ne_i32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 5, [[CMP]]
|
||||||
; SI: s_and_b64 vcc, exec, [[COND]]
|
; GCN: s_and_b64 vcc, exec, [[COND]]
|
||||||
; SI: s_cbranch_vccnz [[ENDIF_LABEL:[0-9_A-Za-z]+]]
|
; GCN: s_cbranch_vccnz [[ENDIF_LABEL:[0-9_A-Za-z]+]]
|
||||||
; SI: buffer_store_dword
|
; GCN: buffer_store_dword
|
||||||
; SI: [[ENDIF_LABEL]]:
|
; GCN: [[ENDIF_LABEL]]:
|
||||||
; SI: s_endpgm
|
; GCN: s_endpgm
|
||||||
define void @uniform_if_move_valu(i32 addrspace(1)* %out, float %a) {
|
define void @uniform_if_move_valu(i32 addrspace(1)* %out, float %a) {
|
||||||
entry:
|
entry:
|
||||||
%a.0 = fadd float %a, 10.0
|
%a.0 = fadd float %a, 10.0
|
||||||
|
@ -140,16 +140,16 @@ endif:
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|
||||||
; SI-LABEL: {{^}}uniform_if_move_valu_commute:
|
; GCN-LABEL: {{^}}uniform_if_move_valu_commute:
|
||||||
; SI: v_add_f32_e32 [[CMP:v[0-9]+]]
|
; GCN: v_add_f32_e32 [[CMP:v[0-9]+]]
|
||||||
; Using a floating-point value in an integer compare will cause the compare to
|
; Using a floating-point value in an integer compare will cause the compare to
|
||||||
; be selected for the SALU and then later moved to the VALU.
|
; be selected for the SALU and then later moved to the VALU.
|
||||||
; SI: v_cmp_gt_u32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 6, [[CMP]]
|
; GCN: v_cmp_gt_u32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 6, [[CMP]]
|
||||||
; SI: s_and_b64 vcc, exec, [[COND]]
|
; GCN: s_and_b64 vcc, exec, [[COND]]
|
||||||
; SI: s_cbranch_vccnz [[ENDIF_LABEL:[0-9_A-Za-z]+]]
|
; GCN: s_cbranch_vccnz [[ENDIF_LABEL:[0-9_A-Za-z]+]]
|
||||||
; SI: buffer_store_dword
|
; GCN: buffer_store_dword
|
||||||
; SI: [[ENDIF_LABEL]]:
|
; GCN: [[ENDIF_LABEL]]:
|
||||||
; SI: s_endpgm
|
; GCN: s_endpgm
|
||||||
define void @uniform_if_move_valu_commute(i32 addrspace(1)* %out, float %a) {
|
define void @uniform_if_move_valu_commute(i32 addrspace(1)* %out, float %a) {
|
||||||
entry:
|
entry:
|
||||||
%a.0 = fadd float %a, 10.0
|
%a.0 = fadd float %a, 10.0
|
||||||
|
@ -166,18 +166,18 @@ endif:
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
; SI-LABEL: {{^}}uniform_if_else_ret:
|
; GCN-LABEL: {{^}}uniform_if_else_ret:
|
||||||
; SI: s_cmp_lg_i32 s{{[0-9]+}}, 0
|
; GCN: s_cmp_lg_i32 s{{[0-9]+}}, 0
|
||||||
; SI-NEXT: s_cbranch_scc0 [[IF_LABEL:[0-9_A-Za-z]+]]
|
; GCN-NEXT: s_cbranch_scc0 [[IF_LABEL:[0-9_A-Za-z]+]]
|
||||||
|
|
||||||
; SI: v_mov_b32_e32 [[TWO:v[0-9]+]], 2
|
; GCN: v_mov_b32_e32 [[TWO:v[0-9]+]], 2
|
||||||
; SI: buffer_store_dword [[TWO]]
|
; GCN: buffer_store_dword [[TWO]]
|
||||||
; SI: s_endpgm
|
; GCN: s_endpgm
|
||||||
|
|
||||||
; SI: {{^}}[[IF_LABEL]]:
|
; GCN: {{^}}[[IF_LABEL]]:
|
||||||
; SI: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
|
; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
|
||||||
; SI: buffer_store_dword [[ONE]]
|
; GCN: buffer_store_dword [[ONE]]
|
||||||
; SI: s_endpgm
|
; GCN: s_endpgm
|
||||||
define void @uniform_if_else_ret(i32 addrspace(1)* nocapture %out, i32 %a) {
|
define void @uniform_if_else_ret(i32 addrspace(1)* nocapture %out, i32 %a) {
|
||||||
entry:
|
entry:
|
||||||
%cmp = icmp eq i32 %a, 0
|
%cmp = icmp eq i32 %a, 0
|
||||||
|
@ -195,22 +195,22 @@ if.end: ; preds = %if.else, %if.then
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|
||||||
; SI-LABEL: {{^}}uniform_if_else:
|
; GCN-LABEL: {{^}}uniform_if_else:
|
||||||
; SI: s_cmp_lg_i32 s{{[0-9]+}}, 0
|
; GCN: s_cmp_lg_i32 s{{[0-9]+}}, 0
|
||||||
; SI-NEXT: s_cbranch_scc0 [[IF_LABEL:[0-9_A-Za-z]+]]
|
; GCN-NEXT: s_cbranch_scc0 [[IF_LABEL:[0-9_A-Za-z]+]]
|
||||||
|
|
||||||
; SI: v_mov_b32_e32 [[TWO:v[0-9]+]], 2
|
; GCN: v_mov_b32_e32 [[TWO:v[0-9]+]], 2
|
||||||
; SI: buffer_store_dword [[TWO]]
|
; GCN: buffer_store_dword [[TWO]]
|
||||||
; SI: s_branch [[ENDIF_LABEL:[0-9_A-Za-z]+]]
|
; GCN: s_branch [[ENDIF_LABEL:[0-9_A-Za-z]+]]
|
||||||
|
|
||||||
; SI: [[IF_LABEL]]:
|
; GCN: [[IF_LABEL]]:
|
||||||
; SI: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
|
; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
|
||||||
; SI: buffer_store_dword [[ONE]]
|
; GCN: buffer_store_dword [[ONE]]
|
||||||
|
|
||||||
; SI: [[ENDIF_LABEL]]:
|
; GCN: [[ENDIF_LABEL]]:
|
||||||
; SI: v_mov_b32_e32 [[THREE:v[0-9]+]], 3
|
; GCN: v_mov_b32_e32 [[THREE:v[0-9]+]], 3
|
||||||
; SI: buffer_store_dword [[THREE]]
|
; GCN: buffer_store_dword [[THREE]]
|
||||||
; SI: s_endpgm
|
; GCN: s_endpgm
|
||||||
define void @uniform_if_else(i32 addrspace(1)* nocapture %out0, i32 addrspace(1)* nocapture %out1, i32 %a) {
|
define void @uniform_if_else(i32 addrspace(1)* nocapture %out0, i32 addrspace(1)* nocapture %out1, i32 %a) {
|
||||||
entry:
|
entry:
|
||||||
%cmp = icmp eq i32 %a, 0
|
%cmp = icmp eq i32 %a, 0
|
||||||
|
@ -229,12 +229,12 @@ if.end: ; preds = %if.else, %if.then
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|
||||||
; SI-LABEL: {{^}}icmp_2_users:
|
; GCN-LABEL: {{^}}icmp_2_users:
|
||||||
; SI: s_cmp_lt_i32 s{{[0-9]+}}, 1
|
; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 1
|
||||||
; SI: s_cbranch_scc1 [[LABEL:[a-zA-Z0-9_]+]]
|
; GCN: s_cbranch_scc1 [[LABEL:[a-zA-Z0-9_]+]]
|
||||||
; SI: buffer_store_dword
|
; GCN: buffer_store_dword
|
||||||
; SI: [[LABEL]]:
|
; GCN: [[LABEL]]:
|
||||||
; SI: s_endpgm
|
; GCN: s_endpgm
|
||||||
define void @icmp_2_users(i32 addrspace(1)* %out, i32 %cond) {
|
define void @icmp_2_users(i32 addrspace(1)* %out, i32 %cond) {
|
||||||
main_body:
|
main_body:
|
||||||
%0 = icmp sgt i32 %cond, 0
|
%0 = icmp sgt i32 %cond, 0
|
||||||
|
@ -249,16 +249,16 @@ ENDIF: ; preds = %IF, %main_body
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|
||||||
; SI-LABEL: {{^}}icmp_users_different_blocks:
|
; GCN-LABEL: {{^}}icmp_users_different_blocks:
|
||||||
; SI: s_load_dword [[COND:s[0-9]+]]
|
; GCN: s_load_dword [[COND:s[0-9]+]]
|
||||||
; SI: s_cmp_lt_i32 [[COND]], 1
|
; GCN: s_cmp_lt_i32 [[COND]], 1
|
||||||
; SI: s_cbranch_scc1 [[EXIT:[A-Za-z0-9_]+]]
|
; GCN: s_cbranch_scc1 [[EXIT:[A-Za-z0-9_]+]]
|
||||||
; SI: v_cmp_gt_i32_e64 [[MASK:s\[[0-9]+:[0-9]+\]]], [[COND]], 0{{$}}
|
; GCN: v_cmp_gt_i32_e64 [[MASK:s\[[0-9]+:[0-9]+\]]], [[COND]], 0{{$}}
|
||||||
; SI: s_and_b64 vcc, exec, [[MASK]]
|
; GCN: s_and_b64 vcc, exec, [[MASK]]
|
||||||
; SI: s_cbranch_vccnz [[EXIT]]
|
; GCN: s_cbranch_vccnz [[EXIT]]
|
||||||
; SI: buffer_store
|
; GCN: buffer_store
|
||||||
; SI: {{^}}[[EXIT]]:
|
; GCN: {{^}}[[EXIT]]:
|
||||||
; SI: s_endpgm
|
; GCN: s_endpgm
|
||||||
define void @icmp_users_different_blocks(i32 %cond0, i32 %cond1, i32 addrspace(1)* %out) {
|
define void @icmp_users_different_blocks(i32 %cond0, i32 %cond1, i32 addrspace(1)* %out) {
|
||||||
bb:
|
bb:
|
||||||
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
||||||
|
@ -279,15 +279,15 @@ bb9: ; preds = %bb8, %bb4
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|
||||||
; SI-LABEL: {{^}}uniform_loop:
|
; GCN-LABEL: {{^}}uniform_loop:
|
||||||
; SI: {{^}}[[LOOP_LABEL:[A-Z0-9_a-z]+]]:
|
; GCN: {{^}}[[LOOP_LABEL:[A-Z0-9_a-z]+]]:
|
||||||
; FIXME: We need to teach SIFixSGPRCopies about uniform branches so we
|
; FIXME: We need to teach GCNFixSGPRCopies about uniform branches so we
|
||||||
; get s_add_i32 here.
|
; get s_add_i32 here.
|
||||||
; SI: v_add_i32_e32 [[I:v[0-9]+]], vcc, -1, v{{[0-9]+}}
|
; GCN: v_add_i32_e32 [[I:v[0-9]+]], vcc, -1, v{{[0-9]+}}
|
||||||
; SI: v_cmp_ne_i32_e32 vcc, 0, [[I]]
|
; GCN: v_cmp_ne_i32_e32 vcc, 0, [[I]]
|
||||||
; SI: s_and_b64 vcc, exec, vcc
|
; GCN: s_and_b64 vcc, exec, vcc
|
||||||
; SI: s_cbranch_vccnz [[LOOP_LABEL]]
|
; GCN: s_cbranch_vccnz [[LOOP_LABEL]]
|
||||||
; SI: s_endpgm
|
; GCN: s_endpgm
|
||||||
define void @uniform_loop(i32 addrspace(1)* %out, i32 %a) {
|
define void @uniform_loop(i32 addrspace(1)* %out, i32 %a) {
|
||||||
entry:
|
entry:
|
||||||
br label %loop
|
br label %loop
|
||||||
|
@ -304,15 +304,15 @@ done:
|
||||||
|
|
||||||
; Test uniform and divergent.
|
; Test uniform and divergent.
|
||||||
|
|
||||||
; SI-LABEL: {{^}}uniform_inside_divergent:
|
; GCN-LABEL: {{^}}uniform_inside_divergent:
|
||||||
; SI: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}}
|
; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}}
|
||||||
; SI: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
|
; GCN: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
|
||||||
; SI: s_xor_b64 [[MASK1:s\[[0-9]+:[0-9]+\]]], exec, [[MASK]]
|
; GCN: s_xor_b64 [[MASK1:s\[[0-9]+:[0-9]+\]]], exec, [[MASK]]
|
||||||
; SI: s_cbranch_execz [[ENDIF_LABEL:[0-9_A-Za-z]+]]
|
; GCN: s_cbranch_execz [[ENDIF_LABEL:[0-9_A-Za-z]+]]
|
||||||
; SI: s_cmp_lg_i32 {{s[0-9]+}}, 0
|
; GCN: s_cmp_lg_i32 {{s[0-9]+}}, 0
|
||||||
; SI: s_cbranch_scc1 [[ENDIF_LABEL]]
|
; GCN: s_cbranch_scc1 [[ENDIF_LABEL]]
|
||||||
; SI: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
|
; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
|
||||||
; SI: buffer_store_dword [[ONE]]
|
; GCN: buffer_store_dword [[ONE]]
|
||||||
define void @uniform_inside_divergent(i32 addrspace(1)* %out, i32 %cond) {
|
define void @uniform_inside_divergent(i32 addrspace(1)* %out, i32 %cond) {
|
||||||
entry:
|
entry:
|
||||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
|
%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
|
||||||
|
@ -332,16 +332,16 @@ endif:
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|
||||||
; SI-LABEL: {{^}}divergent_inside_uniform:
|
; GCN-LABEL: {{^}}divergent_inside_uniform:
|
||||||
; SI: s_cmp_lg_i32 s{{[0-9]+}}, 0
|
; GCN: s_cmp_lg_i32 s{{[0-9]+}}, 0
|
||||||
; SI: s_cbranch_scc1 [[ENDIF_LABEL:[0-9_A-Za-z]+]]
|
; GCN: s_cbranch_scc1 [[ENDIF_LABEL:[0-9_A-Za-z]+]]
|
||||||
; SI: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}}
|
; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}}
|
||||||
; SI: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
|
; GCN: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
|
||||||
; SI: s_xor_b64 [[MASK1:s\[[0-9]+:[0-9]+\]]], exec, [[MASK]]
|
; GCN: s_xor_b64 [[MASK1:s\[[0-9]+:[0-9]+\]]], exec, [[MASK]]
|
||||||
; SI: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
|
; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
|
||||||
; SI: buffer_store_dword [[ONE]]
|
; GCN: buffer_store_dword [[ONE]]
|
||||||
; SI: [[ENDIF_LABEL]]:
|
; GCN: [[ENDIF_LABEL]]:
|
||||||
; SI: s_endpgm
|
; GCN: s_endpgm
|
||||||
define void @divergent_inside_uniform(i32 addrspace(1)* %out, i32 %cond) {
|
define void @divergent_inside_uniform(i32 addrspace(1)* %out, i32 %cond) {
|
||||||
entry:
|
entry:
|
||||||
%u_cmp = icmp eq i32 %cond, 0
|
%u_cmp = icmp eq i32 %cond, 0
|
||||||
|
@ -361,19 +361,19 @@ endif:
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|
||||||
; SI-LABEL: {{^}}divergent_if_uniform_if:
|
; GCN-LABEL: {{^}}divergent_if_uniform_if:
|
||||||
; SI: v_cmp_eq_i32_e32 vcc, 0, v0
|
; GCN: v_cmp_eq_i32_e32 vcc, 0, v0
|
||||||
; SI: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
|
; GCN: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
|
||||||
; SI: s_xor_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], exec, [[MASK]]
|
; GCN: s_xor_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], exec, [[MASK]]
|
||||||
; SI: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
|
; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
|
||||||
; SI: buffer_store_dword [[ONE]]
|
; GCN: buffer_store_dword [[ONE]]
|
||||||
; SI: s_or_b64 exec, exec, [[MASK]]
|
; GCN: s_or_b64 exec, exec, [[MASK]]
|
||||||
; SI: s_cmp_lg_i32 s{{[0-9]+}}, 0
|
; GCN: s_cmp_lg_i32 s{{[0-9]+}}, 0
|
||||||
; SI: s_cbranch_scc1 [[EXIT:[A-Z0-9_]+]]
|
; GCN: s_cbranch_scc1 [[EXIT:[A-Z0-9_]+]]
|
||||||
; SI: v_mov_b32_e32 [[TWO:v[0-9]+]], 2
|
; GCN: v_mov_b32_e32 [[TWO:v[0-9]+]], 2
|
||||||
; SI: buffer_store_dword [[TWO]]
|
; GCN: buffer_store_dword [[TWO]]
|
||||||
; SI: [[EXIT]]:
|
; GCN: [[EXIT]]:
|
||||||
; SI: s_endpgm
|
; GCN: s_endpgm
|
||||||
define void @divergent_if_uniform_if(i32 addrspace(1)* %out, i32 %cond) {
|
define void @divergent_if_uniform_if(i32 addrspace(1)* %out, i32 %cond) {
|
||||||
entry:
|
entry:
|
||||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
|
%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
|
||||||
|
@ -401,19 +401,19 @@ exit:
|
||||||
; the first, leaving an scc use in a different block than it was
|
; the first, leaving an scc use in a different block than it was
|
||||||
; defed.
|
; defed.
|
||||||
|
|
||||||
; SI-LABEL: {{^}}cse_uniform_condition_different_blocks:
|
; GCN-LABEL: {{^}}cse_uniform_condition_different_blocks:
|
||||||
; SI: s_load_dword [[COND:s[0-9]+]]
|
; GCN: s_load_dword [[COND:s[0-9]+]]
|
||||||
; SI: s_cmp_lt_i32 [[COND]], 1
|
; GCN: s_cmp_lt_i32 [[COND]], 1
|
||||||
; SI: s_cbranch_scc1 BB[[FNNUM:[0-9]+]]_3
|
; GCN: s_cbranch_scc1 BB[[FNNUM:[0-9]+]]_3
|
||||||
|
|
||||||
; SI: BB#1:
|
; GCN: BB#1:
|
||||||
; SI-NOT: cmp
|
; GCN-NOT: cmp
|
||||||
; SI: buffer_load_dword
|
; GCN: buffer_load_dword
|
||||||
; SI: buffer_store_dword
|
; GCN: buffer_store_dword
|
||||||
; SI: s_cbranch_scc1 BB[[FNNUM]]_3
|
; GCN: s_cbranch_scc1 BB[[FNNUM]]_3
|
||||||
|
|
||||||
; SI: BB[[FNNUM]]_3:
|
; GCN: BB[[FNNUM]]_3:
|
||||||
; SI: s_endpgm
|
; GCN: s_endpgm
|
||||||
define void @cse_uniform_condition_different_blocks(i32 %cond, i32 addrspace(1)* %out) {
|
define void @cse_uniform_condition_different_blocks(i32 %cond, i32 addrspace(1)* %out) {
|
||||||
bb:
|
bb:
|
||||||
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
||||||
|
@ -434,6 +434,137 @@ bb9: ; preds = %bb8, %bb4
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|
||||||
|
; GCN-LABEL: {{^}}uniform_if_scc_i64_eq:
|
||||||
|
; VI-DAG: s_cmp_eq_u64 s{{\[[0-9]+:[0-9]+\]}}, 0
|
||||||
|
; GCN-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0
|
||||||
|
|
||||||
|
; SI: v_cmp_eq_i64_e64
|
||||||
|
; SI: s_and_b64 vcc, exec,
|
||||||
|
; SI: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]]
|
||||||
|
|
||||||
|
; VI: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]]
|
||||||
|
|
||||||
|
; Fall-through to the else
|
||||||
|
; GCN: v_mov_b32_e32 [[STORE_VAL]], 1
|
||||||
|
|
||||||
|
; GCN: [[IF_LABEL]]:
|
||||||
|
; GCN: buffer_store_dword [[STORE_VAL]]
|
||||||
|
define void @uniform_if_scc_i64_eq(i64 %cond, i32 addrspace(1)* %out) {
|
||||||
|
entry:
|
||||||
|
%cmp0 = icmp eq i64 %cond, 0
|
||||||
|
br i1 %cmp0, label %if, label %else
|
||||||
|
|
||||||
|
if:
|
||||||
|
br label %done
|
||||||
|
|
||||||
|
else:
|
||||||
|
br label %done
|
||||||
|
|
||||||
|
done:
|
||||||
|
%value = phi i32 [0, %if], [1, %else]
|
||||||
|
store i32 %value, i32 addrspace(1)* %out
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
; GCN-LABEL: {{^}}uniform_if_scc_i64_ne:
|
||||||
|
; VI-DAG: s_cmp_lg_u64 s{{\[[0-9]+:[0-9]+\]}}, 0
|
||||||
|
; GCN-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0
|
||||||
|
|
||||||
|
; SI: v_cmp_ne_i64_e64
|
||||||
|
; SI: s_and_b64 vcc, exec,
|
||||||
|
; SI: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]]
|
||||||
|
|
||||||
|
; VI: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]]
|
||||||
|
|
||||||
|
; Fall-through to the else
|
||||||
|
; GCN: v_mov_b32_e32 [[STORE_VAL]], 1
|
||||||
|
|
||||||
|
; GCN: [[IF_LABEL]]:
|
||||||
|
; GCN: buffer_store_dword [[STORE_VAL]]
|
||||||
|
define void @uniform_if_scc_i64_ne(i64 %cond, i32 addrspace(1)* %out) {
|
||||||
|
entry:
|
||||||
|
%cmp0 = icmp ne i64 %cond, 0
|
||||||
|
br i1 %cmp0, label %if, label %else
|
||||||
|
|
||||||
|
if:
|
||||||
|
br label %done
|
||||||
|
|
||||||
|
else:
|
||||||
|
br label %done
|
||||||
|
|
||||||
|
done:
|
||||||
|
%value = phi i32 [0, %if], [1, %else]
|
||||||
|
store i32 %value, i32 addrspace(1)* %out
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
; GCN-LABEL: {{^}}uniform_if_scc_i64_sgt:
|
||||||
|
; GCN: v_cmp_gt_i64_e64
|
||||||
|
; GCN: s_and_b64 vcc, exec,
|
||||||
|
; GCN: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]]
|
||||||
|
|
||||||
|
; Fall-through to the else
|
||||||
|
; GCN: v_mov_b32_e32 [[STORE_VAL]], 1
|
||||||
|
|
||||||
|
; GCN: [[IF_LABEL]]:
|
||||||
|
; GCN: buffer_store_dword [[STORE_VAL]]
|
||||||
|
define void @uniform_if_scc_i64_sgt(i64 %cond, i32 addrspace(1)* %out) {
|
||||||
|
entry:
|
||||||
|
%cmp0 = icmp sgt i64 %cond, 0
|
||||||
|
br i1 %cmp0, label %if, label %else
|
||||||
|
|
||||||
|
if:
|
||||||
|
br label %done
|
||||||
|
|
||||||
|
else:
|
||||||
|
br label %done
|
||||||
|
|
||||||
|
done:
|
||||||
|
%value = phi i32 [0, %if], [1, %else]
|
||||||
|
store i32 %value, i32 addrspace(1)* %out
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
; GCN-LABEL: {{^}}move_to_valu_i64_eq:
|
||||||
|
; SI: v_cmp_eq_i64_e32
|
||||||
|
; VI: v_cmp_eq_u64_e32
|
||||||
|
define void @move_to_valu_i64_eq(i32 addrspace(1)* %out) {
|
||||||
|
%cond = load volatile i64, i64 addrspace(3)* undef
|
||||||
|
%cmp0 = icmp eq i64 %cond, 0
|
||||||
|
br i1 %cmp0, label %if, label %else
|
||||||
|
|
||||||
|
if:
|
||||||
|
br label %done
|
||||||
|
|
||||||
|
else:
|
||||||
|
br label %done
|
||||||
|
|
||||||
|
done:
|
||||||
|
%value = phi i32 [0, %if], [1, %else]
|
||||||
|
store i32 %value, i32 addrspace(1)* %out
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
; GCN-LABEL: {{^}}move_to_valu_i64_ne:
|
||||||
|
; SI: v_cmp_ne_i64_e32
|
||||||
|
; VI: v_cmp_ne_u64_e32
|
||||||
|
define void @move_to_valu_i64_ne(i32 addrspace(1)* %out) {
|
||||||
|
%cond = load volatile i64, i64 addrspace(3)* undef
|
||||||
|
%cmp0 = icmp ne i64 %cond, 0
|
||||||
|
br i1 %cmp0, label %if, label %else
|
||||||
|
|
||||||
|
if:
|
||||||
|
br label %done
|
||||||
|
|
||||||
|
else:
|
||||||
|
br label %done
|
||||||
|
|
||||||
|
done:
|
||||||
|
%value = phi i32 [0, %if], [1, %else]
|
||||||
|
store i32 %value, i32 addrspace(1)* %out
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
declare i32 @llvm.amdgcn.workitem.id.x() #0
|
declare i32 @llvm.amdgcn.workitem.id.x() #0
|
||||||
|
|
||||||
attributes #0 = { readnone }
|
attributes #0 = { nounwind readnone }
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefix=GCN %s
|
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=SICI %s
|
||||||
// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck --check-prefix=GCN %s
|
// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
|
||||||
// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefix=GCN %s
|
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSICI %s
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
// SOPC Instructions
|
// SOPC Instructions
|
||||||
|
@ -56,3 +56,11 @@ s_bitcmp1_b64 s[2:3], s4
|
||||||
|
|
||||||
s_setvskip s3, s5
|
s_setvskip s3, s5
|
||||||
// GCN: s_setvskip s3, s5 ; encoding: [0x03,0x05,0x10,0xbf]
|
// GCN: s_setvskip s3, s5 ; encoding: [0x03,0x05,0x10,0xbf]
|
||||||
|
|
||||||
|
s_cmp_eq_u64 s[0:1], s[2:3]
|
||||||
|
// VI: s_cmp_eq_u64 s[0:1], s[2:3] ; encoding: [0x00,0x02,0x12,0xbf]
|
||||||
|
// NOSICI: error: instruction not supported on this GPU
|
||||||
|
|
||||||
|
s_cmp_lg_u64 s[0:1], s[2:3]
|
||||||
|
// VI: s_cmp_lg_u64 s[0:1], s[2:3] ; encoding: [0x00,0x02,0x13,0xbf]
|
||||||
|
// NOSICI: error: instruction not supported on this GPU
|
||||||
|
|
Loading…
Reference in New Issue