[AArch64] Fix some coding standard issues related to namespace llvm

https://llvm.org/docs/CodingStandards.html#use-namespace-qualifiers-to-implement-previously-declared-functions

llvm/lib/Target/AArch64/AArch64ExpandImm.cpp

@@ -14,9 +14,8 @@
 #include "AArch64ExpandImm.h"
 #include "MCTargetDesc/AArch64AddressingModes.h"
 
-namespace llvm {
-
-namespace AArch64_IMM {
+using namespace llvm;
+using namespace llvm::AArch64_IMM;
 
 /// Helper function which extracts the specified 16-bit chunk from a
 /// 64-bit value.
@@ -302,8 +301,8 @@ static inline void expandMOVImmSimple(uint64_t Imm, unsigned BitSize,
 
 /// Expand a MOVi32imm or MOVi64imm pseudo instruction to one or more
 /// real move-immediate instructions to synthesize the immediate.
-void expandMOVImm(uint64_t Imm, unsigned BitSize,
-		  SmallVectorImpl<ImmInsnModel> &Insn) {
+void AArch64_IMM::expandMOVImm(uint64_t Imm, unsigned BitSize,
+                               SmallVectorImpl<ImmInsnModel> &Insn) {
   const unsigned Mask = 0xFFFF;
 
   // Scan the immediate and count the number of 16-bit chunks which are either
@@ -405,7 +404,3 @@ void expandMOVImm(uint64_t Imm, unsigned BitSize,
   // four-instruction sequence.
   expandMOVImmSimple(Imm, BitSize, OneChunks, ZeroChunks, Insn);
 }
-
-} // end namespace AArch64_AM
-
-} // end namespace llvm

llvm/lib/Target/AArch64/AArch64FastISel.cpp

@@ -5094,11 +5094,7 @@ bool AArch64FastISel::fastSelectInstruction(const Instruction *I) {
   return selectOperator(I, I->getOpcode());
 }
 
-namespace llvm {
-
 FastISel *AArch64::createFastISel(FunctionLoweringInfo &FuncInfo,
                                         const TargetLibraryInfo *LibInfo) {
   return new AArch64FastISel(FuncInfo, LibInfo);
 }
-
-} // end namespace llvm

llvm/lib/Target/AArch64/AArch64MacroFusion.cpp

@@ -11,14 +11,13 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "AArch64MacroFusion.h"
 #include "AArch64Subtarget.h"
 #include "llvm/CodeGen/MacroFusion.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 
 using namespace llvm;
 
-namespace {
-
 /// CMN, CMP, TST followed by Bcc
 static bool isArithmeticBccPair(const MachineInstr *FirstMI,
                                 const MachineInstr &SecondMI, bool CmpOnly) {
@@ -410,13 +409,7 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
   return false;
 }
 
-} // end namespace
-
-
-namespace llvm {
-
-std::unique_ptr<ScheduleDAGMutation> createAArch64MacroFusionDAGMutation () {
+std::unique_ptr<ScheduleDAGMutation>
+llvm::createAArch64MacroFusionDAGMutation() {
   return createMacroFusionDAGMutation(shouldScheduleAdjacent);
 }
-
-} // end namespace llvm

llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp

@@ -203,6 +203,7 @@ void AArch64StackTaggingPreRA::uncheckLoadsAndStores() {
   }
 }
 
+namespace {
 struct SlotWithTag {
   int FI;
   int Tag;
@@ -213,6 +214,7 @@ struct SlotWithTag {
     return FI == Other.FI && Tag == Other.Tag;
   }
 };
+} // namespace
 
 namespace llvm {
 template <> struct DenseMapInfo<SlotWithTag> {

llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp

@@ -12,6 +12,8 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "AArch64ELFStreamer.h"
+#include "AArch64MCTargetDesc.h"
 #include "AArch64TargetStreamer.h"
 #include "AArch64WinCOFFStreamer.h"
 #include "llvm/ADT/DenseMap.h"
@@ -243,8 +245,6 @@ private:
 
 } // end anonymous namespace
 
-namespace llvm {
-
 AArch64ELFStreamer &AArch64TargetELFStreamer::getStreamer() {
   return static_cast<AArch64ELFStreamer &>(Streamer);
 }
@@ -257,23 +257,20 @@ void AArch64TargetELFStreamer::emitDirectiveVariantPCS(MCSymbol *Symbol) {
   cast<MCSymbolELF>(Symbol)->setOther(ELF::STO_AARCH64_VARIANT_PCS);
 }
 
-MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S,
-                                                 formatted_raw_ostream &OS,
-                                                 MCInstPrinter *InstPrint,
-                                                 bool isVerboseAsm) {
+MCTargetStreamer *
+llvm::createAArch64AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS,
+                                     MCInstPrinter *InstPrint,
+                                     bool isVerboseAsm) {
   return new AArch64TargetAsmStreamer(S, OS);
 }
 
-MCELFStreamer *createAArch64ELFStreamer(MCContext &Context,
-                                        std::unique_ptr<MCAsmBackend> TAB,
-                                        std::unique_ptr<MCObjectWriter> OW,
-                                        std::unique_ptr<MCCodeEmitter> Emitter,
-                                        bool RelaxAll) {
+MCELFStreamer *llvm::createAArch64ELFStreamer(
+    MCContext &Context, std::unique_ptr<MCAsmBackend> TAB,
+    std::unique_ptr<MCObjectWriter> OW, std::unique_ptr<MCCodeEmitter> Emitter,
+    bool RelaxAll) {
   AArch64ELFStreamer *S = new AArch64ELFStreamer(
       Context, std::move(TAB), std::move(OW), std::move(Emitter));
   if (RelaxAll)
     S->getAssembler().setRelaxAll(true);
   return S;
 }
-
-} // end namespace llvm

llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp

@@ -107,10 +107,9 @@ void AArch64TargetStreamer::emitInst(uint32_t Inst) {
   getStreamer().emitBytes(StringRef(Buffer, 4));
 }
 
-namespace llvm {
-
 MCTargetStreamer *
-createAArch64ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
+llvm::createAArch64ObjectTargetStreamer(MCStreamer &S,
+                                        const MCSubtargetInfo &STI) {
   const Triple &TT = STI.getTargetTriple();
   if (TT.isOSBinFormatELF())
     return new AArch64TargetELFStreamer(S);
@@ -118,5 +117,3 @@ createAArch64ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
     return new AArch64TargetWinCOFFStreamer(S);
   return nullptr;
 }
-
-} // end namespace llvm

llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp

@@ -6,6 +6,7 @@
 //
 //===---------------------------------------------------------------------===//
 
+#include "AArch64MCTargetDesc.h"
 #include "MCTargetDesc/AArch64FixupKinds.h"
 #include "MCTargetDesc/AArch64MCExpr.h"
 #include "llvm/ADT/Twine.h"
@@ -153,10 +154,6 @@ bool AArch64WinCOFFObjectWriter::recordRelocation(const MCFixup &Fixup) const {
   return true;
 }
 
-namespace llvm {
-
-std::unique_ptr<MCObjectTargetWriter> createAArch64WinCOFFObjectWriter() {
+std::unique_ptr<MCObjectTargetWriter> llvm::createAArch64WinCOFFObjectWriter() {
   return std::make_unique<AArch64WinCOFFObjectWriter>();
 }
-
-} // end namespace llvm

llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp

@@ -59,8 +59,6 @@ void AArch64WinCOFFStreamer::finishImpl() {
 }
 } // end anonymous namespace
 
-namespace llvm {
-
 // Helper function to common out unwind code setup for those codes that can
 // belong to both prolog and epilog.
 // There are three types of Windows ARM64 SEH codes.  They can
@@ -223,7 +221,7 @@ void AArch64TargetWinCOFFStreamer::EmitARM64WinCFIClearUnwoundToCall() {
   EmitARM64WinUnwindCode(Win64EH::UOP_ClearUnwoundToCall, -1, 0);
 }
 
-MCWinCOFFStreamer *createAArch64WinCOFFStreamer(
+MCWinCOFFStreamer *llvm::createAArch64WinCOFFStreamer(
     MCContext &Context, std::unique_ptr<MCAsmBackend> MAB,
     std::unique_ptr<MCObjectWriter> OW, std::unique_ptr<MCCodeEmitter> Emitter,
     bool RelaxAll, bool IncrementalLinkerCompatible) {
@@ -232,5 +230,3 @@ MCWinCOFFStreamer *createAArch64WinCOFFStreamer(
   S->getAssembler().setIncrementalLinkerCompatible(IncrementalLinkerCompatible);
   return S;
 }
-
-} // end llvm namespace