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AMDGPU: Fix isTypeDesirableForOp for i16 

This should do nothing for targets without i16.

llvm-svn: 289235
This commit is contained in:
Matt Arsenault 2016-12-09 17:57:43 +00:00
parent 6ea7a7a310
commit 7b00cf4706
1 changed files with 15 additions and 3 deletions
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18
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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@ -658,10 +658,22 @@ bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
}
bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
if (Subtarget->has16BitInsts() && VT == MVT::i16) {
switch (Op) {
case ISD::LOAD:
case ISD::STORE:
// i16 is not desirable unless it is a load or a store.
if (VT == MVT::i16 && Op != ISD::LOAD && Op != ISD::STORE)
return false;
// These operations are done with 32-bit instructions anyway.
case ISD::AND:
case ISD::OR:
case ISD::XOR:
case ISD::SELECT:
// TODO: Extensions?
return true;
default:
return false;
}
}
// SimplifySetCC uses this function to determine whether or not it should
// create setcc with i1 operands. We don't have instructions for i1 setcc.