forked from OSchip/llvm-project
[RISCV] Add more sign-extending ops to MIR sext.w pass.
This patch adds single-bit and bit-counting ops to list of sign-extending ops. A single-bit write propagates sign-extendedness if it's not in the sign-bits. Bit extraction and bit counting always outputs a small number, so sign-extended. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D121152
This commit is contained in:
Mohammed Nurul Hoque
Kito Cheng
parent
53491e4519
commit
7afa44f5f5
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@ -91,7 +91,7 @@ static bool isSignExtendingOpW(const MachineInstr &MI) {
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case RISCV::FCVT_WU_D:
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case RISCV::FMV_X_W:
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// The following aren't W instructions, but are either sign extended from a
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// smaller size or put zeros in bits 63:31.
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// smaller size, always outputs a small integer, or put zeros in bits 63:31.
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case RISCV::LBU:
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case RISCV::LHU:
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case RISCV::LB:
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@ -104,6 +104,11 @@ static bool isSignExtendingOpW(const MachineInstr &MI) {
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case RISCV::SEXT_H:
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case RISCV::ZEXT_H_RV64:
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case RISCV::FMV_X_H:
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case RISCV::BEXT:
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case RISCV::BEXTI:
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case RISCV::CLZ:
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case RISCV::CPOP:
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case RISCV::CTZ:
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return true;
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// shifting right sufficiently makes the value 32-bit sign-extended
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case RISCV::SRAI:
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@ -167,14 +172,21 @@ static bool isSignExtendedW(const MachineInstr &OrigMI,
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Worklist.push_back(SrcMI);
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break;
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}
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// For these, we just need to check if the 1st operand is sign extended.
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case RISCV::BCLRI:
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case RISCV::BINVI:
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case RISCV::BSETI:
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if (MI->getOperand(2).getImm() >= 31)
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return false;
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LLVM_FALLTHROUGH;
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case RISCV::REM:
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case RISCV::ANDI:
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case RISCV::ORI:
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case RISCV::XORI: {
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// |Remainder| is always <= |Dividend|. If D is 32-bit, then so is R.
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// DIV doesn't work because of the edge case 0xf..f 8000 0000 / (long)-1
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// Logical operations use a sign extended 12-bit immediate. We just need
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// to check if the other operand is sign extended.
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// Logical operations use a sign extended 12-bit immediate.
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Register SrcReg = MI->getOperand(1).getReg();
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if (!SrcReg.isVirtual())
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return false;
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@ -315,17 +315,108 @@ bb7: ; preds = %bb2
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}
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declare float @baz(i32 signext %i3)
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define void @test7(i32 signext %arg, i32 signext %arg1) nounwind {
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; RV64I-LABEL: test7:
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; RV64I: # %bb.0: # %bb
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; RV64I-NEXT: addi sp, sp, -48
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; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: lui a2, %hi(.LCPI6_0)
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; RV64I-NEXT: ld s0, %lo(.LCPI6_0)(a2)
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; RV64I-NEXT: lui a2, %hi(.LCPI6_1)
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; RV64I-NEXT: ld s1, %lo(.LCPI6_1)(a2)
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; RV64I-NEXT: lui a2, %hi(.LCPI6_2)
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; RV64I-NEXT: ld s2, %lo(.LCPI6_2)(a2)
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; RV64I-NEXT: lui a2, %hi(.LCPI6_3)
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; RV64I-NEXT: ld s3, %lo(.LCPI6_3)(a2)
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; RV64I-NEXT: sraw a0, a0, a1
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; RV64I-NEXT: .LBB6_1: # %bb2
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; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
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; RV64I-NEXT: call foo@plt
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; RV64I-NEXT: srli a1, a0, 1
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; RV64I-NEXT: and a1, a1, s0
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; RV64I-NEXT: sub a0, a0, a1
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; RV64I-NEXT: and a1, a0, s1
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; RV64I-NEXT: srli a0, a0, 2
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; RV64I-NEXT: and a0, a0, s1
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: srli a1, a0, 4
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: and a0, a0, s2
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; RV64I-NEXT: mul a0, a0, s3
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; RV64I-NEXT: srli a0, a0, 56
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; RV64I-NEXT: bnez a0, .LBB6_1
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; RV64I-NEXT: # %bb.2: # %bb7
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; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
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; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
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; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
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; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
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; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 48
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; RV64I-NEXT: ret
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;
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; RV64ZBB-LABEL: test7:
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; RV64ZBB: # %bb.0: # %bb
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; RV64ZBB-NEXT: addi sp, sp, -16
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; RV64ZBB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64ZBB-NEXT: sraw a0, a0, a1
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; RV64ZBB-NEXT: .LBB6_1: # %bb2
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; RV64ZBB-NEXT: # =>This Inner Loop Header: Depth=1
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; RV64ZBB-NEXT: call foo@plt
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; RV64ZBB-NEXT: cpop a0, a0
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; RV64ZBB-NEXT: bnez a0, .LBB6_1
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; RV64ZBB-NEXT: # %bb.2: # %bb7
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; RV64ZBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64ZBB-NEXT: addi sp, sp, 16
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; RV64ZBB-NEXT: ret
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;
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; NOREMOVAL-LABEL: test7:
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; NOREMOVAL: # %bb.0: # %bb
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; NOREMOVAL-NEXT: addi sp, sp, -16
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; NOREMOVAL-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; NOREMOVAL-NEXT: sraw a0, a0, a1
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; NOREMOVAL-NEXT: .LBB6_1: # %bb2
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; NOREMOVAL-NEXT: # =>This Inner Loop Header: Depth=1
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; NOREMOVAL-NEXT: sext.w a0, a0
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; NOREMOVAL-NEXT: call foo@plt
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; NOREMOVAL-NEXT: cpop a0, a0
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; NOREMOVAL-NEXT: bnez a0, .LBB6_1
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; NOREMOVAL-NEXT: # %bb.2: # %bb7
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; NOREMOVAL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; NOREMOVAL-NEXT: addi sp, sp, 16
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; NOREMOVAL-NEXT: ret
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bb:
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%i = ashr i32 %arg, %arg1
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br label %bb2
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bb2: ; preds = %bb2, %bb
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%i3 = phi i32 [ %i, %bb ], [ %i6, %bb2 ]
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%i4 = tail call signext i64 @foo(i32 signext %i3)
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%i5 = tail call i64 @llvm.ctpop.i64(i64 %i4)
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%i6 = trunc i64 %i5 to i32
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%i7 = icmp eq i32 %i6, 0
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br i1 %i7, label %bb7, label %bb2
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bb7: ; preds = %bb2
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ret void
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}
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declare i64 @llvm.ctpop.i64(i64)
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define void @test8(i32 signext %arg, i32 signext %arg1) nounwind {
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; CHECK-LABEL: test8:
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; CHECK: # %bb.0: # %bb
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sraw a0, a0, a1
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; CHECK-NEXT: .LBB6_1: # %bb2
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; CHECK-NEXT: .LBB7_1: # %bb2
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: call foo@plt
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; CHECK-NEXT: ori a0, a0, -256
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; CHECK-NEXT: bnez a0, .LBB6_1
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; CHECK-NEXT: bnez a0, .LBB7_1
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; CHECK-NEXT: # %bb.2: # %bb7
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; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; CHECK-NEXT: addi sp, sp, 16
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@ -336,12 +427,12 @@ define void @test8(i32 signext %arg, i32 signext %arg1) nounwind {
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; NOREMOVAL-NEXT: addi sp, sp, -16
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; NOREMOVAL-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; NOREMOVAL-NEXT: sraw a0, a0, a1
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; NOREMOVAL-NEXT: .LBB6_1: # %bb2
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; NOREMOVAL-NEXT: .LBB7_1: # %bb2
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; NOREMOVAL-NEXT: # =>This Inner Loop Header: Depth=1
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; NOREMOVAL-NEXT: sext.w a0, a0
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; NOREMOVAL-NEXT: call foo@plt
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; NOREMOVAL-NEXT: ori a0, a0, -256
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; NOREMOVAL-NEXT: bnez a0, .LBB6_1
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; NOREMOVAL-NEXT: bnez a0, .LBB7_1
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; NOREMOVAL-NEXT: # %bb.2: # %bb7
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; NOREMOVAL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; NOREMOVAL-NEXT: addi sp, sp, 16
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@ -372,12 +463,12 @@ define void @test9(i32 signext %arg, i32 signext %arg1) nounwind {
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; CHECK-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sraw a0, a0, a1
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; CHECK-NEXT: li s0, 254
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; CHECK-NEXT: .LBB7_1: # %bb2
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; CHECK-NEXT: .LBB8_1: # %bb2
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: call bar@plt
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; CHECK-NEXT: mv a1, a0
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; CHECK-NEXT: slti a0, a0, 255
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; CHECK-NEXT: blt s0, a1, .LBB7_1
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; CHECK-NEXT: blt s0, a1, .LBB8_1
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; CHECK-NEXT: # %bb.2: # %bb7
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; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; CHECK-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
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@ -391,12 +482,12 @@ define void @test9(i32 signext %arg, i32 signext %arg1) nounwind {
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; NOREMOVAL-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
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; NOREMOVAL-NEXT: sraw a1, a0, a1
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; NOREMOVAL-NEXT: li s0, 254
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; NOREMOVAL-NEXT: .LBB7_1: # %bb2
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; NOREMOVAL-NEXT: .LBB8_1: # %bb2
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; NOREMOVAL-NEXT: # =>This Inner Loop Header: Depth=1
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; NOREMOVAL-NEXT: sext.w a0, a1
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; NOREMOVAL-NEXT: call bar@plt
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; NOREMOVAL-NEXT: slti a1, a0, 255
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; NOREMOVAL-NEXT: blt s0, a0, .LBB7_1
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; NOREMOVAL-NEXT: blt s0, a0, .LBB8_1
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; NOREMOVAL-NEXT: # %bb.2: # %bb7
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; NOREMOVAL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; NOREMOVAL-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
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@ -426,12 +517,12 @@ define void @test10(i32 signext %arg, i32 signext %arg1) nounwind {
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; CHECK-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
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; CHECK-NEXT: sraw a0, a0, a1
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; CHECK-NEXT: fmv.w.x fs0, zero
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; CHECK-NEXT: .LBB8_1: # %bb2
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; CHECK-NEXT: .LBB9_1: # %bb2
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: call baz@plt
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; CHECK-NEXT: feq.s a1, fa0, fs0
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; CHECK-NEXT: fmv.x.w a0, fa0
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; CHECK-NEXT: beqz a1, .LBB8_1
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; CHECK-NEXT: beqz a1, .LBB9_1
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; CHECK-NEXT: # %bb.2: # %bb7
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; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; CHECK-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
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@ -445,13 +536,13 @@ define void @test10(i32 signext %arg, i32 signext %arg1) nounwind {
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; NOREMOVAL-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
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; NOREMOVAL-NEXT: sraw a0, a0, a1
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; NOREMOVAL-NEXT: fmv.w.x fs0, zero
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; NOREMOVAL-NEXT: .LBB8_1: # %bb2
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; NOREMOVAL-NEXT: .LBB9_1: # %bb2
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; NOREMOVAL-NEXT: # =>This Inner Loop Header: Depth=1
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; NOREMOVAL-NEXT: sext.w a0, a0
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; NOREMOVAL-NEXT: call baz@plt
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; NOREMOVAL-NEXT: feq.s a1, fa0, fs0
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; NOREMOVAL-NEXT: fmv.x.w a0, fa0
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; NOREMOVAL-NEXT: beqz a1, .LBB8_1
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; NOREMOVAL-NEXT: beqz a1, .LBB9_1
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; NOREMOVAL-NEXT: # %bb.2: # %bb7
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; NOREMOVAL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; NOREMOVAL-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
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