forked from OSchip/llvm-project
[aarch64][tests] Add tests which show current lack of implicit null support
I will be posting a patch which adds appropriate target support shortly; landing the tests so that the diffs are clear.
This commit is contained in:
Philip Reames
parent
ce0eb81c72
commit
7af4f44c3e
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@ -0,0 +1,422 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -verify-machineinstrs -O3 -mtriple=aarch64-unknown-unknown -enable-implicit-null-checks | FileCheck %s
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; Basic test for implicit null check conversion - this is analogous to the
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; file with the same name in the X86 tree, but adjusted to remove patterns
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; related to memory folding of arithmetic (since aarch64 doesn't), and add
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; a couple of aarch64 specific tests.
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; NOTE: Currently negative tests as these are being precommitted before
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; the changes to enable.
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define i32 @imp_null_check_load_fallthrough(i32* %x) {
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; CHECK-LABEL: imp_null_check_load_fallthrough:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB0_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ldr w0, [x0]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB0_2: // %is_null
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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not_null:
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%t = load i32, i32* %x
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ret i32 %t
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is_null:
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ret i32 42
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}
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define i32 @imp_null_check_load_reorder(i32* %x) {
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; CHECK-LABEL: imp_null_check_load_reorder:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB1_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ldr w0, [x0]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB1_2: // %is_null
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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%t = load i32, i32* %x
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ret i32 %t
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}
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define i32 @imp_null_check_unordered_load(i32* %x) {
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; CHECK-LABEL: imp_null_check_unordered_load:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB2_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ldr w0, [x0]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB2_2: // %is_null
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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%t = load atomic i32, i32* %x unordered, align 4
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ret i32 %t
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}
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define i32 @imp_null_check_seq_cst_load(i32* %x) {
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; CHECK-LABEL: imp_null_check_seq_cst_load:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB3_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ldar w0, [x0]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB3_2: // %is_null
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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%t = load atomic i32, i32* %x seq_cst, align 4
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ret i32 %t
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}
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;; Might be memory mapped IO, so can't rely on fault behavior
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define i32 @imp_null_check_volatile_load(i32* %x) {
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; CHECK-LABEL: imp_null_check_volatile_load:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB4_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ldr w0, [x0]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB4_2: // %is_null
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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%t = load volatile i32, i32* %x, align 4
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ret i32 %t
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}
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define i8 @imp_null_check_load_i8(i8* %x) {
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; CHECK-LABEL: imp_null_check_load_i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB5_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ldrb w0, [x0]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB5_2: // %is_null
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i8* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i8 42
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not_null:
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%t = load i8, i8* %x
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ret i8 %t
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}
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define i256 @imp_null_check_load_i256(i256* %x) {
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; CHECK-LABEL: imp_null_check_load_i256:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB6_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ldp x8, x1, [x0]
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; CHECK-NEXT: ldp x2, x3, [x0, #16]
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; CHECK-NEXT: mov x0, x8
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB6_2: // %is_null
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: mov x1, xzr
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; CHECK-NEXT: mov x2, xzr
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; CHECK-NEXT: mov x3, xzr
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i256* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i256 42
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not_null:
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%t = load i256, i256* %x
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ret i256 %t
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}
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define i32 @imp_null_check_gep_load(i32* %x) {
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; CHECK-LABEL: imp_null_check_gep_load:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB7_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ldr w0, [x0, #128]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB7_2: // %is_null
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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%x.gep = getelementptr i32, i32* %x, i32 32
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%t = load i32, i32* %x.gep
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ret i32 %t
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}
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define i32 @imp_null_check_add_result(i32* %x, i32 %p) {
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; CHECK-LABEL: imp_null_check_add_result:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB8_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ldr w8, [x0]
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; CHECK-NEXT: add w0, w8, w1
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB8_2: // %is_null
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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%t = load i32, i32* %x
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%p1 = add i32 %t, %p
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ret i32 %p1
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}
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; Can hoist over a potential faulting instruction as long as we don't
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; change the conditions under which the instruction faults.
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define i32 @imp_null_check_hoist_over_udiv(i32* %x, i32 %a, i32 %b) {
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; CHECK-LABEL: imp_null_check_hoist_over_udiv:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB9_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ldr w8, [x0]
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; CHECK-NEXT: udiv w9, w1, w2
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; CHECK-NEXT: add w0, w8, w9
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB9_2: // %is_null
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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%p1 = udiv i32 %a, %b
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%t = load i32, i32* %x
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%res = add i32 %t, %p1
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ret i32 %res
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}
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define i32 @imp_null_check_hoist_over_unrelated_load(i32* %x, i32* %y, i32* %z) {
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; CHECK-LABEL: imp_null_check_hoist_over_unrelated_load:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB10_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ldr w8, [x1]
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; CHECK-NEXT: ldr w0, [x0]
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; CHECK-NEXT: str w8, [x2]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB10_2: // %is_null
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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%t0 = load i32, i32* %y
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%t1 = load i32, i32* %x
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store i32 %t0, i32* %z
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ret i32 %t1
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}
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define i32 @imp_null_check_gep_load_with_use_dep(i32* %x, i32 %a) {
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; CHECK-LABEL: imp_null_check_gep_load_with_use_dep:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB11_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ldr w8, [x0]
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; CHECK-NEXT: add w9, w0, w1
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; CHECK-NEXT: add w8, w9, w8
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; CHECK-NEXT: add w0, w8, #4 // =4
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB11_2: // %is_null
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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%x.loc = getelementptr i32, i32* %x, i32 1
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%y = ptrtoint i32* %x.loc to i32
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%b = add i32 %a, %y
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%t = load i32, i32* %x
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%z = add i32 %t, %b
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ret i32 %z
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}
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define i32 @imp_null_check_load_fence1(i32* %x) {
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; CHECK-LABEL: imp_null_check_load_fence1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB12_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: dmb ishld
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; CHECK-NEXT: ldr w0, [x0]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB12_2: // %is_null
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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fence acquire
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%t = load i32, i32* %x
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ret i32 %t
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}
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define i32 @imp_null_check_load_fence2(i32* %x) {
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; CHECK-LABEL: imp_null_check_load_fence2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB13_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: ldr w0, [x0]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB13_2: // %is_null
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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fence seq_cst
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%t = load i32, i32* %x
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ret i32 %t
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}
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define void @imp_null_check_store(i32* %x) {
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; CHECK-LABEL: imp_null_check_store:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB14_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: mov w8, #1
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; CHECK-NEXT: str w8, [x0]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB14_2: // %is_null
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret void
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not_null:
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store i32 1, i32* %x
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ret void
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}
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define void @imp_null_check_unordered_store(i32* %x) {
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; CHECK-LABEL: imp_null_check_unordered_store:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB15_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: mov w8, #1
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; CHECK-NEXT: str w8, [x0]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB15_2: // %is_null
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret void
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not_null:
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store atomic i32 1, i32* %x unordered, align 4
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ret void
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}
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define i32 @imp_null_check_neg_gep_load(i32* %x) {
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; CHECK-LABEL: imp_null_check_neg_gep_load:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB16_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ldur w0, [x0, #-128]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB16_2: // %is_null
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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%x.gep = getelementptr i32, i32* %x, i32 -32
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%t = load i32, i32* %x.gep
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ret i32 %t
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}
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!0 = !{}
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