forked from OSchip/llvm-project
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.
llvm-svn: 140974
This commit is contained in:
Craig Topper
parent
7de05027a5
commit
7aea69d949
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@ -866,11 +866,10 @@ class BinOpMI8_F<string mnemonic, X86TypeInfo typeinfo,
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// BinOpAI - Instructions like "add %eax, %eax, imm".
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class BinOpAI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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Register areg>
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Register areg, string operands>
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: ITy<opcode, RawFrm, typeinfo,
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(outs), (ins typeinfo.ImmOperand:$src),
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mnemonic, !strconcat("{$src, %", areg.AsmName, "|%",
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areg.AsmName, ", $src}"), []> {
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mnemonic, operands, []> {
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let ImmT = typeinfo.ImmEncoding;
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let Uses = [areg];
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let Defs = [areg];
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@ -935,10 +934,14 @@ multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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def #NAME#32mi : BinOpMI_RMW<mnemonic, Xi32, opnode, MemMRM>;
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def #NAME#64mi32 : BinOpMI_RMW<mnemonic, Xi64, opnode, MemMRM>;
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def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL>;
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def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX>;
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def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX>;
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def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX>;
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def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL,
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"{$src, %al|AL, $src}">;
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def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX,
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"{$src, %ax|AX, $src}">;
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def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX,
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"{$src, %eax|EAX, $src}">;
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def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX,
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"{$src, %rax|RAX, $src}">;
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}
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}
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@ -1002,10 +1005,14 @@ multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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def #NAME#32mi : BinOpMI_RMW_FF<mnemonic, Xi32, opnode, MemMRM>;
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def #NAME#64mi32 : BinOpMI_RMW_FF<mnemonic, Xi64, opnode, MemMRM>;
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def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL>;
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def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX>;
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def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX>;
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def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX>;
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def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL,
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"{$src, %al|AL, $src}">;
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def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX,
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"{$src, %ax|AX, $src}">;
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def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX,
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"{$src, %eax|EAX, $src}">;
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def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX,
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"{$src, %rax|RAX, $src}">;
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}
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}
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@ -1065,10 +1072,14 @@ multiclass ArithBinOp_F<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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def #NAME#32mi : BinOpMI_F<mnemonic, Xi32, opnode, MemMRM>;
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def #NAME#64mi32 : BinOpMI_F<mnemonic, Xi64, opnode, MemMRM>;
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def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL>;
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def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX>;
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def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX>;
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def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX>;
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def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL,
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"{$src, %al|AL, $src}">;
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def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX,
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"{$src, %ax|AX, $src}">;
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def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX,
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"{$src, %eax|EAX, $src}">;
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def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX,
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"{$src, %rax|RAX, $src}">;
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}
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}
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@ -1126,9 +1137,13 @@ let Defs = [EFLAGS] in {
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def TEST32mi : BinOpMI_F<"test", Xi32, X86testpat, MRM0m, 0xF6>;
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def TEST64mi32 : BinOpMI_F<"test", Xi64, X86testpat, MRM0m, 0xF6>;
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def TEST8i8 : BinOpAI<0xA8, "test", Xi8 , AL>;
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def TEST16i16 : BinOpAI<0xA8, "test", Xi16, AX>;
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def TEST32i32 : BinOpAI<0xA8, "test", Xi32, EAX>;
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def TEST64i32 : BinOpAI<0xA8, "test", Xi64, RAX>;
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def TEST8i8 : BinOpAI<0xA8, "test", Xi8 , AL,
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"{$src, %al|AL, $src}">;
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def TEST16i16 : BinOpAI<0xA8, "test", Xi16, AX,
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"{$src, %ax|AX, $src}">;
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def TEST32i32 : BinOpAI<0xA8, "test", Xi32, EAX,
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"{$src, %eax|EAX, $src}">;
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def TEST64i32 : BinOpAI<0xA8, "test", Xi64, RAX,
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"{$src, %rax|RAX, $src}">;
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}
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@ -877,22 +877,22 @@ def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
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/// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
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/// 32-bit offset from the PC. These are only valid in x86-32 mode.
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def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
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"mov{b}\t{$src, %al|%al, $src}", []>,
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"mov{b}\t{$src, %al|AL, $src}", []>,
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Requires<[In32BitMode]>;
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def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
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"mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize,
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"mov{w}\t{$src, %ax|AL, $src}", []>, OpSize,
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Requires<[In32BitMode]>;
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def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
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"mov{l}\t{$src, %eax|%eax, $src}", []>,
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"mov{l}\t{$src, %eax|EAX, $src}", []>,
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Requires<[In32BitMode]>;
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def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
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"mov{b}\t{%al, $dst|$dst, %al}", []>,
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"mov{b}\t{%al, $dst|$dst, AL}", []>,
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Requires<[In32BitMode]>;
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def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
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"mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize,
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"mov{w}\t{%ax, $dst|$dst, AL}", []>, OpSize,
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Requires<[In32BitMode]>;
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def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
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"mov{l}\t{%eax, $dst|$dst, %eax}", []>,
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"mov{l}\t{%eax, $dst|$dst, EAX}", []>,
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Requires<[In32BitMode]>;
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// FIXME: These definitions are utterly broken
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@ -901,13 +901,13 @@ def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
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// in question.
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/*
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def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
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"mov{q}\t{$src, %rax|%rax, $src}", []>;
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"mov{q}\t{$src, %rax|RAX, $src}", []>;
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def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
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"mov{q}\t{$src, %rax|%rax, $src}", []>;
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"mov{q}\t{$src, %rax|RAX, $src}", []>;
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def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
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"mov{q}\t{%rax, $dst|$dst, %rax}", []>;
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"mov{q}\t{%rax, $dst|$dst, RAX}", []>;
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def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
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"mov{q}\t{%rax, $dst|$dst, %rax}", []>;
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"mov{q}\t{%rax, $dst|$dst, RAX}", []>;
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*/
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@ -1153,11 +1153,11 @@ def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
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}
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def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
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"xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
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"xchg{w}\t{$src, %ax|AX, $src}", []>, OpSize;
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def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
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"xchg{l}\t{$src, %eax|%eax, $src}", []>;
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"xchg{l}\t{$src, %eax|EAX, $src}", []>;
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def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
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"xchg{q}\t{$src, %rax|%rax, $src}", []>;
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"xchg{q}\t{$src, %rax|RAX, $src}", []>;
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@ -20,3 +20,60 @@
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# CHECK: in AL, DX
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0xec
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# CHECK: nop
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0x90
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# CHECK: xchg EAX, R8D
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0x41 0x90
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# CHECK: xchg RAX, R8
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0x49 0x90
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# CHECK: add AL, 0
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0x04 0x00
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# CHECK: add AX, 0
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0x66 0x05 0x00 0x00
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# CHECK: add EAX, 0
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0x05 0x00 0x00 0x00 0x00
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# CHECK: add RAX, 0
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0x48 0x05 0x00 0x00 0x00 0x00
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# CHECK: adc AL, 0
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0x14 0x00
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# CHECK: adc AX, 0
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0x66 0x15 0x00 0x00
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# CHECK: adc EAX, 0
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0x15 0x00 0x00 0x00 0x00
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# CHECK: adc RAX, 0
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0x48 0x15 0x00 0x00 0x00 0x00
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# CHECK: cmp AL, 0
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0x3c 0x00
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# CHECK: cmp AX, 0
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0x66 0x3d 0x00 0x00
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# CHECK: cmp EAX, 0
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0x3d 0x00 0x00 0x00 0x00
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# CHECK: cmp RAX, 0
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0x48 0x3d 0x00 0x00 0x00 0x00
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# CHECK: test AL, 0
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0xa8 0x00
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# CHECK: test AX, 0
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0x66 0xa9 0x00 0x00
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# CHECK: test EAX, 0
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0xa9 0x00 0x00 0x00 0x00
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# CHECK: test RAX, 0
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0x48 0xa9 0x00 0x00 0x00 0x00
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@ -309,5 +309,59 @@
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# CHECK: invvpid (%rax), %rax
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0x66 0x0f 0x38 0x81 0x00
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# CHECK: nop
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0x90
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# CHECK: xchgl %r8d, %eax
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0x41 0x90
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# CHECK: xchgq %r8, %rax
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0x49 0x90
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# CHECK: addb $0, %al
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0x04 0x00
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# CHECK: addw $0, %ax
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0x66 0x05 0x00 0x00
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# CHECK: addl $0, %eax
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0x05 0x00 0x00 0x00 0x00
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# CHECK: addq $0, %rax
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0x48 0x05 0x00 0x00 0x00 0x00
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# CHECK: adcb $0, %al
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0x14 0x00
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# CHECK: adcw $0, %ax
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0x66 0x15 0x00 0x00
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# CHECK: adcl $0, %eax
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0x15 0x00 0x00 0x00 0x00
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# CHECK: adcq $0, %rax
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0x48 0x15 0x00 0x00 0x00 0x00
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# CHECK: cmpb $0, %al
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0x3c 0x00
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# CHECK: cmpw $0, %ax
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0x66 0x3d 0x00 0x00
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# CHECK: cmpl $0, %eax
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0x3d 0x00 0x00 0x00 0x00
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# CHECK: cmpq $0, %rax
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0x48 0x3d 0x00 0x00 0x00 0x00
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# CHECK: testb $0, %al
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0xa8 0x00
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# CHECK: testw $0, %ax
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0x66 0xa9 0x00 0x00
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# CHECK: testl $0, %eax
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0xa9 0x00 0x00 0x00 0x00
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# CHECK: testq $0, %rax
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0x48 0xa9 0x00 0x00 0x00 0x00
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@ -327,3 +327,60 @@
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# CHECK: invvpid (%eax), %eax
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0x66 0x0f 0x38 0x81 0x00
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# CHECK: nop
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0x90
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# CHECK: addb $0, %al
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0x04 0x00
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# CHECK: addw $0, %ax
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0x66 0x05 0x00 0x00
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# CHECK: addl $0, %eax
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0x05 0x00 0x00 0x00 0x00
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# CHECK: adcb $0, %al
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0x14 0x00
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# CHECK: adcw $0, %ax
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0x66 0x15 0x00 0x00
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# CHECK: adcl $0, %eax
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0x15 0x00 0x00 0x00 0x00
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# CHECK: cmpb $0, %al
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0x3c 0x00
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# CHECK: cmpw $0, %ax
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0x66 0x3d 0x00 0x00
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# CHECK: cmpl $0, %eax
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0x3d 0x00 0x00 0x00 0x00
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# CHECK: testb $0, %al
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0xa8 0x00
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# CHECK: testw $0, %ax
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0x66 0xa9 0x00 0x00
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# CHECK: testl $0, %eax
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0xa9 0x00 0x00 0x00 0x00
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# CHECK: movb 0, %al
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0xa0 0x00 0x00 0x00 0x00
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# CHECK: movw 0, %ax
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0x66 0xa1 0x00 0x00 0x00 0x00
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# CHECK: movl 0, %eax
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0xa1 0x00 0x00 0x00 0x00
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# CHECK: movb %al, 0
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0xa2 0x00 0x00 0x00 0x00
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# CHECK: movw %ax, 0
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0x66 0xa3 0x00 0x00 0x00 0x00
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# CHECK: movl %eax, 0
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0xa3 0x00 0x00 0x00 0x00
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